CXA3266Q Sony, CXA3266Q Datasheet
CXA3266Q
Specifications of CXA3266Q
Related parts for CXA3266Q
CXA3266Q Summary of contents
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... PLL IC for LCD Monitor/Projector Description The CXA3266Q is a PLL IC for LCD monitors/projectors with built-in phase detector, charge pump, VCO and counter. The various internal settings are performed by serial data via a 3-line bus. Applicable LCD monitor/projector resolutions are NTSC, PAL, VGA, SVGA, XGA, SXGA and UXGA etc. ...
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Pin Configuration (Top View) IOGND VOCLP PLLV CC PLLGND VCOV CC VCOGND VCOHGND IREF RC2 RC1 IRGND IRV ...
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Absolute Maximum Ratings ° ( Supply voltage IOV CC VCOV IOGND, DGND, TTLGND, VCOHGND, PLLGND, VCOGND, IRGND Input voltage VCOH, VCOL, SYNCH, SYNCL, VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS, VOCLP RC2 Output current SEROUT, DIVOUT, ...
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Block Diagram - 4 - ...
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Pin Description Pin No. Symbol 1 IOV CC 2 IOGND 3 VCOH 4 VCOL 5 VCO 6 HOLD 7 SYNCH 8 SYNCL 9 SYNC 10 SENABLE 11 SCLK 12 SDATA 13 TLOAD SEROUT 16 DIVOUT 17 UNLOCK ...
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Pin No. Symbol 38 VOCLP 39 PLLV CC 40 PLLGND 41 VCOV CC 42 VCOGND 43 VCOHGND 44 IREF 45 RC2 46 RC1 47 IRGND 48 IRV CC Pin Description and I/O Pin Equivalent Circuit Pin Reference Symbol I/O No. ...
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Pin Reference Symbol I/O No. voltage level 41 VCOV 5V — VCOGND — VCOHGND — IRGND — IRV — VCOH I PECL 4 VCOL I PECL 7 SYNCH I ...
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Pin Reference Symbol I/O No. voltage level 5 VCO I TTL 6 HOLD I TTL 9 SYNC I TTL 10 SENABLE I TTL 11 SCLK I TTL 12 SDATA I TTL 13 TLOAD I TTL Equivalent circuit IOV CC 40k ...
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Pin Reference Symbol I/O No. voltage level TTL Clamp 38 VOCLP I voltage Equivalent circuit IOV CC 40k 192 14 IOGND TTLV 3.5k TTLGND - 9 - Description Chip select. When Low, all circuits ...
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Pin Reference Symbol I/O No. voltage level 15 SEROUT O TTL 16 DIVOUT O TTL 20 CLK/2N O TTL 21 CLK/2 O TTL 22 CLKN O TTL 23 CLK O TTL 24 DSYNC O TTL 17 UNLOCK O TTL Equivalent ...
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Pin Reference Symbol I/O No. voltage level 29 CLK/2L O PECL 30 CLK/2H O PECL 31 CLKL O PECL 32 CLKH O PECL 33 DSYNCL O PECL 34 DSYNCH O PECL PECLV CC 35 VBB O – 1.7V 44 IREF ...
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Pin Reference Symbol I/O No. voltage level 45 RC2 — 2.0 to 4.4V 46 RC1 — 2.1V Equivalent circuit IRV IRGND IOGND - 12 - Description External pin for LPF. See the Recommended Operating Circuit for the ...
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Control Register Table Register Register DATA7 No. Name MSB register 1 read no Register 1 VCO DIVREG1 DIV Bit 7 register read no Register 2 DIVREG2 register read no Register 3 CENFREREG register 15 read no Register 4 COARSE DELAYREG ...
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Electrical Characteristics ° ( 5V, GND = 0V) CC Item Current consumption (excluding output current) Current consumption 1 Current consumption 2 Current consumption 3 Digital input Digital High level input voltage (PECL) Digital Low level ...
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Item UNLOCK output UNLOCK output current Iunlock SYNC input SYNC input frequency range Fin DSYNC output DSYNC output coarse delay Rdsync1 time setting resolution (upper) DSYNC output coarse delay time Td1 (upper) DSYNC output fine delay time Rdsync2 setting resolution ...
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Item CLK (CLK, CLK/2) output CLK output (PECL) Fclk1PECL DIV = 1/1 frequency range 1 CLK output (PECL) Fclk2PECL DIV = 1/2 frequency range 2 CLK output (PECL) Fclk3PECL DIV = 1/4 frequency range 3 CLK output (PECL) Fclk4PECL DIV ...
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Item CLK (CLK, CLK/2) output CLK vs. SYNC output jitter Tj1p-p (NTSC) CLK vs. SYNC output jitter Tj2p-p (VGA) CLK vs. SYNC output jitter Tj3p-p (SVGA) CLK vs. SYNC output jitter Tj4p-p (XGA) CLK vs. SYNC output jitter Tj5p-p (SXGA) ...
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... PD POL = 1. Phase comparison is performed at the edges. The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped at the front end of the CXA3266Q when inputting a noisy signal. The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.) The PLL UNLOCK signal is output by an open collector ...
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VCO The VCO oscillator frequency covers from 40 to 203MHz. VCO Rear-end Counter The VCO output is frequency divided to 1/1, 1/2, 1/4 or 1/8 by switching 2 bits of control register. The operating range can be expanded to 5 ...
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Delay Sync Output The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can ...
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DSYNC Output Switching during HOLD By switching with a control register, DSYNC output during HOLD period is controlled. Its output status is different according to DSYNC By-pass, DSYNC POL and HOLD signals of the register. The output for each setting ...
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... Programmable counter TTL output OFF function Programmable counter TTL output switching Delay sync output hold function Power Save The CXA3266Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a control register and the chip selector. Step 1 : Chip selector control CS ...
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Readout Circuit (during test mode) The control register contents can be read by serial data from SEROUT. (See the Control Register Timing Chart.) Register : Read out power Readout status Function OFF Programmable Counter Output (during test mode) The programmable ...
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... Control Register Timing Write Mode Many functions of the CXA3266Q can be controlled via a program. Characteristics are changed by setting the internal control register values via a serial interface comprised of three pins : SENABLE (Pin 10), SCLK (Pin 11) and SDATA (Pin 12). The write timing diagram is shown below. ...
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The settings of the frequency divider (2 bits, DIV1 and programmable counter (12 bits, VCODIV) at the rear end of the VCO are transferred in the order shown below. (The data will be set when the three ...
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Read Mode Data can be transferred from the shift register to the data register only when SENABLE is High. Binary data can be read from the data register by inputting SCLK when SENABLE is High. Data is loaded from the ...
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Timing Chart Td1 = 2CLK - 27 - ...
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Td1 = 3CLK - 28 - ...
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Td1 = 4CLK - 29 - ...
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Td1 = 5CLK - 30 - ...
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HOLD Timing SYNC input (SYNC POL = 1) SYNC input (SYNC POL = 0) D/VOUT output (TTL) HOLD input (TTL) CLK output HOLD signal setup time (Ths time from the rising edge of HOLD signal to the falling ...
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Relationship between SYNC Input and DSYNC Output during HOLD SYNC J internal signal DIVOUTN K internal signal CK CLK When the above SYNC internal and DIVOUTN internal signals are input, the DSYNC internal signal is output as shown in the ...
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During HOLD, the output from DSYNC can be controlled by register DSYNC hold. Its output status differs according to the DSYNC polarity or DSYNC By-pass switching. The below diagrams show the relationship with DSYNC output for each SYNC input. (DSYNC ...
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CASE 3 HSYNC (SYNC POL = 1) HOLD input (1) During DSYNC HOLD ON (DSYNC Hold = 1) DSYNC By-pass = 1 DSYNC By-pass = 0 (2) During DSYNC HOLD OFF (DSYNC Hold = 0) DSYNC By-pass = 1 DSYNC ...
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UNLOCK Timing Signal from phase comparator The unlock detect output is an open collector. When unlock detect output S1 goes High, the current I1 is pulled in. The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and ...
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... Charge Pump and Loop Filter Settings The CXA3266Q's charge pump is a constant-current output type as shown below LPF 1/S + The PLL closed loop transmittance is obtained by the following formula. (θo/N)/θr = (KPD • F (S) • KVCO • 1/N • 1/S)/(1 + KPD • F (S) • KVCO • 1/N • 1/S) ... (1) Here, KPD, F (S), and KVCO are ...
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... VCO. In addition to this, however, the loop filter also plays an important element in determining the PLL response characteristics. Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3266Q's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants ...
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Here, ωn and ζ are as follows. ωn characteristic angular frequency : The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency : ...
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... Next, the various parameters inside an actual CXA3266Q are obtained. The CXA3266Q's charge pump output block and the LPF circuit are as follows 100µA or 200µA or 400µA or 800µA 100µA or 200µA or 400µA or 800µA First, KPD is as follows. ...
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... SXGA 1280 × 1024 91.15 156.96 400 UXGA 1600 × 1200 81.23 175.46 800 UXGA 1600 × 1200 93.72 202.44 800 * Consult your Sony representative for use other than noted above. (KPD × 2π 100 or 200 or 400 or 800) (when VCO DIV = 1/1, KVCO/2π = 75) (when VCO DIV = 1/2, KVCO/2π ...
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... CLK Jitter Evaluation Method The regenerated CLK is obtained by applying Hsync to the CXA3266Q. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger. Hsync Pulse Generator H Sync Computer signal Hsync CLK Trigger The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure ...
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Example of Representative Characteristics K characteristics VCO 250 200 150 100 50 0 1.5 2.0 2.5 3.0 VCO control voltage [V] Fine delay Td2 vs. Fine delay bit +75° +25° –25°C 32 ...
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... Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during high-speed operation. Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3266Q PWB.) The voltage applied to VOCLP pin must be supplied from the stabilized power supplies (3-pin regulator etc.) because of the construction of internal circuit ...
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Recommended PECL I/O circuit The peripheral circuits mainly use PECL for digital input and output. Of course, PECL and TTL can also be mixed. In this case, disable the TTL outputs with the control registers. GND ...
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Recommended TTL I/O circuit The peripheral circuits mainly use TTL for digital input and output. Of course, PECL and TTL can also be mixed IOGND VOCLP 38 39 PLLV CC PLLGND 40 41 VCOV CC 42 ...
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... When connecting the PLL output to A/D converters with built-in demultiplex function such as the CXA3246Q/ CXA3276Q/CXA3256R/CXA3286R (Sony), a simple system can be configured by connecting the CLK (PECL) and CLKN (PECL) outputs of the CXA3266Q to the CLK (PECL) and CLKN (PECL) inputs of each A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3266Q to the RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively (when the PLL counter value even number) ...
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... CXA3266Q and Sony ADC (Demultiplex Mode) Timing : 120MHz specification The CXA3266Q and CXA3246Q/CXA3256R timings are shown below. Here, the important timings are as follows. (The clock cycle is labeled as T.) For the A/D converters Clock input vs. reset input The setup time is T – 1.1ns and the hold time is 0.3ns, satisfying the A/D converter specifications. ...
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... A/D converters from different lots, and are defined for all operating temperatures and all operating supply voltages. See the CXA3276Q/CXA3286R data sheets for a detailed description.) For the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3266Q vs. 1/2 clock output of A/D converter The setup time is T – 3.2ns and the hold time is T – 3.7ns. CXA3266Q ...
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... Connecting the CXA3266Q with Sony ADC (Straight Mode) When connecting the PLL output to A/D converters such as the CXA3246Q/CXA3276Q/CXA3256R/CXA3286R (Sony), a simple system can be configured as shown below. Wiring Diagram PLL CXA3266Q VIN CLK (PECL) CLKN (PECL) ADC CXA3246Q CXA3276Q CXA3256R CXA3286R VIN CLK (PECL) ...
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... CXA3266Q and Sony ADC (Straight Mode) Timing : 100MHz specification The CXA3266Q and CXA3246Q/CXA3256R timings are shown below. Here, the important timings are as follows. (The clock cycle is labeled as T.) For the CMOS LOGIC at the rear end of the A/D converters A/D converter data output vs. clock output from CXA3266Q The setup time is T – ...
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... CXA3266Q and Sony ADC (Straight Mode) Timing : 100MHz specification The CXA3266Q and CXA3276Q/CXA3286R timings are shown below. Here, the important timings are as follows. (The clock cycle is labeled as T.) For the CMOS LOGIC at the rear end of the A/D converters A/D converter data output vs. clock output from CXA3266Q The setup time is T – ...
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... CXA3266Q-PWB (CXA3266Q Evaluation Board) The CXA3266Q – PWB is an evaluation board for the CXA3266Q PLL-IC. This board makes it possible to easily evaluate the CXA3266Q's performance using the supplied control program (Note : IBM PC/AT, MS-DOS 5.0 or newer US mode specifications). Features Two input level (TTL and PECL) SYNC input Two output level (TTL and PECL) CLK, CLK2 and DSYNC output Supply voltage : + 5 ...
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Setting Methods and Notes on Operation Input Pins This PWB supports TTL single and PECL complementary input. Input pins : SYNC : TTL level input 120kHz SYNCL : PECL Low level input 120kHz SYNCH : PECL ...
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... Connect the power cable and supply power to the CXA3266Q-PWB. 4. Start the program (1) Boot the personal computer and then shift to the directory containing the program. (2) Set MS-DOS to US mode. → US Return or Enter (3) Input the program name. → CXA3266Q Return or Enter → Move to the program screen. 13 pin 2 : SCLK pin 3 : SDATA ...
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Description of program screen (1) Setting of each function When the program is started, the following initial screen is displayed. Coarse Delay 00 Polarity SYNC DSYNC O/P Enable DIVOUT UNLOCK ON ON DSYNC Functions DELAY ...
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... Return or Enter key. (Note : The operating range of the CXA3266Q is from 256 to 4096.) The value can also be incremented or decremented by one step by pressing the Page Up or Page Down key, respectively. ...
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Power SCAN : This is the control register read setting. When this is ON, the control register serial data is output from SEROUT (Pin 15). This should normally be set to OFF. SYNTH : This is the enable/disable setting for ...
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... Description of readout mode This program has a function (readout mode) that reads the contents written to the control registers from the CXA3266Q SEROUT (Pin 15) and displays these contents on the screen. This function is described below. (a) Set SCAN the function setting screen. (b) Press the S key. ...
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Substrate Pattern (parts surface) Substrate Pattern (solder surface ...
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... VCO VCOL VCOH BNC3 BNC2 BNC1 CXA3266Q PWB BNC4 SYNCH S1 S2 BNC5 SYNCL IC1 BNC6 SYNC PR2 PR3 PR4 PR11 SEROUT DIVOUT UNLOCK CLK/2N Silk Screen (parts surface Silk Screen (solder surface VCC GND C21 33µ ...
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PWB Circuit Diagram - 61 - ...
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... DETAIL A SONY CODE EIAJ CODE JEDEC CODE 48PIN QFP (PLASTIC 0.15 0.3 – 0.1 0.24 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-48P-L04 QFP048-P-1212 LEAD MATERIAL PACKAGE MASS - 62 - 0.15 – 0.05 A 0.1 – 0.1 + 0.35 2.2 – 0.15 M EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.7g Sony Corporation + 0.1 0.15 + 0.2 ...