MPC948 Freescale Semiconductor, Inc, MPC948 Datasheet
MPC948
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MPC948 Summary of contents
Page 1
... L2 cache of a PowerPC 620 based system. The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies ...
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... MPC948 PECL_CLK PECL_CLK TTL_CLK TTL_CLK_Sel Sync_OE Tristate VCCO GND 28 MPC948 Q1 29 VCCO GND Figure 2. 32–Lead Pinout (Top View) TTL_CLK Sync_OE Q MOTOROLA 0 1 Figure 1. Logic Diagram GND VCCO GND ...
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... V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the V CMR range and the input swing lies within the V PP specification. 2. The MPC948 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). ...
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... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC948 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...
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... F D É É SECTION AE– MPC948 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...
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... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 MPC948/D TIMING SOLUTIONS BR1333 — Rev 6 ...