MT8880CP Zarlink Semiconductor, MT8880CP Datasheet
MT8880CP
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MT8880CP Summary of contents
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... MT8880CP1 MT8880CS1 MT8880CE1 MT8880CN1 MT8880CSR MT8880CPR MT8880CPR1 MT8880CSR1 provides low power dissipation and high reliability. The DTMF receiver is based upon the industry standard MT8870 monolithic DTMF receiver; the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing ...
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... IRQ/CP Φ2 R RS0 24 PIN SSOP Figure 2 - Pin Connections Description /2 is used to bias inputs at mid-rail (see Fig. 13). DD Ω resistor to VSS if crystal oscillator is used. 2 Zarlink Semiconductor Inc. Data Sheet • VRef VSS 7 23 OSC1 ...
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... Figure 4 shows the necessary connections for a differential input configuration. VOLTAGE GAIN (A MT8880C Description /2. Provision is made for connection of a feedback resistor to the op- DD IN+ IN MT8880C ) = Figure 3 - Single-Ended Input Configuration 3 Zarlink Semiconductor Inc. Data Sheet detected at St TSt Ref ...
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... IN Ref MT8880C diff) = R5/ diff (1/ωC) Figure 4 - Differential Input Configuration ), v reaches the threshold (V GTP continues to drive high as long as ESt remains high. Finally, after Zarlink Semiconductor Inc. Data Sheet ) of the steering logic to register the TSt ...
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... V GTA (R1C1 GTP DD Figure 5 - Basic Steering Circuit REC DP GTP GTA ). This may be necessary to meet system specifications which place both GTA 5 Zarlink Semiconductor Inc. Data Sheet the delayed ) TSt - TSt is the minimum signal duration REC ...
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... GTP (RpC1 GTA (R1R2) / ( decreasing tGTA; (tGTP > tGTA) Figure 6 - Guard Time Adjustment The call progress tone input and DTMF input are common, 6 Zarlink Semiconductor Inc. Data Sheet )] TSt /V ) TSt -V ) TSt /V ) TSt with a long t REC DO ...
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... 1633 1633 1633 LOGIC LOW, 1= LOGIC HIGH Figure 7 - Functional Encode/Decode Table 7 Zarlink Semiconductor Inc. Data Sheet ) are referred to as Low Group and HIGH ...
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... FREQUENCY (Hz) = Reject = May Accept = Accept Figure 8 - Call Progress Response REC ID TONE # GTP t GTA t PStRX # n t PStb3 Figure 9 - Receiver Timing Diagram 8 Zarlink Semiconductor Inc. Data Sheet 750 TONE TONE # TSt ...
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... The total harmonic distortion for a single tone can be calculated using MT8880C Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 10 - Spectrum Plot 9 Zarlink Semiconductor Inc. Data Sheet ...
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... GUARD TIME, TONE PRESENT. GTP t GUARD TIME, TONE ABSENT. GTA THD(%) = MT8880C Figure 11 - Description of Timing Events .... 100 V fundamental Equation 1. THD (%) For a Single Tone 10 Zarlink Semiconductor Inc. Data Sheet .... the sum of all the IMD ...
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... IMD Equation 2. THD (%) For a Dual Tone OUTPUT FREQUENCY (Hz) SPECIFIED ACTUAL L1 697 699.1 L2 770 766.2 L3 852 847.4 L4 941 948.0 H1 1209 1215.9 H2 1336 1331.7 H3 1477 1471.9 H4 1633 1645.0 11 Zarlink Semiconductor Inc. Data Sheet %ERROR +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0.73 ...
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... OSC1 OSC2 OSC1 OSC2 3.579545 MHz Figure 12 - Common Crystal Connection RS0 R/W FUNCTION 0 0 Write to Transmit Data Register 0 1 Read from Receive Data Register 1 0 Write to Control Register 1 1 Read from Status Register Table 2 - Internal Register Functions 12 Zarlink Semiconductor Inc. Data Sheet MT8880C ...
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... A logic ‘1’ selects Control Register B on the next Write cycle to the Control Register address. Subsequent Write cycles to the Control Register are directed back to Control Register A. 13 Zarlink Semiconductor Inc. Data Sheet . will be ...
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... Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Table 7 - Status Register Description 14 Zarlink Semiconductor Inc. Data Sheet STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode ...
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... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8880 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 15 Zarlink Semiconductor Inc. Data Sheet µ ...
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... Test load for D0-D3 pins 6802 IRQ Address Peripheral decode VMA R/W E Data Figure 15 - MT8880C to 6802 Interface MT8880C TEST POINT Test load for IRQ/CP pin Figure 14 - Test Circuit +5 V 3.3k 16 Zarlink Semiconductor Inc. Data Sheet 5.0 VDC 3 kΩ MT8880C IRQ RS0 CS R/W Φ2 Data ...
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... CS RS0 R Figure 16 - Application Hints 17 Zarlink Semiconductor Inc. Data Sheet Data ...
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... 3.5 IHO V ILO V 2.2 2.3 TSt V OLO V 4.9 OHO 2.4 2.5 Ref Zarlink Semiconductor Inc. Data Sheet Min. Max. Units 6 V -0 -65 +150 1000 mW Max. Units Test Conditions 5.25 V °C +85 MHz Max. Units Test Conditions ...
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... 100 1 † - Voltages are with respect to ground (V SS ‡ Sym Min. Typ. Max. -29 27.5 +1 869 19 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 0V. SS Units Test Conditions ≤ ...
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... REC t 20 REC PStb3 t 8 PStRX t 50 BST 100 BSTE t 100 PSE 20 Zarlink Semiconductor Inc. Data Sheet =3.579545 MHz. C Units Notes* dB 2,3,6,9 dB 2,3,6,9 2,3,5,9 2,3,5 dB 2,3,4,5,9,10 dB 2,3,4,5,7,9,10 dB 2,3,4,5,8,9,11 ) unless otherwise stated. SS Units Notes -25 dBm Hz @ -25 dBm Hz @ -25 dBm Hz @ -25 dBm dBm Max ...
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... OUT f 3.5759 3.5795 3.5831 C t LHCL t HLCL DHR ± 2 Hz. ± 2%). 21 Zarlink Semiconductor Inc. Data Sheet ‡ Max. Units Conditions -2.1 dBm R =10 kΩ L -4.1 dBm R =10 kΩ =10 kΩ kHz Bandwidth R =10 kΩ ...
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... R Φ2 Φ RS0 RWS R/W DATA BUS MT8880C t CYC Figure 17 - Φ2 Pulse t DDR t RWH t DHR Valid Data Figure 18 - MPU Read Cycle 22 Zarlink Semiconductor Inc. Data Sheet t AH ...
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... AS CS RS0 t RWS R/W DATA BUS MT8880C RWH t t DSW DHW Valid Data Figure 19 - MPU Write Cycle 23 Zarlink Semiconductor Inc. Data Sheet ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...