MC12429 Freescale Semiconductor, Inc, MC12429 Datasheet

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MC12429

Manufacturer Part Number
MC12429
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
High Frequency Clock
Synthesizer
internal VCO will operate over a range of frequencies from 200 to
400MHz. The differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4, or 8. With the output configured to divide the
VCO frequency by 1, and with a 16.000MHz external quartz crystal used
to provide the reference frequency, the output frequency can be specified
in 1MHz steps. The PLL loop filter is fully integrated so that no external
components are required. The output frequency is configured using a
parallel or serial interface.
Functional Description
its frequency reference. The output of the reference oscillator is divided
by 16 before being sent to the phase detector. With a 16MHz crystal, this
provides a reference frequency of 1MHz. Although this data sheet
illustrates functionality only for a 16MHz crystal, any crystal in the
10–25MHz range can be used.
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or
8). This divider extends performance of the part while providing a 50% duty cycle.
in 50Ω to V CC – 2.0V. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase–locked loop to minimize noise induced jitter.
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
programming section for more information.
06/01
Motorola, Inc. 2001
25 to 400MHz Differential PECL Outputs
Fully Integrated Phase–Locked Loop
Minimal Frequency Over–Shoot
Synthesized Architecture
Serial 3–Wire Interface
Parallel Interface for Power–Up
Quartz Crystal Interface
28–Lead PLCC and 32–Lead LQFP Packages
Operates from 3.3V or 5.0V Power Supply
The MC12429 is a general purpose synthesized clock source. Its
The internal oscillator uses the external quartz crystal as the basis of
The VCO within the PLL operates over a range of 200 to 400MHz. Its output is scaled by a divider that is configured by either
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
25ps Peak–to–Peak Output Jitter
1
REV 7
HIGH FREQUENCY PLL
CLOCK SYNTHESIZER
28–LEAD PLCC PACKAGE
32–LEAD LQFP PACKAGE
MC12429
CASE 873A–02
CASE 776–02
FN SUFFIX
FA SUFFIX
Order this document
by MC12429/D

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MC12429 Summary of contents

Page 1

... SEMICONDUCTOR TECHNICAL DATA High Frequency Clock Synthesizer The MC12429 is a general purpose synthesized clock source. Its internal VCO will operate over a range of frequencies from 200 to 400MHz. The differential PECL output can be configured to be the VCO frequency divided With the output configured to divide the VCO frequency by 1, and with a 16 ...

Page 2

... MC12429 V CC FOUT FOUT GND S_CLOCK 26 S_DATA 27 S_LOAD 28 28–Lead PLCC 1 PLL_V XTAL1 XTAL2 OE P_LOAD S_CLOCK S_DATA S_LOAD PLL–V CC PLL–Vcc N/C N/C XTAL1 MOTOROLA V CC TEST GND N[1] 17 N[0] 16 M[8] M[ M[6] 13 M[ M[0] M[1] M[2] M[3] Figure 1. 28–Lead (Top View) ...

Page 3

... This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is connected to +3. PLL_V CC ). Current drain through PLL_V CC GND These pins are the negative supply for the chip and are normally all connected to ground. TIMING SOLUTIONS Function 85mA. 15mA. 3 MC12429 MOTOROLA ...

Page 4

... S_DATA 26 S_CLOCK V CC1 21 +3.3 or 5.0V Figure 3. MC12429 Block Diagram (28–Lead PLCC Pinout) Programming the device amounts to properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: FOUT = (F XTAL 16 Where F XTAL is the crystal frequency the loop divider modulus, and N is the output divider modulus ...

Page 5

... However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MC12429 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin ...

Page 6

... MC12429 FREF PLL 12429 MCNT SCLOCK M COUNTER SHIFT SDATA REG T0 14–BIT T1 T2 T2=T1=1, T0=0: Test Mode (PLL bypass) SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE FOUT pin PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin. ...

Page 7

... APPLICATIONS INFORMATION characterized result a parallel resonant crystal can be used with the MC12429 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies ...

Page 8

... The simplest form of isolation is a power supply filter on the PLL_VCC pin for the MC12429. Figure 6 illustrates a typical power supply filter scheme. The MC12429 is most susceptible to noise with spectral content in the 1KHz to 1MHz range ...

Page 9

... Care must be taken that the measured edge is the edge immediately following the trigger edge. All of the jitter data reported on the MC12429 was collected in this manner. Figure 9 shows the jitter as a function of the output frequency ...

Page 10

... MC12429 –N– –L– 0.010 (0.250 L– NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. ...

Page 11

... N É É É É É É SECTION AE– MC12429 AE AE DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...

Page 12

... JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 12 TIMING SOLUTIONS MC12429/D ...

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