CS4216-KL Cirrus Logic, Inc., CS4216-KL Datasheet
CS4216-KL
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CS4216-KL Summary of contents
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... The ADCs include a digital decimation filter which eliminates the need for external anti-aliasing filters. The DACs include output smoothing filters on-chip. Ordering Information: CS4216-KL CS4216-KQ CDB4216 ...
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... Specifications are subject to change without notice. 2 (AGND, DGND = 0V, all voltages with re- Symbol Digital VD Analog VA +5V; Input Levels: Logic 0 = 0V, A Symbol (Note 1) IDR THD (Note 1) DC Coupled Inputs AC Coupled Inputs (Notes 1,2) (Note 1) CS4216 Min Typ Max Units 4.75 5.0 5.25 4.75 5.0 5. Min Typ Max Units ...
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... Parameter definitions are given at the end of this data sheet. DS83F2 (Continued) Symbol (Note 1) TDR IDR (Note 4) THD (Note 4) (Note 1) (Note 3) (Note 3) (Note 3) (Note 5) (Note 4) (Note 1) (22 kHz to 100 kHz) Operating Power Down (1 kHz) CS4216 Min Typ Max Units Bits - - 0.9 LSB - ...
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... CCLK rising to CDOUT data valid CCLK rising to CDOUT Hi-Z CCLK falling to CCS high Notes: 7. When the CS4216 is in master mode (SSYNC and SCLK outputs), the SCLK duty cycle is 50%. The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf ...
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... tt4 Err1 Err0 ain0 Serial Mode 4. Control Data Serial Port Timing CS4216 *Word Sync Bit 33 Bit 63 Bit 64 (Bit 1) (Bit 32) (Bit 31) Bit 63 Bit 64 Bit 33 (Bit 31) (Bit 1) (Bit 32 tt0 L A tt1 ...
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... Output Capacitance Input Capacitance 6 CLKIN t pd2 SCLK SSYNC (Master Mode VA 5V) A Symbol (Digital Inputs) (High-Z Digital Outputs) C OUT C IN CS4216 t ckl t ckh t pd3 SCLK & SSYNC Output Timing (Master Mode) Min Typ Max VD-1 1.0 VD-0 ...
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... Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS83F2 Symbol (Fs is conversion freq.) Symbol (Fs is conversion freq.) (AGND, DGND = 0V, all voltages with respect to 0V.) Symbol Digital VD Analog VA (Except Supply Pins) (Power Applied) CS4216 Min Typ Max 0 - 0.45Fs -0 0.2 0.45Fs - ...
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... M F2:D O 3/F 2 F3:D I3/F3 4:D I4/M A F5 F6:D I2 Figure 1. Typical Connection Diagram CS4216 + nalog eparate + log supply is use d, rem ove 24 the 2 sistor VA > 1 600 > ...
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... RC filter acts as a charge reserve for the switched-capacitor input and buffers op-amps from a switched-capacitor load. Communication with the CS4216 is via a serial port, with sepa- rate pins for data into the device, and data from the device. The filters and converters operate over a sample rate range of 4 kHz to 50 kHz ...
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... DO pins are up- dated in SM3 and SM4. Reset and Power Down Modes Reset places the CS4216 into a known state and must be held low for at least 50 ms after power hard power down. Reset must also occur when the codec is in master mode and a change in sample frequency is desired ...
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... A/D converters’ output data and status bits. SDOUT goes to a high-impedance state during frames not allocated to the selected CS4216. SCLK clocks data in to and out of the CS4216. The rising edge of SCLK clocks data out on SDOUT. The falling edge latches data on SDIN into the port (SCLK polarity is inverted in Serial Modes 1& ...
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... Sel. SM1 and SM2 Left Right DAC - Right Word M Sel. A/D Gain A/D Gain SM3 CS4216 LA3 LA2 LA1 LA0 RA3 RA2 RA1 RA0 Sets left output attenuation *SM3,4 LA4 is the MSB. 00000 = no attenuation 11111 = -46.5 dB LA0 represents 1.5 dB. *SM3,4 RA4 is the MSB ...
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... Input Sub-frame Bit 21 is set. Control data will not be loaded 0010 - Sync Pulse is incorrect. Causes the analog output to mute. 0011 - SCLK is outside the allowable range. Analog output mutes. CS4216 Version Number 0000 = "A" (see Appendix A) 0001 = "B", "C" (This data sheet ...
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... CLKIN and SCLK to set the internal sample frequency and causes the CS4216 to go into soft power down mode if the SCLK fre- quency drops to <CLKIN/12. Even if only 1 CS4216 is used, the timing for 4 devices must be maintained. Table 2 shows some example sample rates for SM1. Sample Rate ...
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... MF6:DI2 is a general purpose input. The other six multifunction pins are used to select sub-modes under SM3. SM3 is divided into two sub-modes, Master and Slave. In Master sub-mode, the CS4216 gener- ates SSYNC and SCLK, while in Slave sub-mode SSYNC and SCLK must be generated CS4216 ...
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... Slave Sub-Mode (SM3) In SM3, Slave sub-mode is selected by setting MF4: which configures SSYNC and SCLK as inputs to the CS4216. These two sig- nals must be externally derived from CLKIN. In Slave sub-mode, the phase relationship between SCLK/SSYNC and CLKIN cannot be controlled since SCLK and SSYNC are externally derived ...
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... Word A Word B Word A FRAME (n+2) FRAME (n+3) Sub-frame 1 Sub-frame 1 Word B Word A Word B Word A Figure 8. SM3, Master Sub-Mode. LSB Word A 32 CLOCKS Figure 9. Detailed Master Sub-Mode, 64 BPF. CS4216 FRAME (n+3) Sub-frame 1 Word B Word A Word B FRAME (n+4) Sub-frame 1 Word B Word A Word B FRAME (n+4) Sub-frame 1 Word B Word A Word B MSB ...
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... Bits per Frame (Slave Sub-Mode) In Slave sub-mode, MF1:F1 and MF2:F2 select the number of bits per frame which determines how many CS4216’s can occupy one serial port. Table 4 lists the decoding for MF1:F1 and MF2:F2. When set for 64 SCLKs per frame, one device occupies the entire frame ...
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... Sub-frame 1 Sub-frame 2 Word B Word A Word B Word erio b-fram b-fra ord B W ord A W ord B W ord A CS4216 MF8: Word B SFS2 0 FRAME (n+2) Sub-frame 1 MF8: SFS2 Word B Word A Word (n+1) ...
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... In SM4, Slave sub-mode is selected by setting SMODE1,SMODE2 = 01. This mode configures SSYNC and SCLK as inputs to the CS4216. These two signals must be externally derived from CLKIN. Since the CS4216 has no control over the phase relationship of SSYNC and Sub-Fram e ADC - Left W ord ADC - Right W ord ...
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... Ta- ble 8 lists the decoding for time slot selection. In SM4-Slave, the frequency of the incoming SCLK signal, in relation to CLKIN, determines the sample frequency on the CS4216. The CS4216 determines the ratio of SCLK to CLKIN and sets the internal sample frequency accord- MF6: MF7: MF8: ...
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... CS4216 as a simple 17.64 stereo codec: no gain, no attenuation, line inputs 14.70 #1, and not muted. 11.025 8.82 Figure 17 illustrates how to use all the CS4216 7.35 features with a low cost DSP that cannot support the interrupt rate of SM3. Using SM4 (32 bits Left ...
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... SM4 32 BPF MF3:CCLK Micro- Controller MF4:CCS MF5:INT Serial MF1:CDOUT Port MF2:CDIN IRQ RESET MF6:F1 General MF7:F2 Purpose Port MF8:F3 Pins Figure 16. SM4 - Minimum DSP Interface CS4216 43 42 SDIN 1 44 SCLK VD Hard Wired or 34 DIP Switch 31 30 selectable DSP ...
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... SM4 32 BPF 40 MF1:CDOUT 2 RESET 34 MF6:F1 31 MF7:F2 30 MF8:F3 24 VD+ HC597 HC597 A 0 SCLK B ADV C DI1 LCLK RCL D E LCL AIN F ERR0 HC595 G ERR1 CS_STATUS CS_FS HC574 Figure 17. SM4 - Enhanced DSP Interface CS4216 DSP HC597 DIN CS_CONTROL 24+ bit DSP Data Bus DS83F2 ...
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... The CS4216, along with associated analog cir- cuitry, should be positioned in an isolated section of the circuit board, and have its own, separate, ground plane. On the CS4216, the analog and digital grounds are internally connected; there- fore, the AGND and DGND pins must be externally connected with no impedance between them ...
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... ADC and DAC Filter Response Plots Figures shows the overall frequency re- sponse, passband ripple and transition band for the CS4216 ADCs and DACs. Figure 27 shows the DACs’ deviation from linear phase defined as the selected sample frequency and is also the SSYNC frequency. Since the sample frequency is programmable, the filters will adjust to the selected sample frequency ...
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... Digital Supply 1 + Digital Supply 1.0 uF Figure 20. CS4216 Surface Mount Decoupling Layout DS83F2 Figure 19. CS4216 Decoupling Layout Guideline CS4216 + Analog Supply + + Analog Supply + ...
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... Input Frequency (Fs) Figure 25. CS4216 DAC Passband Ripple 28 0.6 0.4 0.2 -0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 0.6 0.7 0.8 0.9 1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0. -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 Figure 24. CS4216 DAC Frequency Response 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 CS4216 Input Frequency (Fs) Figure 22. CS4216ADC Passband Ripple 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Input Frequency (Fs) Input Frequency (Fs) Figure 26. CS4216 DAC Transition Band 0.7 0.8 0.9 1.0 DS83F2 ...
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... Input Frequency (Fs) Figure 27. CS4216 DAC Deviation from Linear Phase DS83F2 CS4216 29 ...
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... NC Top View MF3 MF4 DI3 DI4 DI3 DI4 CCLK CCS CCLK CCS CS4216 SCLK SDOUT SDIN SMODE3 MF1:DO4/F1/CDOUT MF2:DO3/F2/CDIN 34 MF5:DO2/INT 33 DO1 32 MF4:DI4/MA/CCS 31 30 MF3:DI3/F3/CCLK 29 MF6:DI2/ DI1 26 SMODE2 25 24 MF7:SFS1/F2 23 ...
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... Top View MF3 MF4 DI3 DI4 DI3 DI4 CCLK CCS CCLK CCS CS4216 SCLK SDOUT SDIN SMODE3 MF1:DO4/F1/CDOUT MF2:DO3/F2/CDIN MF5:DO2/INT 40 39 DO1 38 MF4:DI4/MA/CCS 37 36 MF3:DI3/F3/CCLK 35 MF6:DI2/ DI1 32 SMODE2 31 30 MF7:SFS1/F2 ...
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... A nominal +2.2 V output for setting the bias level for external analog circuits. Serial Digital Audio Interface Signals SDIN - Serial Port Data In, PIN 42(L), 36(Q). Digital audio data to the DACs and level control information is received by the CS4216 via SDIN. SDOUT - Serial Port Data Out, PIN 43(L), 37(Q). ...
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... In slave mode, the pin reverts to being a general purpose input. MF3:CCLK - Control Data Clock in SM4, PIN 35(L), 29(Q). In serial mode 4 this pin is the control port serial bit clock which latches data from CDIN on the falling edge, and outputs data onto CDOUT on the rising edge. DS83F2 CS4216 33 ...
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... MF7:SFS1 - Sub-Frame Select 1 in SM1/SM2/SM3/SM4-SL, PIN 31(L), 25(Q). In serial modes 1, 2, and 3, MF7:SFS1 helps select the sub-frame that this particular CS4216 is allocated. In slave sub-mode of serial mode 4, this pin is one of two pins used as a sub-frame select when MF6: (128-bit frames). When MF6: this pin is used to select the frame sizes bits ...
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... PDN - Power Down, PIN 13(L), 7(Q). This pin, when low, causes the CS4216 to go into a power down state. RESET should be held low for 50 ms when exiting the power down state to allow time for the voltage reference to settle ...
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... For the ADCs, the deviation of the output code from the mid-scale with the selected input at REFBUF. For the DACs, the deviation of the output from REFBUF with mid-scale input code. Units in LSB’s for the ADCs and volts for the DACs. 36 CS4216 DS83F2 ...
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... Out of Band Energy The ratio of the rms sum of the energy from 0. 2.1 Fs compared to the rms full-scale signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz. DS83F2 CS4216 37 ...
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... APPENDIX A This data sheet describes version 1 of the CS4216. Therefore, this appendix is included to describe the differences between version 0 and version 1. This information is only useful for users that still have version 0 since version 1 devices will supplant the earlier version. The version number is contained in the serial data line, bits SDOUT in SM1-SM3 and, bits CDOUT in SM4 ...
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... BNCs. Digital interfacing is facilitated using one to three of the buffered ribbon cable headers. All four serial modes of the CS4216 and all three modes of the CS4218 are supported using a simple DIP switch which is decoded to select the proper mode and sub-mode. ...
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... Serial Port Format Table 1 lists the DIP switches used to select the serial mode. SPF2 and SPF1 select one the four serial modes of the CS4216 or one of three serial modes for the CS4218. MA selects master ( slave and is only useful in serial modes 3 and 4. The majority of users select ...
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... F1-F3 pins on the CS4216/8 are different between SM3 and SM4 as shown in Table 4 at the end of the data sheets. Table 3 and Table 9 of the CS4216 Data Sheet describe the sample fre- quencies obtained using the on-board oscillator of 11.2896 MHz example, if all DIV switches are off, the sample frequency is 44 ...
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... PAL equations used for decoding. Table 4 shows the CS4216/8 multi-function pin settings for each possible DIP switch configura- tion. Refer to the CS4216/8 data sheets to determine pin settings for sample frequencies. Once a suitable mode has been chosen using the evaluation board, this table will show the hard wire configuration for each multi-function pin ...
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... C36 C35 REFBYP VA 16 LOUT CS4216 15 U1 ROUT 2 RESET 36 MF4 35 MF3 34 MF6 REFGND AGND Figure 1. CS4216 and Power Supplies CDB4216 VA (+5V P6KE C29 AGND C32 604 R27 + 1 uF C31 47.5 k R28 2200 pF NPO C33 R30 47.5 k 2200 pF NPO ...
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... Space for headers are included, J19 and J20, to connect to the LIN2 and RIN2 inputs. To use these headers, the microphone traces must be cut. ANALOG OUTPUTS The CS4216/8 drives the line outputs into filter and then to a pair of BNCs labeled CDB4216 . Another 22 dB DS83DB4 ...
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... R11 U2 LT1013 R17 + 150 R15 R13 10 k C27 56 pF NPO Figure 3. Line Input Buffer CDB4216 CS4216 C19 26 RIN2 C17 0.47 uF 0.01 uF NPO 20 REFBUF C37 0.1 uF C20 28 LIN2 C18 0.47 uF 0.01 uF NPO 0.1 uF CS4216 27 LIN1 C13 0.01 uF NPO 20 REFBUF C37 0 RIN1 C14 0.01 uF NPO 45 ...
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... AUDIO PORT HEADER The CDB4216/8 is primarily designed to evalu- ate the CS4216/8 in single chip mode, i.e. only one codec on the serial bus. This is the factory default state of the CDB4216/8. The audio port header J15 provides all buffered signals necessary to connect to the serial port of a DSP or other controller (see Figure 4) ...
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LB SPF2 SPF1 MA BPF2 BPF1 TS2 TS1 DIV3 DIV2 DIV1 SWX DS83DB4 CDB4216 47 ...
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... In SM3 slave sub-modes, three inputs and + two outputs are functional. In SM4 only DO1 and DI1 are functional. See the CS4216/8 Data Sheet for more details. CLOCKS The CDB4216/8 provides an on-board default clock oscillator of 11.2896 MHz (see Figure 7). ...
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... CDB4216/8 evaluation board. These plots are included to provide an example of how to correctly layout a PCB for the codec. Grounding and Power Y1 C43 R55 33 pF 10M 74HCUO4 Figure 8. Optional Clock Circuit CDB4216 CS4216 CLKIN CLKIN- ...
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Notice in Figure 12 and Figure 13 how the ground plane split is positioned. The split is next to the part - NOT UNDER IT. The AGND and DGND pins are connected to the ground plane fill inside the codec ...
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Design Description ;---------------------------------- Declaration Segment ------------ TITLE CDB4216 PATTERN 4216S_B REVISION 4.0B AUTHOR C. Sanchez, M. Jordan COMPANY Crystal Semiconductor DATE 5/28/93 CHIP _4216s_b PALCE16V8 ;---------------------------------- PIN Declarations --------------- PIN 1 /SPF2 PIN 2 /SPF1 PIN 3 /MA PIN ...
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SPF2 * SPF1 * /MA * /BPF2 * BPF1 * TS2 + SPF2 * SPF1 * /MA * BPF2 * TS2 + SPF2 * SPF1 * MA * DIV3 MF7 = /SPF2 * TS1 + SPF2 * /SPF1 * ...
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Design Description ;---------------------------------- Declaration Segment ------------ TITLE CDB4216 PATTERN 4216L_B REVISION 2.0B AUTHOR C. Sanchez COMPANY Crystal Semiconductor DATE 4/27/93 CHIP _4216l_b PALCE22V10Z ;---------------------------------- PIN Declarations --------------- PIN 1 /SPF2 PIN 2 /SPF1 PIN 3 /MA PIN 4 /BPF2 ...
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SPF2 * /SPF1 * MA + SPF2 * SPF1 * /CCS MF6 = /SPF2 * DI2 + /SPF1 * DI2 + SPF2 * SPF1 * MA * DIV1 + SPF2 * SPF1 * /MA * BPF2 54 Figure 10. ...
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D2/E2 44 pin PLCC MILLIMETERS E DIM MIN A 4.20 A1 2.29 B 0.33 D/E 17.40 D1/E1 16.51 D2/E2 14.99 e 1.19 A NO. OF TERMINALS INCHES NOM MAX MIN NOM MAX 4.45 4.57 ...
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PIN TQFP DIM D/E D1/ ccc A2 A ccc A1 44 LEAD TQFP MILLIMETERS INCHES MAX MIN NOM MIN NOM 1.60 0.15 0.05 ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...