PEB3445E Infineon Technologies AG, PEB3445E Datasheet
PEB3445E
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PEB3445E Summary of contents
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... Edition 2001-06-29 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 7/26/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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PEB 3445 E Revision History: 2001-06-29 Previous Version: Preliminary Data Sheet 09.2000 Page Subjects (major changes since last revision) Changed document to new documentation guidelines. 21 Recommendation for demultiplexed bus operation added to signal LALE. 55 Added table content which ...
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TE3-MUX Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C-Bit Path Maintenance (HDLC) Registers . . . . . . . . . . . . . . . . . . . . . 171 8 Electrical Characteristics . . . . . . . . . ...
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Data Sheet PEB 3445 E 8 2001-06-29 ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 42 DS3 Receive Stuff Bit Timing 198 Figure 43 ...
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List of Tables Table 1 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Data Sheet PEB 3445 E 12 2001-06-29 ...
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M13 Multiplexer and DS3 Framer TE3-MUX V2.1 1 TE3-MUX Overview The TE3-MUX integrates a DS3 framer, with a M13 multiplexer, a tributary interchanger/ line selector and 32 serial line interfaces for DS1/E1/J1 lines with 4:28 line protection capability ...
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M23 Multiplexer and DS3 Framer • Multiplexing/demultiplexing of seven DS2 into/from M13 asynchronous format according to ANSI T1.107, ANSI T1.107a • Multiplexing/demultiplexing of seven DS2 into/from C-bit parity format according to ANSI T1.107, ITU-T G.704 • DS3 framing according ...
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Optional zero suppression • 32-bit counters for errors and received bits • Programmable bit intervals for receive measurements • Framed DS3, framed/unframed DS2 or framed/unframed DS1/E1 error insertion • Additional framing error counters for DS1/E1 error insertion Data Sheet ...
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Logic Symbol • TCLKO44 Transmit TCLK44 Line TD44P Interface TD44N Receive RCLK44 Line RD44P Interface RD44N TDI TDO JTAG TMS TCK TRST Microprocessor Figure 1 Logic Symbol Data Sheet PEB 3445 E TE3-MUX Overview TTC(1) TTC(32:1) TTD(32:1) RTC(32:1) TE3-MUX ...
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Typical Applications Typical applications for the TE3-MUX support of channelized DS3 with serial line interfaces on the low speed side. The system partitioning due to ORB compliance may allow usage in following systems: • Terminal Multiplexers with DS1/E1 and ...
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Pin Description 2.1 Pin Diagram (top view NC23 RTD(25) VDD25 TTD(24) TTD(23) RTC(22) TTC(22) RTC(21) W RTC(26) TTD(26) RTC(25) RTD(24) TTC(24) TTC(23) TTD(22) RTD(21) V RTD(27) RTD(26) TTC(26) TTD(25) RTC(24) ...
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Pin Definitions and Functions Signal Type Definitions: I Input is a standard input- only signal. O Totem Pole Output is a standard active driver. I/O I bidirectional, tri-state input/output pin. o/d Open Drain allows multiple devices to ...
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Local Microprocessor Interface • Pin No. Symbol Input (I) Output (O) D16 RST J17 IM H20 DBW E17, C20, D19, LA(7:0) E18, E19, F18, G17, E20 B11, A12, B12, LD(15:0) I/O C12, A13, B13, C13, A14, C14, A15, B15, ...
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Pin No. Symbol Input (I) Output (O) F20 LALE H18 LRD or LDS G20 LWR or LRDWR J20 LINT Data Sheet Pin Description Function I Address Latch Enable The address information provided on address lines LA(7:0) is internally latched with ...
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Pin No. Symbol Input (I) Output (O) G19 LBHE or LBLE J18 DRR K19 RMC J19 DRT K18 TXME Data Sheet Pin Description Function I Byte High Enable (Intel Bus Mode) If 16-bit bus interface mode is enabled, this signal ...
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Serial Interface • Pin No. Symbol Input (I) Output (O) DS3 Serial Interface Signals B10 TCLK44 C10 TCLKO44 A11 TD44 or TD44P A10 TD44N C9 RCLK44 Data Sheet Pin Description Function I DS3 Transmit Clock Input This clock provides ...
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Pin No. Symbol Input (I) Output (O) A9 RD44 or RD44P B9 RD44N DS3 Overhead Interface B5 TOVHCK A4 TOVHD C5 TOVHDEN Data Sheet Pin Description Function I DS3 Receive Data This unipolar serial data input represents the DS3 signal. ...
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Pin No. Symbol Input (I) Output (O) B4 TOVHSYN I/O D5 TSBCK A3 TSBD C4 ROVHCK B3 ROVHD Data Sheet Pin Description Function Transmit Overhead Synchronization TOVHSYN provides the means to align TOVHD to the first M-frame of the DS3 ...
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Pin No. Symbol Input (I) Output (O) B2 ROVHSYN C3 RSBCK A2 RSBD DS1/E1 Interface Signals, DS3 System Interface Signals L20, M19, N18, RTC(32:1) R20, T20, T17, W20, W18, V16, U14, Y15, Y13, Y12, Y11, W9, W8, V7, Y5, Y3, ...
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Pin No. Symbol Input (I) Output (O) K20, M20, N19, RTD(32:1) P18, R18, V20, V19, Y19, W17, V15, V14, W13, W12, W11, Y9, Y8, W7, V6, Y4, W4, U3, T3, P4, P2, N1, M1, K1, J2, H2, F1, E1, C1 ...
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Pin No. Symbol Input (I) Output (O) L19, M17, P19 , TTC(32:1) P17, T18, U19, V18, U16, W16, W15, Y14, V12, V11, V10, U9, Y7, W6, V5, V4, W1, U2, R3, P3, N2, M2, L2, J1, H1, G2, F3, D1, ...
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Test interface • Pin No. Symbol Input (I) Output (O) C17 TCK B18 TMS B19 TDI A19 TDO B17 TRST D7 SCANEN Data Sheet Pin Description Function I JTAG Test Clock This pin is connected with an internal pull- ...
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Power Supply, Reserved Pins and No-connect Pins • Pin No. Symbol Input (I) Output (O) A1, D4, D8 D13, D17, H4, H17, N4, N17, U4, U8, U13, U17, J9, J10, J11, J12, K9, K10, K11, K12, L9, ...
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General Overview 3.1 Block Diagram • TSBCK TSBD TOVHSYN TOVHDEN TOVHD TOVHCK Figure 4 Block Diagram Data Sheet PEB 3445 E General Overview TRST TCK TMS TDO Remote Loop TDI LINT IM DBW LALE Loop Local Local Loop LBHE/LBLE ...
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Block Description 32 port line selector/tributary mapper This structure allows the user to connect any DS1/E1 signal to a specified tributary of any M12 module. Therefore it maps 32 DS1/E1 signals into 28 DS1 time slots ...
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The test unit also has single/multi bit error insertion for testing and diagnostics and supports framed DS3, framed/unframed DS2 and framed/unframed DS1/E1 error insertion. Data Sheet PEB 3445 E General Overview 33 2001-06-29 ...
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Functional Description 4.1 Remote and Local Loops 4.1.1 Local Loops Local loops are provided on DS3 and DS1 level on a per port/tributary basis. In the local loop the outgoing bit stream of a port/tributary is mirrored to the ...
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DS2 signals are looped after the M23 stage the of the TE3-MUX. Finally the DS1/E1 line loopback mode mirrors one or more incoming lines. Tributary data provided via the low speed serial interface is replaced by the mirrored data ...
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B3ZS Code In the B3ZS line code each block of three consecutive zeros is replaced by either of two replacements codes which are B0V and 00V, where B represents a pulse which applies to the bipolar rule (‘+1’ or ...
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Tributary Mapper The tributary mapper connects any of the 28 low speed tributaries to any of the 32 DS1/ E1 low speed interfaces. A DS3 tributary consists of seven DS2 tributaries. Each DS2 tributaries consists of four DS1 tributaries ...
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Transmit Path Figure 8 shows the DS1/E1 transmit part of the TE3-MUX. Each M12 multiplexer is assigned one input switch which maps 4 out of 32 input signals to the four inputs of the M12 multiplexer. The multiplexer as well ...
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From Transmit Path + 0 M12 1 Demux M12 1 Demux Figure 9 Tributary Mapper (Receive Direction) Data Sheet PEB 3445 E Functional Description To Transmit Path RTC(1) 0 RTD(1) 1 ...
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M12 Multiplexer/Demultiplexer and DS2 framer The M12 multiplexer and the DS2 framer can be operated in two modes: • M12 multiplex format according to ANSI T1.107 • ITU-T G.747 format 4.4.1 M12 multiplex format The framing structure of the ...
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Synchronization Procedure The integrated DS2 framer searches for the frame alignment pattern ’01’ and the multiframe alignment pattern in each of the seven DS2 frames which are contained in a DS3 signal. Frame alignment is declared, when the DS2 ...
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Alarm Indication Signal Detection AIS is declared, when the AIS condition (the received DS2 data stream contains an all ‘1’ signal with less then 3/9 zeros within 3156 bits while the DS2 framer is out of frame) is present ...
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ITU-T G.747 format The multiplexing frame structure is shown in Table 2. Table 2 ITU-T G.747 format Set I Frame Alignment Signal 111010000 Bits from tributaries II Alarm indication to the remote multiplex equipment Parity Bit Reserved ITU-T Bits ...
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Multiplexer The multiplexer combines three E1 signals to form a DS2 signal. Stuffing bits are inserted and the -bits, which are assigned to the case that not enough data is ...
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M23 multiplexer and DS3 framer The DS3 path of the TE3-MUX can be operated in three modes: • M23 multiplex format • C-bit parity format with modified M23 multiplex operation • Full payload rate format 4.5.1 M23 multiplex format ...
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X The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be identical and may not change more than once every second. [84] These bits represent a data block, which consists of 84 bits. [84] consists of ...
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Alarm Indication Signal, Idle Signal Detection Alarm indication signal or Idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one multiframe. The alarm indication ...
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C-bit parity format The framing structure of the C-bit parity format is shown in Table 3. The assignment of the information bits [84] is identical to the M23 multiplex format, but the function of the C-bits is redefined for ...
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FEBE The far end block error bits indicate a CP-bit parity error or a framing error. They are used to monitor the performance of a DS3 signal. Upon detection of either error in the incoming data stream the FEBE-bits are ...
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Far End Alarm and Control Channel The Far End Alarm and Control Channel is handled via an internal BOM controller (see Chapter 4.6, Signalling Controller). The following byte format is assumed (the left most bit is received first): 111111110xxxxxx0 ...
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Loss of Signal Detection Loss of signal is declared, when the incoming data stream contains more than 175 consecutive ’0’s. Recovery Loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.5.2.8 ...
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Full Payload Rate Format In full payload rate format the DS3 multiframe structure can be selected according to M13 multiplex structure or C-bit parity structure. In either case the data blocks [84] carry one continuous data stream which is ...
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Signalling Controller The signalling controller provides access to the Far End Alarm and Control Channel and to the C-bit Parity Path Maintenance Data Link Channel. Note: The C-bit parity path maintenance data link channel and the far end alarm ...
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Data Transmission Transmission of BOM data is done by using a transparent mode of the signalling controller. After having written bytes to the transmit FIFO, the command ’Start Transmission, Enable Automatic Repetition’ via the handshake register FHND ...
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Maintenance data link channel are named PRFF and PXFF respectively. The FIFOs of the Far End Alarm and Control Channel are named FRFF and FXFF. FIFO status and commands are exchanged using the port status registers PPSR (FPSR) and the ...
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C-bit Parity Path Maintenance Data Link 00011 Not Octet B 00100 CRC Error B 00101 Channel Off B Note: For a description of the status information refer to After the received data has been read from the FIFO, the receive ...
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Link). If the transmit command does not include a ’Transmit Message End’ indication (FHND.XME, PHND.XME), the signalling controller will repeatedly request for the next data block by means of a XPR interrupt as soon as the transmit FIFO becomes free. ...
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DMA Supported Data Transmission The C-bit parity Path Maintenance Data Link Channel supports additionally DMA signals to optimize data transfers to and from the internal FIFOs. Request signals for transmit and receive direction indicate free respectively available channel data. ...
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Then the next data transfer is the first byte of a new message. The TE3-MUX automatically appends the CRC and the flags between messages. • C-bit Parity Path ...
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Test Unit The test unit of the TE3-MUX incorporates a test pattern generator and a test pattern synchronizer which can be attached to different test points as shown in Figure 14. Controlled by a small set of registers it ...
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N Pattern length X Feedback Tap Figure 15 Pattern Generator Bit Error Insertion The test unit provides the optional capability to insert bit errors in the range error in 10.000.000 bits ...
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Interrupt Interface Special events in the TE3-MUX are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull, active low/high), which requests the CPU to read status information or to transfer to/from the TE3-MUX. Since ...
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Interface Description 5.1 Local Microprocessor Interface The Local Microprocessor Interface is a demultiplexed/multiplexed switchable Intel or Motorola style interface with 16-bit bus interface. 5.1.1 Intel Mode The Intel mode supports a 16- or 8-bit bus interface ...
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Read Cycle (16 Bit) LA(7:0) Address LBHE LCS LRD LWR LD(15:0) Figure 16 Intel Bus Mode (Demultiplexed Bus Operation) • Read Cycle (16 Bit) LA(7:0) Addr. Data LD(15:0) LALE LBHE LCS LRD LWR Figure 17 Intel Bus Mode (Multiplexed ...
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Motorola Mode The Motorola bus mode supports a 16- or 8-bit bus interface with demultiplexed or multiplexed bus operation. For multiplexed bus operation LA(7:0) must be connected to LD(7:0). The TE3-MUX uses the port pins LA(7:0) for the 8 ...
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Read Cycle (8 bit) LA(7:0) Address LBLE LCS LDS LRDWR LD(15:0) Figure 18 Motorola Bus Mode (Demultiplexed Bus Operation) • Read Cycle (8 bit) LA(7:0) Addr. LD(15:0) LALE LBLE LCS LDS LRDWR Figure 19 Motorola Bus Mode (Multiplexed Bus ...
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Serial Interface Timing 5.2.1 DS3 Interface The DS3 interface of the TE3-MUX consists of one receive port and one transmit port. The receive port provides a clock input (RCLK44) and one (RD44) or two data inputs (RD44P, RD44N) for ...
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Transmit Overhead Bit Access (TOVHSYN in output mode subframe TCLKO44 TD44 C 84 data bits 73 TOVHCK TOVHD F TOVHSYN (Output mode) TOVHDEN 2. Transmit Overhead Bit Access (TOVHSYN in input mode subframe TCLKO44 ...
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DS1/E1 Interface/DS3 System Interface Dependent on the selected operational mode the TE3-MUX operates in channelized mode, where the M13 multiplexer is enabled unchannelized mode where the M13 multiplexer is disabled. In unchannelized mode the first tributary interface ...
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JTAG Interface A test access port (TAP) is implemented in the TE3-MUX. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary ...
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The desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices ...
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Reset and Initialization procedure Since the term “initialization” can have different meanings, the following definition applies: Chip Initialization Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc. Mode Initialization Software procedure, that prepares the device to ...
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Register Description The register description of the TE3-MUX is divided into two parts, an overview of all internal registers and in the second part a detailed description of all internal registers. 7.1 Register Overview Note: Register locations not contained ...
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Register Access Address DS3 Receive Control/Status Registers D3RCFG R D3RCOM R D3RAP R D3RIMSK R D3RESIM R D3RTUC R D3RSTAT D3RLPCS D3RSDL ...
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Register Access Address DS2 Receive Control Registers D2RSEL R D2RCFG R D2RCOM R D2RIMSK R D2RTM0 R D2RTM1 R D2RTM2 R D2RTM3 R D2RLAIS ...
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Register Access Address TURBC0 TURBC1 TUREC0 TUREC1 TURFP0 TURFP1 Test Unit Framer Registers TUTFCFG R TUTFCOM R TURFCFG ...
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Register Access Address PHND PMSK R Data Sheet PEB 3445 E Register Description Reset Comment value 0000 Handshake Register H 00 Interrupt Mask Register H 77 Page 179 181 2001-06-29 ...
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Detailed Register Description 7.2.1 DS3 Control and Status Registers D3CLKCS DS3 Clock Configuration and Status Register Access : read/write Address : 00 H Reset Value : RCA TCA RRX ...
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T2RL Transmit to Receive Loop (Local DS3 Loopback) This bit enables the local DS3 loop where the outgoing DS3 bit stream is mirrored to the DS3 input. 0 Disable local loop. 1 Enable local loop. R2TL Receive to Transmit Loop ...
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TUCLKC Test Unit Clock Configuration Register Access : read/write Address : 01 H Reset Value : RTUR TUL RTUR Reset Test Unit Receiver This bit resets the test unit receiver. ...
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D3TCFG DS3 Transmit Configuration Register Access : read/write Address : 02 H Reset Value : 0000 ITRCK ITRD FAM ITCK ITRCK Invert DS1/E1 Interface Clock This bit sets the clock edge ...
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ITD Invert DS3 Transmit Data This bit enables inversion of DS3 transmit data. 0 Transmit data is logic high (not inverted). 1 Transmit data is logic low (inverted). UTD Unipolar data mode This bit sets the port mode to dual-rail ...
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D3TCOM DS3 Transmit Command Register Access : read/write Address : 04 H Reset Value : TAIC TN B TXBIT SIDLESAISA SAIS r TAIC Transmitted AIC-bit This bit sets the value ...
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SIDLE Send DS3 Idle Code This bit enables transmission of the DS3 idle code (’1100’ between overhead bits, C-bits all ‘0’s). The X-bits must be set to ‘1’ independently by setting TXBIT to ‘1’. 0 Normal operation. 1 Send DS3 ...
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D3TLPB DS3 Transmit Remote DS2 Loopback Register Access : read/write Address : 05 H Reset Value : LPB(6:0) LPB Remote DS2 Loopback Setting LPB(x) enables the remote DS2 loopback of tributary x. In this mode ...
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D3TLPC DS3 Transmit Loopback Code Insertion Register Access : read/write Address : 06 H Reset Value : LPC(6:0) LPC Send Loopback Setting LPC(x) enables transmission of the loopback code in tributary x of the DS3 ...
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D3TAIS DS3 Transmit AIS Insertion Register Access : read/write Address : 07 H Reset Value : AISE AIS(6:0) AISE AIS Error Insertion Toggling this bit inserts one ‘0’ in all DS3 tributaries which transmit AIS. AIS ...
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D3TFINS DS3 Transmit Fault Insertion Control Register Access : read/write Address : 08 H Reset Value : FINSC(3:0) FINSC Fault Insertion Code. Fault insertion is service affecting and is intended for testing ...
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D3TTUC DS3 Transmit Test Unit Control Register Access : read/write Address : 09 H Reset Value : TUDS2(2:0) TUDS1(1:0) EN Enable Test Unit Insertion Setting this bit enables insertion of the ...
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D3TSDL DS3 Transmit Spare Data Link Register Access : read/write Address : 0A H Reset Value : 01FF Multiframe buffer for spare DL bits transmitted in blocks 3, 5, and 7 ...
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D3RCFG DS3 Receive Configuration Register Access : read/write Address : 10 H Reset Value : 0000 CVM ITRCK ITRD OD IL STTM ECM FEBM Note: M13 mode, Full payload mode, loopback code, ...
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IL Interrupt Active Level This bit selects the active level of the interrupt pin. 0 Active Low. 1 Active High. STTM Select Transmit Tributary Monitoring for receive test unit This bit selects the DS1/E1 tributary observed by the test unit ...
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MFM Multiframe Framing Mode This bit selects the M-bit error condition which triggers the DS3 framer to start a new frame search. To enable reframing in case of M-bit errors MDIS must be set to ‘0’. 0 Start new F-frame ...
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D3RCOM DS3 Receive Command Register Access : read/write Address : 12 H Reset Value : C3NC C3C CNCA CCA FRS C3NC Copy DS3 Error Counters Values of DS3 background registers ...
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No operation. 1 Copy background counters to foreground. CCA Copy and Clear DS2/DS3 Error ...
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D3RAP DS3 Receive Alarm Timer Parameters Register Access : read/write Address : 13 H Reset Value : AIS 0 CV(5:0) AIS AIS criteria This bits sets the error rate for AIS detection. Declaration of AIS depends ...
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D3RIMSK DS3 Receive Interrupt Mask Register Access : read/write Address : 14 H Reset Value : 0FFF RSDL TSDL LPCS 1SEC This register provides the interrupt mask for DS3 status interrupts ...
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D3RESIM DS3 Receive Error Simulation Register Access : read/write Address : 16 H Reset Value : FTMR 0 ESIMC(2:0) FTMR Fast Timer This bit enables alarm timer test function (manufacturing test only). ...
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D3RTUC DS3 Receive Test Unit Control Register Access : read/write Address : 17 H Reset Value : TUDS2(2:0) TUDS1(1:0) TURM(1:0) EN Enable Test Unit Receive Clock This bit enables the receive ...
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D3RSTAT DS3 Receive Status Register Access : read Address : 18 H Reset Value : 0001 RSDL TSDL LPCD 1SEC Each bit in the DS3 framer receive status register ...
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N /AICC N -bit Image (C-bit parity format only This bit contains an image of the DS3 frame overhead bit in block 5 of subframe updated only if its state persists for 3 multiframes and ...
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REDS DS3 Red Alarm State (Loss of Frame Alignment) This bit indicates that red alarm was persistent as per alarm timing parameter defined in register D3RAP. The red alarm flag nominally changes when loss of frame alignment condition persists for ...
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D3RLPCS DS3 Receive Loopback Code Status Register Access : read Address : 1A H Reset Value : LPCD(6:0) LPCD Loopback Detected LPCD(x) indicates that a loopback request was received. A ...
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D3RSDL DS3 Receive Spare Data Link Register Access : read Address : 1C H Reset Value : 01FF DL(S)(B) Overhead Bit for Block B of Subframe S These bits buffer the ...
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D3RCVE DS3 Receive B3ZS Code Violation Error Counter Access : read/write Address : 1E H Reset Value : 0000 H 15 CVE(15:0) B3ZS Code Violation Errors Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Register ...
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D3RFEC DS3 Receive Framing Bit Error Counter Access : read/write Address : 20 H Reset Value : 0000 H 15 FEC(15:0) Framing Bit Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of ...
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D3RCPEC DS3 Receive Path Parity Error Counter Access : read/write Address : 24 H Reset Value : 0000 H 15 CPE(15:0) Path Parity Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of ...
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D3RINTV Interrupt Vector Register Access : read Address : 28 H Reset Value : TYPE STATUS 00 0 LBR SR GN(2: RDL TDL TU 10 ALLS XDU XPR ...
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SR Status Register Change This bit indicates a change in DS3 or DS2 status. The status is shown is register D3RINTC. The related port is indicated in bit field GN. GN Group Number This bit field indicates the port where ...
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RME Receive Message End This bit is set, when one complete message of length less than 32 bytes or the last part of a frame is stored in the receive FIFO. The number of bytes in RFF.RFIFO can be determined ...
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D3RINTC Interrupt Status Register Access : read Address : 2A H Reset Value : 0000 H This register must be read after register D3RINTV and dependent on the content of register D3RINTV it contains a copy of register D3RSTAT, D2RSTAT ...
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D3RINTL Interrupt Loopback Code Status Register Access : read Address : 2C H Reset Value : 0000 H This register must be read after register D3RINTV and dependent on the content of register D3RINTV this register contains a copy of ...
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DS2 Control and Status Registers D2TSEL DS2 Transmit Group Select Register Access : read/write Address : 30 H Reset Value : GN(2:0) Note: This register is an indirect access register, ...
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D2TCFG DS2 Transmit Configuration Register Access : read/write Address : 31 H Reset Value : LPC(1:0) LPC Loopback Code This bit selects the C-bit which will be inverted when loopback ...
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D2TCOM DS2 Transmit Command Register Access : read/write Address : 32 H Reset Value : IAIS(3:0) FINSC(1:0) SRA RES IAIS Insert DS1/E1 AIS Setting IAIS(x) enables transmission of the alarm indication signal in ...
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D2TLPC DS2 Transmit DS1/E1 Remote Loopback/Loopback Code Insertion Register Access : read/write Address : 33 H Reset Value : R2T(3:0) LPC(3:0) R2T DS2 Tributary Receive to Transmit Loop (remote loop) Setting bit R2T(x) enables the ...
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D2TTM0, D2TTM1, D2TTM2, D2TTM3 DS2 Transmit Tributary Map Register Access : read/write Address : Reset Value : TN(4:0) TN Tributary Number A ...
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D2RSEL DS2 Receive Group Select Register Access : read/write Address : 40 H Reset Value : GN(2:0) Note: This register is an indirect access register, which must be programmed before accessing ...
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D2RCFG DS2 Receive Configuration Register Access : read/write Address : 41 H Reset Value : ECM AAIS MFM FFM Note: ITU-T G.747 mapping and loop back codes are controlled by ...
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FFM F-Framing Mode This bit selects the F-bit error condition which triggers the DS2 framer to start a new frame search new frame search is started when 2 out of 4 contiguous F-bits are in error ...
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D2RCOM DS2 Receive Command Register Access : read/write Address : 42 H Reset Value : ESIMC(2: C2NC C2C ESIMC Error Simulation Code This bit field enables error simulation. During error simulation ...
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C2C Copy and Clear DS2 Error Counters Only valid when D2RCFG.ECM is set to ‘0’. Values of DS2 background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible ...
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D2RIMSK DS2 Receive Interrupt Mask Register Access : read/write Address : 43 H Reset Value : LPCD AISS REDS RES RAS FAS This register provides the interrupt mask for DS2 ...
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D2RTM0, D2RTM1, D2RTM2, D2RTM3 DS2 Receive Tributary Map Register Access : read/write Address : , Reset Value : TN(4:0) TN Tributary Number A (receive) ...
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D2RLAIS DS2 Receive Local DS1/E1 Loopback/AIS Insertion Register Access : read Address : 48 H Reset Value : IAIS(3:0) T2R(3:0) IAIS Insert AIS Setting bit x of bit field IAIS(x) enables insertion of AIS in ...
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D2RSTAT DS2 Receive Status Register Access : read Address : 49 H Reset Value : AISS REDS RES RAS COFA FAS Each bit in the DS2 framer receive status register ...
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FAS flag. RES Reserved Bit This bit indicates the status of bit 3 in set II of ITU-T G.747 mode updated if the DS2 framer is aligned and when ...
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D2RLPCS DS2 Receive Loopback Code Status Register Access : read Address : 4A H Reset Value : LPCD(3:0) LPCD(N) Loopback Command Detected LPCD(x) indicates that a loopback request was received. A loopback ...
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D2RAP DS2 Receive Alarm Timer Parameters Access : read/write Address : 4B H Reset Value : AIS CM CV(5:0) AIS AIS criteria This bits sets the error rate for AIS detection. Declaration of AIS is ...
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CV Counter Value Dependent on bit CM the counter value specifies the number of frames or the time in multiples of 0.5 milliseconds when AIS or RED is declared, i.e. setting and CM to ‘1’ sets the ...
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D2RFEC DS2 Receive Framing Bit Error Counters Access : read/write Address : 4C H Reset Value : 0000 H 15 FE(15:0) Framing Bit Errors Error counter mode (Clear on Read or Errored Second) depends on register D2RCFG.ECM. For DS1 mode ...
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Test Unit Registers TUTCFG Test Unit Transmit Configuration Register Access : read/write Address : 50 H Reset Value : 0000 INV FBT(4:0) INV Invert output This bit enables inversion of the test unit ...
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TUTCOM Test Unit Transmit Command Register Access : write Address : 52 H Reset Value : LDER IN1E STOP STRT Note: All commands are self clearing i.e. user does not ...
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STRT Start Transmitter. This bit starts the test unit transmitter with the parameters defined in register TUTCFG. In fixed pattern mode the pattern needs to be programmed via register TUTFP0/1 prior to starting the transmitter operation. 1 Start ...
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TUTEIR Test Unit Transmit Error Insertion Rate Register Access : read/write Address : 53 H Reset Value : MTST TXER(2:0) MTST Manufacturing test. Must be written to ‘0’ for normal operation. ...
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TUTFP0 Test Unit Transmit Fixed Pattern Low Word Access : read/write Address : 54 H Reset Value : 0000 Fixed Pattern Low Word See description below. TUTFP1 Test Unit Transmit Fixed Pattern High Word Access : read/write ...
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TURCFG Test Unit Receive Configuration Register Access : read/write Address : 58 H Reset Value : 0000 AIM 0 DAS FBT(4:0) AIM Auxiliary Interrupt Mode This bit field enables the auxiliary interrupt mask AIM of register ...
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ZS Enable Zero Suppression This bit enables zero suppression at the test unit receiver. A ’1’ is expected and inserted at the input if the next 14 bits in the shift register are set to ’0’ zero suppression. ...
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TURCOM Test Unit Receive Command Register Access : write Address : 5A H Reset Value : FRS RDF RDC CAIM STOP STRT Note: All commands are self clearing i.e. user ...
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CAIM Clear Auxiliary Interrupt Masks. This bit resets the internal auxiliary mask. See TURCFG.AIM operation 1 Clear auxiliary interrupts STOP Stop Receiver Setting this bit stopes the test unit receiver. STRT Start Receiver. This bit loads and starts ...
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TURERMI Test Unit Receive Error Measurement Interval Register Access : read/write Address : 5B H Reset Value : TST RXMI(2:0) TST Test Mode This bit enables test of the measurement interval ...
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TURIMSK Test Unit Receive Interrupt Mask Register Access : read/write Address : 5C H Reset Value : 1F1F AIM(4:0) This register provides the interrupt mask for test unit interrupts. See register TURSTAT. The following ...
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TURSTAT Test Unit Receive Status Register Access : read Address : 5E H Reset Value : 0001 INV Inverted Pattern This bit indicates that the received PRBS sequence is inverted. 0 ...
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A0 Input all ‘0’s This bit indicates that the input contained all ’0’ during the last 32 bits reset if at least one ’1’ occurs in 32 bits. OOS Receiver Out of Synchronization This bit indicates the status ...
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TURBC0 Test Unit Receive Bit Counter Low Word Access : read Address : 60 H Reset Value : 0000 H 15 BC(31:0) Bit Counter See description below. TURBC1 Test Unit Receive Bit Counter High Word Access : read Address : ...
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When the error registers are read in response to the “End of Measurement Interval” interrupt vector, reading this register is not necessary because the measurement interval would be known. However the user could assert command TURCOM.RDC to terminate the measurement ...
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TUREC0 Test Unit Receive Error Counter Low Word Access : read Address : 64 H Reset Value : 0000 H 15 EC(31:0) Error Counter See description below. TUREC1 Test Unit Receive Error Counter High Word Access : read Address : ...
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Receive Error Rate Measurement’ interrupt vector is optionally generated. Data Sheet PEB 3445 E Register Description 148 2001-06-29 ...
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TURFP0 Test Unit Receive Fixed Pattern Low Word Access : read Address : 68 H Reset Value : 0000 H 15 FP(31:0) Fixed pattern See description below. TURFP1 Test Unit Receive Fixed Pattern High Word Access : read Address : ...
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Test Unit Framer Registers TUTFCFG Test Unit Transmit Framer Configuration Register Access : read/write Address : 70 H Reset Value : SRAF FM T1E1 OM Overwrite mode This ...
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T1E1 Select DS1/E1 mode This bit switches between DS1 and E1 mode. 0 Select DS1 mode. 1 Select E1 mode. EF Enable framer This bit enables the framer for framed DS1/E1 error insertion mode. 0 Disable framer. (Unframed bit error ...
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TUTFCOM Test Unit Transmit Framer Command Register Access : read/write Address : 71 H Reset Value : EBIT CRC FE EBIT Set active E-bit (E1 mode) This bit inserts an ...
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TURFCFG Test Unit Receive Framer Configuration Register Access : read/write Address : 74 H Reset Value : RRAM FM T1E1 OM Overwrite mode This bit enables test pattern overwrite. ...
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FM Framer Mode This bit selects the frame format of DS1 or E1 mode. DS1 0 Select ESF (F24) format. 1 Select SF (F12) format Select double frame format. 1 Select multiframe format. T1E1 Select DS1/E1 mode This ...
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TURFCOM Test Unit Receive Framer Command Register Access : read/write Address : 75 H Reset Value : Copy and Clear Framer Error Counters Values of framer background registers are ...
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TURFSTAT Test Unit Receive Framer Status Register Access : read Address : 76 H Reset Value : RRA LFA RRA Received Remote Alarm (Yellow Alarm) Condition for receive remote alarm ...
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TURFFEC Test Unit Receive Framing Error Counter Access : read Address : 78 H Reset Value : Framing Error Counter The counter will not be incremented during asynchronous state. The error counter is cleared on read. ...
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TURFCEC Test Unit Receive Framer CRC Error Counter Access : read Address : 7A H Reset Value : CRC Errors The counter will not be incremented during asynchronous state. The error counter is cleared on read. ...
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TURFEBC Test Unit Receive Framer Errored Block Counter Access : read Address : 7C H Reset Value : E-Bit counter The counter will not be incremented during asynchronous state. The error counter is cleared on read. ...
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Far End Alarm and Control Channel (BOM) Registers FRCFG FEAC Receive Configuration Register Access : read/write Address : 80 H Reset Value : 0000 RTF RFIFO Threshold Level This bit ...
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RON Receiver On/Off This bit switches the receiver of the Far End Alarm and Control channel to operational (on) or inoperational state (off recommended to issue a ’Receive Message Complete’ command after the receiver was initialized (FHND.RMC = ...
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FRFF FEAC Receive FIFO Register Access : read Address : 82 H Reset Value : 0000 RFIFO Receive FIFO Data This bit field contains the first 16 bit word of the ...
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FXCFG FEAC Transmit Configuration Register Access : read/write Address : 84 H Reset Value : XON Transmitter On/Off This bit switches the transmitter of the facility data link to operational ...
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FXFF FEAC Transmit FIFO Access : write Address : 86 H Reset Value : 0000 XFIFO Transmit FIFO Data This bit field contains the first 16 bit word of the transmit ...
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FPSR FEAC Port Status register Access : read Address : 88 H Reset Value : 2000 XRA XFW RBC(4:0) XRA Transmit Repeat Active This bit indicates that the transmit signalling controller is operating in ...
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STAT Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. 00000 BOM Filtered Data Declared B This status is reported when ‘BOM Filtered Data’ is enabled, and 7 out of 10 BOM ...
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FHND FEAC Handshake Register Access : write Address : 8A H Reset Value : 0000 Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not ...
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No function 1 Transmit data stored in XFF.XFIFO fully transparent, i.e. without bit stuffing and CRC. XME Transmit Message End Setting this bit indicates that the last data block written to XFF.XFIFO completes the current message. Data Sheet PEB ...
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Table 8 Far End Alarm and Control Transmit Commands XRES XREP XTF XME Function Reset Port Start Transmission Send FIFO content in BOM channel Stop Transmssion Stop transmission ...
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FMSK FEAC Interrupt Mask Register Access : read/write Address : 8C H Reset Value : ALLS XDU XPR RPF RME RMI For each facility data link interrupt vector an interrupt ...
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C-Bit Path Maintenance (HDLC) Registers PRCFG HDLC Receive Configuration Register Access : read/write Address : 90 H Reset Value : 0000 RMCP DRRP DMA RMCP RMC Polarity This bit sets ...
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The threshold value is given as follows byte threshold byte threshold byte threshold byte threshold B INV Invert data input from Receive ...
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PRFF HDLC Receive FIFO Register Access : read Address : 92 H Reset Value : 0000 RFIFO Receive FIFO Data This bit field contains the first 16 bit word of the ...
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PXCFG HDLC Transmit Configuration Register Access : read/write Address : 94 H Reset Value : 0000 DRTP DMA TXMEP TXMEP TXME Polarity This bit sets the polarity of the TXME signal. ...
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DISCRC Disable CRC This bit enables CRC generation and transmission on transmission of HDLC packets. 0 Enable CRC generation. 1 Disable CRC generation. SF Shared Flags This bit enables transmission of protocol data with shared flags. 0 Disable shared flags. ...
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PXFF HDLC Transmit FIFO Register Access : write Address : 96 H Reset Value : 0000 XFIFO Transmit FIFO Data This bit field contains the first 16 bit word of the ...
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PPSR HDLC Port Status register Access : read Address : 98 H Reset Value : 2000 XFW RBC(4:0) XFW Transmit FIFO Write Enable This bit indicates that data can be written to XFF.XFIFO. ...
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STAT Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. 00000 Valid HDLC Frame B This status is reported whenever a valid frame with valid CRC was received. 00001 Receive Data Overflow ...
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PHND HDLC Handshake Register Access : write Address : 9A H Reset Value : 0000 Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not ...
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XHF Transmit HDLC frame Setting this bit indicates that the contents written to XFF.XFIFO shall be transmitted as HDLC frame. If data written to XFF.XFIFO completes a HDLC frame, bit XME must be set together with XHF in order to ...
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PMSK Interrupt Mask Register Access : read/write Address : 9C H Reset Value : ALLS XDU XPR RPF RME For each facility data link interrupt vector an interrupt vector generation ...
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Electrical Characteristics 8.1 Important Electrical Requirements Both V and V can take on any power-on sequence. Within 50 milliseconds of DD3 DD25 power-up the voltages must be within their respective absolute voltage limits. At power- down, within 50 milliseconds ...
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DC Characteristics a) Power Supply Pins Table 11 DC Characteristics Parameter Symbol Core Supply Voltage V DD25 I/O Supply Voltage V DD3 I Core operational CC25 supply I power down CCPD25 current (no clocks) V DD25 I/O supply operational ...
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AC Characteristics 3 DD3 Inputs are driven to 2.4 V for a logical ‘1’ and to 0.4 V for a logical ‘0’. Timing measurements are made ...
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Local Microprocessor Interface Timing 8.4.1.1 Intel Bus Interface Timing • P Read Cycle LA 20 LBHE 20 LCS 28 LRD LD P Write Cycle LA 20 LBHE 20 LCS 28 LWR LD Figure 24 Intel Demultiplexed Bus Timing Data ...
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LRD x LCS LWR x LCS Figure 26 Read, Write Control Interval in Demultiplexed Bus Mode • LRD x LCS LWR x LCS Figure 27 Read, Write Control Interval in Multiplexed Bus Mode Table 13 Intel Bus Interface Timing No. ...
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Motorola Bus Interface Timing • P Read Cycle LA 40 LBLE 40 LRDWR 48 LCS 50 LDS LD P Write Cycle LA 40 LBLE 40 LRDWR 48 LCS 50 LDS LD Figure 28 Motorola Demultiplexed Bus Timing Data Sheet ...
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P Read Cycle 44 LALE LBLE 42 43 LRDWR 45 LCS LDS Write Cycle 44 LALE LBLE 42 43 LRDWR 45 LCS LDS Figure 29 Motorola Multiplexed Bus Timing Data ...
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LCS x LDS Figure 30 Read, Write Control Interval in Demultiplexed Bus Mode LALE LCS x LDS Figure 31 Read, Write, ALE Control Interval in Multiplexed Bus Mode Table 14 Motorola Bus Interface Timing No. Parameter ...
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DMA Interface Signals 8.4.2.1 DMA Receive Timing 1 LRD 2 LDS 3 DRR 4 RMC Figure 32 DMA Receive Timing Note: 1 Intel Mode 2 Motorola Mode 3 DRR is asserted asynchronously as soon as there is data in ...
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DMA Transmit Timing 1 LWR 2 LDS 3 DRT 4 TXME Figure 33 DMA Transmit Timing Note: 1 Intel Mode 2 Motorola Mode 3 DRT is asserted asynchronously as soon as there is free space in the transmit FIFO. ...
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Serial Interface Timing 8.4.3.1 DS3 Serial Interface Timing • TCLK44 RCLK44 Figure 34 Clock Input Timing Table 17 Clock Input Timing No. Parameter 100 Clock period 101 Clock high timing 102 Clock low timing 103 Clock fall time 104 ...
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TCLK44 RCLK44 (Note 1) TCLKO44 Figure 35 DS3 Transmit Cycle Timing Note: 1. Actual clock reference depends on selected clock mode: • TCLKO44 (Note 2) TCLKO44 (Note 3) TD44, TD44P/N Figure 36 DS3 Transmit Data Timing Note: 2. Timing ...
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RCLK44 (Note 1) RCLK44 (Note 2) RD44, RD44P/N Figure 37 DS3 Receive Cycle Timing Note: 1. Timing for data which is sampled on the rising edge of the receive clock. 2. Timing for data which is sampled on the ...
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Overhead Bit Timing • TOVHCK TOVHSYN (Output Mode)) TOVHD TOVHDEN Figure 38 DS3 Transmit Overhead Timing • TCLKO44 TOVHSYN (Input mode) Figure 39 DS3 Transmit Overhead Synchronization Timing Table 20 DS3 Transmit Overhead Timing No. Parameter 150 TOVHCK to ...
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ROVHCK ROVHSYN ROVHD Figure 40 DS3 Receive Overhead Timing Table 21 DS3 Receive Overhead Timing No. Parameter 157 ROVHCK to ROVHSYN delay 158 ROVHCK to ROVHD delay Data Sheet PEB 3445 E Electrical Characteristics 157 158 Limit Values min. ...
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Stuff Bit Timing • TSBCK TSBD Figure 41 DS3 Transmit Stuff Bit Timing Table 22 DS3 Transmit Stuff Timing No. Parameter 160 TSBD to TSBCK setup time 161 TSBD to TSBCK hold time • RSBCK RSBD Figure 42 DS3 ...
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DS1/E1 Interface Timing • TTC(x) Figure 43 DS1/E1 Transmit Clock Timing Table 24 DS1/E1 Transmit Clock Timing No. Parameter Interface operated in E1 Mode 170 Clock period 171 Clock high timing 172 Clock low timing 173 Clock fall time ...
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TTC(x) (Note 1) TTC(x) (Note 2) TTD(x) Figure 44 DS1/E1 Transmit Data Timing Note: 1. Timing for transmit data sampled on the rising edge of TTC(x). 2. Timing for transmit data sampled on the falling edge of TTC(x). Table ...