MPC930 Freescale Semiconductor, Inc, MPC930 Datasheet

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MPC930

Manufacturer Part Number
MPC930
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Part Number:
MPC930
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Low Voltage PLL Clock Driver
targeted for high performance clock applications. With output frequencies
of up to 150MHz and output skews of 300ps the MPC930/931 is ideal for
the most demanding clock distribution designs. The device employs a
fully differential PLL design to minimize cycle to cycle and long term jitter.
This parameter is of significant importance when the clock driver is
providing the reference clock for PLL’s on board todays microprocessors
and ASiC’s. The device offers 6 low skew outputs, and a choice between
internal or external feedback. The feedback option adds to the flexibility of
the device, providing numerous input to output frequency relationships.
there are some minor differences. The MPC931 has been optimized for
use as a zero delay buffer. In addition to tighter specification limits on the
phase offset of the device, a higher speed VCO has been used on the
MPC931. The MPC930, on the other hand, is more optimized for use as a
clock generator. When choosing between the 930 and 931, pay special
attention to the differences in the AC parameters of each device.
seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life.
The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the
power–down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock
outputs while leaving a subset active to allow for total processor shut down while maintaining system monitors to “wake up” the
system when signaled. During shut down, the PLL will remain locked, if internal feedback is used, so that wake up time will be
minimized. The shut down and power down pins can be combined for the ultimate in power savings. The Shut_Dn pins are
synchronized to the clock internal to the chip to eliminate the possibility of generating runt pulses.
integrated crystal oscillator that allows for an inexpensive crystal to be used as the frequency reference. For more information on
the crystal oscillator please refer to the applications section of this data sheet. In those applications where the 930/931 will be
used to regenerate clocks from an existing source or as a zero delay buffer, alternative reference clock inputs are provided. Both
devices offer an LVCMOS input that can be used as the PLL reference. In addition the MPC931 replaces the crystal oscillator
inputs with a differential PECL reference clock input that allows the device to be used in mixed technology clock distribution trees.
oscillator when the internal feedback is selected. The on–board crystal oscillator requires no external components other than a
series resonant crystal (see Applications Information section for more on crystals). The internal VCO is running at 8x the input
reference clock. The outputs can be configured to run at 4x, 2x, 1.25x or 0.66x the input reference frequency. If the external
feedback is selected, one of the MPC931’s outputs must be connected to the Ext_FB pin. Using the external feedback, numerous
input/output frequency relationships can be developed.
or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω transmission
lines. For series terminated applications, each output can drive two 50Ω transmission lines, effectively increasing the fanout to
1:12. The device is packaged in a 32–lead TQFP package to provide the optimum combination of board density and cost.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
1/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
On–Board Crystal Oscillator (MPC930)
Differential LVPECL Reference Input (MPC931)
Fully Integrated PLL
Output Shut Down Mode
Output Frequency up to 150MHz
Compatible with PowerPC
32–Lead TQFP Packaging
Power Down Mode
The MPC930/931 is a 3.3V compatible, PLL based clock driver device
The MPC930 and MPC931 are very similar in basic functionality, but
The MPC930/931 offers two power saving features for power conscious portable or “green” designs. The power down pin will
The MPC930/931 devices offer a great deal of flexibility in what is used as the PLL reference. The MPC930 offers an
An internal feedback divide by 8 of the VCO frequency is compared with the input reference provided by the on–board crystal
The MPC930/931 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS
100ps Typical Cycle–to–Cycle Jitter
and Intel Microprocessors
1
REV 3
PLL CLOCK DRIVER
32–LEAD TQFP PACKAGE
LOW VOLTAGE
MPC930
MPC931
CASE 873A–02
FA SUFFIX

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MPC930 Summary of contents

Page 1

... The MPC930/931 devices offer a great deal of flexibility in what is used as the PLL reference. The MPC930 offers an integrated crystal oscillator that allows for an inexpensive crystal to be used as the frequency reference. For more information on the crystal oscillator please refer to the applications section of this data sheet ...

Page 2

... MPC930 MPC931 GNDO 25 Qa1 26 Qa0 27 VCCO 28 MPC930/ MPC931 Div_Sela 29 Div_Selb 30 Div_Selc Figure 1. 32–Lead Pinout (Top View) (Pullup) Power_Dn (Pullup) PLL_En (Pulldown) TCLK_Sel (Pullup) TCLK MPC930 xtal1 xtal OSC xtal2 Ext_FB (Pullup) (Pulldown) ExtFB_Sel (Pulldown) ...

Page 3

... VCO VCO/2 Power_Dn SHUT_DN0 SHUT_DN1 SHUT_DN0 SHUT_DN1 TIMING SOLUTIONS BR1333 — Rev 6 Figure 3. Power_Dn Timing Diagram Figure 4. Shut_Dn Timing Diagram 3 MPC930 MPC931 MOTOROLA ...

Page 4

... I CCPLL Maximum PLL Supply Current The MPC930/931 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull–up/pull–down resistors which affect input current. MOTOROLA Min – ...

Page 5

... MPC930 AC CHARACTERISTICS ( 3.3V 5%) Symbol Characteristic f xtal Crystal Oscillator Frequency Range f ref Input Reference Frequency t os Output–to–Output Skew (Note 4.) f VCO VCO Lock Range f max Maximum Output Frequency t pd TCLK to EXT_FB Delay t pw Output Duty Cycle (Note 4 Output Rise/Fall Time (Note 4 ...

Page 6

... Power_Dn pin can be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 25 and 180MHz the MPC930/931 can generally be configured into a stable region. Table 2. Input Reference/Output Frequency Relationships (Internal Feedback Only) ...

Page 7

... MPC931 is recommended over the MPC930. The MPC931 has been optimized and specified specifically for use as a zero delay buffer. When used as a zero delay buffer the MPC930/931 will likely nested clock tree application. For these applications the MPC931 offers a LVPECL clock input as a TIMING SOLUTIONS BR1333 — ...

Page 8

... For the case where all of the outputs are switching at the same frequency the total jitter is exactly equal to the PLL jitter device, like the MPC930/931, where a number of the outputs can be switching synchronously but at different frequencies a “multi–modal” ...

Page 9

... DC voltage drop that will be seen between the V CC supply and the PLL_VCC pin of the MPC930/931. From the data sheet the I PLL_VCC current (the current sourced through the PLL_VCC pin) is typically 15mA (20mA maximum), assuming that a minimum of 3 ...

Page 10

... Therefore in the majority of cases a parallel specified crystal can be used with the MPC930 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically ...

Page 11

... V CC /2. This technique draws a fairly high level of DC current and thus only a single terminated line can TIMING SOLUTIONS BR1333 — Rev 6 be driven by each output of the MPC930/931 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines ...

Page 12

... MPC930 MPC931 3.0 OutA 3.8956 OutB 2 3.9386 2.0 In 1.5 1.0 0 TIME (nS) Figure 17. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To ...

Page 13

... N É É É É É É SECTION AE– MPC930 MPC931 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...

Page 14

... MPC930 MPC931 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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