MPC930

Manufacturer Part NumberMPC930
ManufacturerFreescale Semiconductor, Inc
MPC930 datasheet
 


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f ref
VCO
Phase
Detector
LPF
m
+
+
f VCO
f ref
,
f VCO
fQn · N · P
m
N
+
fQn · N · P
f ref
m
m = 8
P = 1 (Power_Dn=‘0’), 2 (Power_Dn=‘1’)
Figure 15. PLL Block Diagram
For the MPC930 clock driver, the following will provide an
example of how to determine the crystal frequency required
for a given design.
Given:
Qa
= 66.6MHz
Qb
= 33.3MHz
Qc
= 22.2MHz
Power_Dn = ‘0’
+
fQn · N · P
f ref
m
From Table 4
fQc = VCO/6 then N = 6
From Figure 15
m = 8 and P = 1
+
+
22.22 · 6 · 1
f ref
16.66MHz
8
Driving Transmission Lines
The MPC930/931 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to V CC /2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
TIMING SOLUTIONS
BR1333 — Rev 6
be driven by each output of the MPC930/931 clock driver. For
P
N
Qn
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 16 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC930/931
clock driver is effectively doubled due to its capability to drive
multiple lines.
MPC930/931
OUTPUT
BUFFER
7Ω
IN
MPC930/931
OUTPUT
BUFFER
7Ω
IN
Figure 16. Single versus Dual Transmission Lines
The waveform plots of Figure 17 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC930/931 output buffers
is more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC930/931. The output
waveform in Figure 17 shows a step in the waveform, this
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 43Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 43Ω || 43Ω
Ro = 7Ω
VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)
= 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
11
MPC930 MPC931
Z O = 50Ω
R S = 43Ω
OutA
Z O = 50Ω
R S = 43Ω
OutB0
Z O = 50Ω
R S = 43Ω
OutB1
MOTOROLA