MPC930

Manufacturer Part NumberMPC930
ManufacturerFreescale Semiconductor, Inc
MPC930 datasheet
 


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MPC930 MPC931
output–to–output skew plus 250ps jitter). For devices that are
configured differently the differences between the nominal
delays must also be accounted for.
When using the MPC931 as a zero delay buffer there is
more information which can help minimize the overall timing
uncertainty. To fully minimize the specified uncertainty, it is
crucial that the relative position of the outputs be known. It is
recommended that if all of the outputs are going to be used
that the Qc0 output be used as the feedback reference. The
Qc0 output lies in the middle of the other outputs with respect
to output skew. Therefore it can be assumed that the output
to output skew of the device is 150ps with respect to output
Qc0.
There will be some cases where only a subset of the
outputs of the MPC931 are required. There is significantly
tighter skew performance between outputs on a common
bank (i.e., Qa0 to Qa1). The skews between these common
bank outputs are outlined in the table below. In general the
skews between outputs on a given bank is about a third of the
skew between all banks, reducing the skew to a value of
100ps.
Table 3. Within–Bank Skews
Outputs
Relative Skews
Qa0
Qa1
+35ps, 50ps
Qb0
Qb1
–30ps, 50ps
Qc0
Qc1
20ps, 50ps
Jitter Performance of the MPC930/931
With the clock rates of today’s digital systems continuing
to increase more emphasis is being placed on clock
distribution design and management. Among the issues
being addressed is system clock jitter and how that affects
the overall system timing budget. The MPC930/931 was
designed to minimize clock jitter by employing a differential
bipolar PLL as well as incorporating numerous power and
ground pins in the design. The following few paragraphs will
outline the jitter performance of the MPC930/931, illustrate
the measurement limitations and provide guidelines to
minimize the jitter of the device.
The most commonly specified jitter parameter is
cycle–to–cycle jitter. Unfortunately with today’s high
performance measurement equipment there is no way to
measure this parameter for jitter performance in the class
demonstrated by the MPC930/931. As a result different
methods are used which approximate cycle–to–cycle jitter.
The typical method of measuring the jitter is to accumulate a
large number of cycles, create a histogram of the edge
placements and record peak–to–peak as well as standard
deviations of the jitter. Care must be taken that the measured
edge is the edge immediately following the trigger edge. If
this is not the case the measurement inaccuracy will add
significantly to the measured jitter. The oscilloscope cannot
collect adjacent pulses, rather it collects data from a very
large sample of pulses. It is safe to assume that collecting
pulse information in this mode will produce jitter values
somewhat larger than if consecutive cycles were measured,
therefore, this measurement will represent an upper bound of
cycle–to–cycle jitter. Most likely, this is a conservative
estimate of the cycle–to–cycle jitter.
MOTOROLA
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Peak–to–Peak PLL Jitter
Peak–to–Peak Period Jitter
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Peak–to–Peak PLL Jitter
Peak–to–Peak Period Jitter
Figure 11. PLL Jitter and Edge Displacement
There are two sources of jitter in a PLL based clock driver,
the commonly known random jitter of the PLL and the less
intuitive jitter caused by synchronous, different frequency
outputs switching. For the case where all of the outputs are
switching at the same frequency the total jitter is exactly
equal to the PLL jitter. In a device, like the MPC930/931,
where a number of the outputs can be switching
synchronously but at different frequencies a “multi–modal”
jitter distribution can be seen on the highest frequency
outputs. Because the output being monitored is affected by
the activity on the other outputs it is important to consider
what is happening on those other outputs. From Figure 11,
one can see for each rising edge on the higher frequency
signal the activity on the lower frequency signal is not
constant. The activity on the other outputs tends to alter the
internal thresholds of the device such that the placement of
the edge being monitored is displaced in time. Because the
signals are synchronous the relationship is periodic and the
resulting jitter is a compilation of the PLL jitter superimposed
on the displaced edges. When histograms are plotted the
jitter looks like a “multi–modal” distribution as pictured in
Figure 11 on page 8. Depending on the size of the PLL jitter
and the relative displacement of the edges the “multi–modal”
distribution will appear truly “multi–modal” or simply like a
“fat” Gaussian distribution. Again note that in the case where
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TIMING SOLUTIONS
BR1333 — Rev 6