MPC930

Manufacturer Part NumberMPC930
ManufacturerFreescale Semiconductor, Inc
MPC930 datasheet
 


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all the outputs are switching at the same frequency there is
no edge displacement and the jitter is reduced to that of
the PLL.
Figure 12 graphically represents the PLL jitter of the
MPC930/931. The data was taken for several different output
configurations. Because of the relatively few outputs on the
MPC930/931, the multimodal distribution is of a second order
affect on the 930/931 and can be ignored. As one can see in
the figure the PLL jitter is much less dependent on output
configuration than on internal VCO frequency. However, for a
given VCO frequency, a lower output frequency produces
more jitter.
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VCO Frequency (MHz)
Conf 1 = Qa= 2, Qb=Qc= 4
Conf 2 = Qa= 2, Qb=Qc=Shut Down
Conf 3 = Qa= 4, Qb=Qc=Shut Down
Figure 12. RMS Jitter versus VCO Frequency
(Qa0 Output)
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Frequency Output (MHz)
Conf 2 = Qa= 2, Qb=Qc=Shut Down
Conf 3 = Qa= 4, Qb=Qc=Shut Down
Figure 13. RMS Jitter versus Output Frequency
(Qa0 Output)
Finally from the data there are some general guidelines
that, if followed, will minimize the output jitter of the device.
First and foremost always configure the device such that the
VCO runs as fast as possible. This is by far the most critical
parameter in minimizing jitter. Second keep the reference
frequency as high as possible. More frequent updates at the
phase detector will help to reduce jitter. Note that if there is a
tradeoff between higher reference frequencies and higher
TIMING SOLUTIONS
BR1333 — Rev 6
VCO frequency always chose the higher VCO frequency to
minimize jitter. The third guideline is to try to shut down
outputs that are unused. Minimizing the number of switching
outputs will minimize output jitter.
Power Supply Filtering
The MPC930/931 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC930/931 provides
separate power supplies for the output buffers (V CCO ) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise digital outputs from the relatively sensitive internal
Conf 1
analog phase–locked loop. In a controlled environment such
Conf 2
as an evaluation board this level of isolation is sufficient.
Conf 3
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies a second
level of isolation may be required. The simplest form of
isolation is a power supply filter on the PLL_VCC pin for the
MPC930/931.
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PLL_VCC
MPC930/931
VCC
Conf 2
Conf 3
Figure 14. Power Supply Filter
Figure 14 illustrates a typical power supply filter scheme.
The MPC930/931 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
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that needs to be met in the final filter design is the DC voltage
drop that will be seen between the V CC supply and the
PLL_VCC pin of the MPC930/931. From the data sheet the
I PLL_VCC current (the current sourced through the PLL_VCC
pin) is typically 15mA (20mA maximum), assuming that a
minimum of 3.0V must be maintained on the PLL_VCC pin
very little DC voltage drop can be tolerated when a 3.3V V CC
supply is used. The resistor shown in Figure 14 must have a
resistance of 10–15Ω to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20KHz. As the noise frequency crosses the
series resonant point of an individual capacitor it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.
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MPC930 MPC931
3.3V
R S =10–15Ω
22µF
0.01µF
0.01µF
MOTOROLA