MCF5307 Freescale Semiconductor, Inc, MCF5307 Datasheet

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MCF5307

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MCF5307
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor, Inc.
MCF5307 ColdFire
®
Integrated Microprocessor
User’s Manual
MCF5307UM/D
Rev. 2.0, 08/2000
For More Information On This Product,
Go to: www.freescale.com

Related parts for MCF5307

MCF5307 Summary of contents

Page 1

... Freescale Semiconductor, Inc. MCF5307 ColdFire Integrated Microprocessor For More Information On This Product, Go to: www.freescale.com User’s Manual MCF5307UM/D Rev. 2.0, 08/2000 ® ...

Page 2

... Freescale Semiconductor, Inc. ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

Page 3

... Freescale Semiconductor, Inc. Part I: MCF5307 Processor Core Hardware Multiply/Accumulate (MAC) Unit Part II: System Integration Module (SIM) Synchronous/Asynchronous DRAM Controller Module Parallel Port (General-Purpose I/O) IEEE 1149.1 Test Access Port (JTAG) Glossary of Terms and Abbreviations For More Information On This Product, Overview ColdFire Core ...

Page 4

... Freescale Semiconductor, Inc. Overview 1 Part I: MCF5307 Processor Core Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module ...

Page 5

... Freescale Semiconductor, Inc. Paragraph Number 1.1 Features ............................................................................................................... 1-1 1.2 MCF5307 Features.............................................................................................. 1-4 1.2.1 Process ............................................................................................................ 1-6 1.3 ColdFire Module Description ............................................................................. 1-7 1.3.1 ColdFire Core ................................................................................................. 1-7 1.3.1.1 Instruction Fetch Pipeline (IFP).................................................................. 1-7 1.3.1.2 Operand Execution Pipeline (OEP) ............................................................ 1-7 1.3.1.3 MAC Module.............................................................................................. 1-7 1.3.1.4 Integer Divide Module................................................................................ 1-7 1.3.1.5 8-Kbyte Unified Cache ............................................................................... 1-8 1.3.1.6 Internal 4-Kbyte SRAM ............................................................................. 1-8 1.3.2 DRAM Controller ........................................................................................... 1-8 1.3.3 DMA Controller.............................................................................................. 1-8 1.3.4 UART Modules............................................................................................... 1-8 1.3.5 Timer Module ................................................................................................. 1-9 1 ...

Page 6

... Instruction Set Summary .............................................................................. 2-37 2.7 Instruction Timing ............................................................................................ 2-40 2.7.1 MOVE Instruction Execution Times ............................................................ 2-41 2.7.2 Execution Timings—One-Operand Instructions .......................................... 2-43 2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-43 2.7.4 Miscellaneous Instruction Execution Times................................................. 2-45 vi For More Information On This Product, CONTENTS Title Part I MCF5407 Processor Core Chapter 2 ColdFire Core MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 7

... Freescale Semiconductor, Inc. Paragraph Number 2.7.5 Branch Instruction Execution Times ............................................................ 2-46 2.8 Exception Processing Overview ....................................................................... 2-47 2.8.1 Exception Stack Frame Definition................................................................ 2-49 2.8.2 Processor Exceptions .................................................................................... 2-50 Hardware Multiply/Accumulate (MAC) Unit 3.1 Overview............................................................................................................. 3-1 3.1.1 MAC Programming Model............................................................................. 3-2 3.1.2 General Operation........................................................................................... 3-3 3.1.3 MAC Instruction Set Summary ...................................................................... 3-4 3.1.4 Data Representation........................................................................................ 3-4 3.2 MAC Instruction Execution Timings.................................................................. 3-5 4.1 Interactions between Local Memory Modules ................................................... 4-1 4 ...

Page 8

... ColdFire BDM Command Format............................................................ 5-20 5.5.3.1.1 Extension Words as Required............................................................... 5-21 5.5.3.2 Command Sequence Diagrams................................................................. 5-21 5.5.3.3 Command Set Descriptions ...................................................................... 5-23 5.5.3.3.1 Read A/D Register ( 5.5.3.3.2 Write A/D Register ( 5.5.3.3.3 Read Memory Location ( viii For More Information On This Product, CONTENTS Title Chapter 5 Debug Support / ) ..................................................... 5-24 RAREG RDREG / )................................................... 5-25 WAREG WDREG )............................................................ 5-26 READ MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 9

... Freescale Semiconductor, Inc. Paragraph Number 5.5.3.3.4 Write Memory Location ( 5.5.3.3.5 Dump Memory Block ( 5.5.3.3.6 Fill Memory Block ( 5.5.3.3.7 Resume Execution ( 5.5.3.3.8 No Operation ( 5.5.3.3.9 Synchronize PC to the PST/DDATA Lines ( 5.5.3.3.10 Read Control Register ( 5.5.3.3.11 Write Control Register ( 5.5.3.3.12 Read Debug Module Register ( 5.5.3.3.13 Write Debug Module Register ( 5.6 Real-Time Debug Support ................................................................................ 5-39 5.6.1 Theory of Operation...................................................................................... 5-40 5 ...

Page 10

... C Data I/O Register (I2DR) ....................................................................... 8- Programming Examples ............................................................................. 8-10 8.6.1 Initialization Sequence.................................................................................. 8-10 8.6.2 Generation of START................................................................................... 8-10 8.6.3 Post-Transfer Software Response................................................................. 8-11 8.6.4 Generation of STOP...................................................................................... 8-12 8.6.5 Generation of Repeated START................................................................... 8-12 8.6.6 Slave Mode ................................................................................................... 8-13 8.6.7 Arbitration Lost............................................................................................. 8-13 x For More Information On This Product, CONTENTS Title Chapter 7 Chapter Module MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 11

... Freescale Semiconductor, Inc. Paragraph Number 9.1 Overview............................................................................................................. 9-1 9.2 Interrupt Controller Registers ............................................................................. 9-2 9.2.1 Interrupt Control Registers (ICR0–ICR9) ...................................................... 9-3 9.2.2 Autovector Register (AVR) ............................................................................ 9-5 9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)................................... 9-6 9.2.4 Interrupt Port Assignment Register (IRQPAR) .............................................. 9-7 10.1 Overview........................................................................................................... 10-1 10.2 Chip-Select Module Signals ............................................................................. 10-1 10.3 Chip-Select Operation....................................................................................... 10-2 10.3.1 General Chip-Select Operation..................................................................... 10-3 10.3.1.1 8-, 16-, and 32-Bit Port Sizing.................................................................. 10-4 10 ...

Page 12

... DMA Transfer Overview.................................................................................. 12-3 12.4 DMA Controller Module Programming Model................................................ 12-4 12.4.1 Source Address Registers (SAR0–SAR3) .................................................... 12-6 12.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 12-7 xii For More Information On This Product, CONTENTS Title Part III Peripheral Module Chapter 12 DMA Controller Module MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 13

... Freescale Semiconductor, Inc. Paragraph Number 12.4.3 Byte Count Registers (BCR0–BCR3)........................................................... 12-7 12.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 12-8 12.4.5 DMA Status Registers (DSR0–DSR3) ....................................................... 12-10 12.4.6 DMA Interrupt Vector Registers (DIVR0–DIVR3) ................................... 12-11 12.5 DMA Controller Module Functional Description........................................... 12-11 12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) ........................... 12-12 12.5.2 Data Transfer Modes .................................................................................. 12-12 12 ...

Page 14

... UART Module Initialization Sequence .................................................. 14-29 Parallel Port (General-Purpose I/O) 15.1 Parallel Port Operation...................................................................................... 15-1 15.1.1 Pin Assignment Register (PAR) ................................................................... 15-1 15.1.2 Port A Data Direction Register (PADDR).................................................... 15-2 15.1.3 Port A Data Register (PADAT) .................................................................... 15-2 15.1.4 Code Example............................................................................................... 15-3 xiv For More Information On This Product, CONTENTS Title Chapter 15 MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 15

... Freescale Semiconductor, Inc. Paragraph Number 16.1 Package ............................................................................................................. 16-1 16.2 Pinout ................................................................................................................ 16-1 16.3 Mechanical Diagram......................................................................................... 16-8 16.4 Case Drawing.................................................................................................... 16-9 17.1 Overview........................................................................................................... 17-1 17.2 MCF5307 Bus Signals ...................................................................................... 17-7 17.2.1 Address Bus .................................................................................................. 17-7 17.2.1.1 Address Bus (A[23:0]).............................................................................. 17-7 17.2.1.2 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7 17.2.2 Data Bus (D[31:0]) ....................................................................................... 17-8 17.2.3 Read/Write (R/W)......................................................................................... 17-8 17.2.4 Size (SIZ[1:0]) .............................................................................................. 17-8 17.2.5 Transfer Start (TS) ........................................................................................ 17-9 17.2.6 Address Strobe (AS) ..................................................................................... 17-9 17.2.7 Transfer Acknowledge (TA) ......................................................................... 17-9 17.2.8 Transfer In Progress (TIP/PP7)................................................................... 17-10 17.2.9 Transfer Type (TT[1:0]/PP[1:0]) ................................................................ 17-10 17.2.10 Transfer Modifier (TM[2:0]/PP[4:2])......................................................... 17-10 17.3 Interrupt Control Signals................................................................................. 17-12 17 ...

Page 16

... Debug Module/JTAG Signals......................................................................... 17-21 17.14.1 Test Reset/Development Serial Clock (TRST/DSCLK) ............................ 17-21 17.14.2 Test Mode Select/Breakpoint (TMS/BKPT) .............................................. 17-22 17.14.3 Test Data Input/Development Serial Input (TDI/DSI) ............................... 17-22 17.14.4 Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22 17.14.5 Test Clock (TCK) ....................................................................................... 17-23 xvi For More Information On This Product, CONTENTS Title MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 17

... Freescale Semiconductor, Inc. Paragraph Number 18.1 Features ............................................................................................................. 18-1 18.2 Bus and Control Signals ................................................................................... 18-1 18.3 Bus Characteristics............................................................................................ 18-2 18.4 Data Transfer Operation ................................................................................... 18-3 18.4.1 Bus Cycle Execution..................................................................................... 18-4 18.4.2 Data Transfer Cycle States ........................................................................... 18-5 18.4.3 Read Cycle.................................................................................................... 18-7 18.4.4 Write Cycle ................................................................................................... 18-8 18.4.5 Fast-Termination Cycles............................................................................... 18-9 18.4.6 Back-to-Back Bus Cycles ........................................................................... 18-10 18.4.7 Burst Cycles................................................................................................ 18-11 18.4.7.1 Line Transfers ......................................................................................... 18-12 18.4.7.2 Line Read Bus Cycles............................................................................. 18-12 18.4.7.3 Line Write Bus Cycles............................................................................ 18-14 18 ...

Page 18

... Timer Module AC Timing Specifications ...................................................... 20- Input/Output Timing Specifications......................................................... 20-15 20.8 UART Module AC Timing Specifications ..................................................... 20-16 20.9 Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-18 20.10 DMA Timing Specifications........................................................................... 20-19 20.11 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-20 xviii For More Information On This Product, CONTENTS Title Chapter 20 Electrical Specifications MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 19

... Freescale Semiconductor, Inc. Figure Number 1-1 MCF5307 Block Diagram............................................................................................. 1-2 1-2 UART Module Block Diagram..................................................................................... 1-9 1-3 PLL Module ................................................................................................................ 1-12 1-4 ColdFire MCF5307 Programming Model .................................................................. 1-13 2-1 ColdFire Enhanced Pipeline ....................................................................................... 2-23 2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25 2-3 ColdFire Programming Model.................................................................................... 2-27 2-5 Status Register (SR).................................................................................................... 2-30 2-6 Vector Base Register (VBR)....................................................................................... 2-30 2-7 Organization of Integer Data Formats in Data Registers............................................ 2-32 2-8 Organization of Integer Data Formats in Address Registers ...................................... 2-32 2-9 Memory Operand Addressing ...

Page 20

... Recommended BDM Connector................................................................................. 5-42 6-1 SIM Block Diagram...................................................................................................... 6-1 6-2 Module Base Address Register (MBAR) ..................................................................... 6-4 6-3 Reset Status Register (RSR) ......................................................................................... 6-5 6-4 MCF5307 Embedded System Recovery from Unterminated Access........................... 6-7 6-5 System Protection Control Register (SYPCR) ............................................................. 6-8 6-6 Software Watchdog Interrupt Vector Register (SWIVR)............................................. 6-9 6-7 Software Watchdog Service Register (SWSR)............................................................. 6-9 6-8 Pin Assignment Register (PAR) ................................................................................. 6-10 ...

Page 21

... Burst Page-Mode Write Operation (4-3-3-3)............................................................ 11-13 11-9 Continuous Page-Mode Operation............................................................................ 11-14 11-10 Write Hit in Continuous Page Mode......................................................................... 11-15 11-11 EDO Read Operation (3-2-2-2) ................................................................................ 11-15 11-12 DRAM Access Delayed by Refresh ......................................................................... 11-16 11-13 MCF5307 SDRAM Interface.................................................................................... 11-18 11-14 Using EDGESEL to Change Signal Timing............................................................. 11-19 For More Information On This Product, ILLUSTRATIONS Title 2 C Interrupt Routine ............................................................. 8-14 Illustrations Go to: www.freescale.com Page ...

Page 22

... Self-Refresh Operation ............................................................................................. 11-32 11-24 Mode Register Set (mrs) Command ......................................................................... 11-34 11-25 Initialization Values for DCR ................................................................................... 11-35 11-26 SDRAM Configuration............................................................................................. 11-36 11-27 DACR Register Configuration.................................................................................. 11-36 11-28 DMR0 Register ......................................................................................................... 11-37 11-29 Mode Register Mapping to MCF5307 A[31:0] ........................................................ 11-38 12-1 DMA Signal Diagram ................................................................................................. 12-1 12-2 Dual-Address Transfer................................................................................................ 12-3 12-3 Single-Address Transfers............................................................................................ 12-4 12-4 Source Address Registers (SARn) .............................................................................. 12-6 12-5 Destination Address Registers (DARn) ...................................................................... 12-7 12-6 Byte Count Registers (BCRn)—BCR24BIT = 1 ........................................................ 12-7 12-7 BCRn— ...

Page 23

... Port A Data Register (PADAT) .................................................................................. 15-3 16-1 Mechanical Diagram................................................................................................... 16-9 16-2 MCF5307 Case Drawing (General View) ................................................................ 16-10 16-3 Case Drawing (Details)............................................................................................. 16-11 17-1 MCF5307 Block Diagram with Signal Interfaces ...................................................... 17-2 18-1 Signal Relationship to BCLKO for Non-DRAM Access ........................................... 18-2 18-2 Connections for External Memory Port Sizes ............................................................ 18-4 18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4 18-4 Data Transfer State Transition Diagram ..................................................................... 18-6 18-5 Read Cycle Flowchart ...

Page 24

... MCF5307 Two-Wire Mode Bus Arbitration Interface............................................. 18-25 18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26 18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27 18-29 MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28 18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30 18-31 Three-Wire Bus Arbitration...................................................................................... 18-31 18-32 Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32 18-33 Master Reset Timing ...

Page 25

... General Branch Instruction Execution Times............................................................. 2-46 2-17 Bcc Instruction Execution Times................................................................................ 2-47 2-18 Exception Vector Assignments................................................................................... 2-48 2-19 Format Field Encoding ............................................................................................... 2-49 2-20 Fault Status Encodings................................................................................................ 2-50 2-21 MCF5307 Exceptions ................................................................................................. 2-50 3-1 MAC Instruction Summary........................................................................................... 3-4 3-2 Two-Operand MAC Instruction Execution Times ....................................................... 3-5 3-3 MAC Move Instruction Execution Times..................................................................... 3-6 4-1 RAMBAR Field Description ........................................................................................ 4-3 4-2 Examples of Typical RAMBAR Settings ..................................................................... 4-6 4-3 Valid and Modified Bit Settings ...

Page 26

... SR Field Descriptions ................................................................................................ 8-9 9-1 Interrupt Controller Registers ....................................................................................... 9-2 9-2 Interrupt Control Registers ........................................................................................... 9-2 9-3 ICRn Field Descriptions ............................................................................................... 9-3 9-4 Interrupt Priority Scheme.............................................................................................. 9-4 9-5 AVR Field Descriptions................................................................................................ 9-6 9-6 Autovector Register Bit Assignments........................................................................... 9-6 9-7 IPR and IMR Field Descriptions................................................................................... 9-7 xxvi For More Information On This Product, TABLES Title MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 27

... MCF5307 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 11-25 11-24 MCF5307 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 11-26 11-25 MCF5307to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) .............. 11-26 11-26 MCF5307 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26 11-27 MCF5307 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26 11-28 MCF5307 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 11-26 11-29 MCF5307 to SDRAM Interface (32-Bit Port, 11-Column Address Lines) ...

Page 28

... Pins 1–52 (Left, Top-to-Bottom) ................................................................................ 16-1 16-2 Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3 16-3 Pins 105–156 (Right, Bottom-to-Top)........................................................................ 16-4 16-4 Pins 157–208 (Top, Right-to-Left) ............................................................................. 16-6 16-5 Dimensions ............................................................................................................... 16-11 17-1 MCF5307 Signal Index............................................................................................... 17-3 17-2 Data Pin Configuration ............................................................................................... 17-6 17-3 Bus Cycle Size Encoding............................................................................................ 17-7 17-4 Bus Cycle Transfer Type Encoding............................................................................ 17-9 17-5 TM[2:0] Encodings for (Normal Access)..................................................... 17-9 17-6 TM0 Encoding for DMA as Master (TT = 01) ...

Page 29

... ColdFire Bus Arbitration Signal Summary............................................................... 18-21 18-8 Cycles for Basic No-Wait-State External Master Access......................................... 18-23 18-9 Cycles for External Master Burst Line Access to 32-Bit Port .................................. 18-24 18-10 MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions.................... 18-28 18-11 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32 18-12 Data Pin Configuration ............................................................................................. 18-35 19-1 JTAG Pin Descriptions ............................................................................................... 19-3 19-2 JTAG Instructions ...

Page 30

... Freescale Semiconductor, Inc. Table Number A-6 UART0 Control Registers............................................................................................ A-4 A-7 UART1 Control Registers............................................................................................ A-6 A-8 Parallel Port Memory Map........................................................................................... A Interface Memory Map.......................................................................................... A-8 A-10 DMA Controller Registers........................................................................................... A-8 xxx For More Information On This Product, TABLES Title MCF5307 User’s Manual Go to: www.freescale.com Page Number ...

Page 31

... Freescale Semiconductor, Inc. About This Book The primary objective of this user’s manual is to define the functionality of the MCF5307 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation the readers’ ...

Page 32

... Chapter 4, “Local Memory.” This chapter describes the MCF5307 implementation of the ColdFire V3 local memory specification. It consists of the two following major sections. – Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. – ...

Page 33

... DRAM Controller Module,” describes DRAM cycles. — Chapter 19, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the MCF5307 JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. — Chapter 20, “Electrical Specifications,” describes AC and DC electrical specifi ...

Page 34

... Freescale Semiconductor, Inc. Suggested Reading This manual includes the following appendix: • Appendix A, “List of Memory Maps,” lists the entire address-map for MCF5307 memory-mapped registers. This manual also includes a glossary and an index. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture ...

Page 35

... Freescale Semiconductor, Inc. italics Italics indicate variable command parameters. Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifi ...

Page 36

... Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter xxxvi For More Information On This Product, Meaning MCF5307 User’s Manual Go to: www.freescale.com ...

Page 37

... Freescale Semiconductor, Inc. Terminology and Notational Conventions Table ii shows notational conventions used throughout this document. Table ii Notational Conventions Instruction cc Logical condition (example: NE for not equal) An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example data register 5) ...

Page 38

... Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word xxxviii For More Information On This Product, Operand Syntax Operations Subfields and Qualifiers is a 16-bit displacement) 16 MCF5307 User’s Manual Go to: www.freescale.com ...

Page 39

... Freescale Semiconductor, Inc. Table ii Notational Conventions (Continued) Instruction Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero For More Information On This Product, Terminology and Notational Conventions Operand Syntax About This Book Go to: www.freescale.com xxxix ...

Page 40

... Freescale Semiconductor, Inc. Terminology and Notational Conventions xl For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 41

... Freescale Semiconductor, Inc. Chapter 1 Overview This chapter is an overview of the MCF5307 ColdFire processor. It includes general descriptions of the modules and features incorporated in the MCF5307. 1.1 Features The MCF5307 integrated microprocessor combines a V3 ColdFire processor core with the following components, as shown in Figure 1-1: • 8-Kbyte unified cache • ...

Page 42

... DRAM Controller Chip-Select Module DRAM Control 8 8 DCR CSARs CSCRs CSMRs Addr/Cntrl Mask DACR0/1 DMR0/1 8 DRAM Controller CS[7:0] Outputs Figure 1-1. MCF5307 Block Diagram 1-2 For More Information On This Product, V3 COLDFIRE PROCESSOR COMPLEX Instruction Unit Branch Logic CCR General- Purpose Registers A0– DSOC D0– ...

Page 43

... The MCF5307 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged. In fact, customers moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K assembly code to the ColdFire architecture ...

Page 44

... Freescale Semiconductor, Inc. MCF5307 Features 1.2 MCF5307 Features The following list summarizes MCF5307 features: • ColdFire processor core — Variable-length RISC, clock-multiplied Version 3 microprocessor core — Fully code compatible with Version 2 processors — Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and two-stage operand execution pipeline (OEP) — ...

Page 45

... Master or slave modes support multiple masters — Automatic interrupt generation with programmable level • System interface module (SIM) — Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM, For More Information On This Product bus Chapter 1. Overview Go to: www.freescale.com MCF5307 Features 1-5 ...

Page 46

... QFP package — 0°–70° C operating temperature 1.2.1 Process The MCF5307 is manufactured in a 0.35-µ CMOS process with triple-layer-metal routing technology. This process combines the high performance and low power needed for embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0 GND - 0.5 V, with guaranteed TTL-level specifi ...

Page 47

... MAC Module The MAC unit provides signal processing capabilities for the MCF5307 in a variety of applications including digital audio and servo control. Integrated as an execution unit in the processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers, plus signed, fi ...

Page 48

... DRAM Controller The MCF5307 DRAM controller provides a direct interface for up to two blocks of DRAM. The controller supports 8-, 16-, or 32-bit memory widths and can easily interface to PC-100 DIMMs. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards ...

Page 49

... Freescale Semiconductor, Inc. System Integration Module (SIM) Interrupt Controller Figure 1-2. UART Module Block Diagram Each UART module consists of the following major functional areas: • Serial communication channel • 16-bit divider for clock generation • Internal channel control logic • Interrupt control logic Each UART contains an programmable clock-rate generator ...

Page 50

... System Interface The MCF5307 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM, ROM, and peripheral devices through the use of fully programmable chip selects and write enables. Support for burst ROMs is also included. Through the on-chip PLL, users can input a slower clock (16 ...

Page 51

... This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug unit in the MCF5307 is a compatible upgrade to the MCF52xx debug module with added flexibility in the breakpoint registers and a new command to view the program counter (PC). The on-chip breakpoint resources include a total of 6 programmable registers— ...

Page 52

... The PLL module’s three modes of operation are described as follows. • Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO from the MCF5307. The core:bus frequency ratio and other MCF5307 configuration information are sampled during reset. ...

Page 53

... The supervisor programming model provides access to the same registers as the user model, plus additional registers for configuring on-chip system resources, as described in Section 1.4.3, “Supervisor Registers.” Exceptions (including interrupts) are handled in supervisor mode. 1.4.1 Programming Model Figure 1-4 shows the MCF5307 programming model Figure 1-4 ...

Page 54

... The base address registers can be used for word and longword operations. A7 functions as a hardware stack pointer during stacking for subroutine calls and exception handling. Program counter Contains the address of the instruction currently being executed by the MCF5307 processor (PC) Condition code The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous register (CCR) operation and are used for conditional instruction execution ...

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... Freescale Semiconductor, Inc. 1.4.4 Instruction Set The ColdFire instruction set supports high-level languages and is optimized for those instructions most commonly generated by compilers in embedded applications. Table 2-8 provides an alphabetized listing of the ColdFire instruction set opcodes, supported operation sizes, and assembler syntax. For two-operand instructions, the first operand is generally the source operand and the second is the destination ...

Page 56

... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1-16 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 57

... Freescale Semiconductor, Inc. Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5307. It also describes the operation of the MCF5307 Contents • Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the V2 ColdFire core, and then fully describes the V3 programming model implemented on the MCF5307 ...

Page 58

... Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit I-xviii For More Information On This Product, Meaning MCF5307 User’s Manual Go to: www.freescale.com ...

Page 59

... Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part I. MCF5307 Processor Core For More Information On This Product, Meaning Go to: www.freescale.com I-xix ...

Page 60

... Freescale Semiconductor, Inc. I-xx For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 61

... This chapter provides an overview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the Version 2 (V2) ColdFire core, and then fully describes the V3 programming model implemented on the MCF5307. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings ...

Page 62

... Freescale Semiconductor, Inc. Features and Enhancements 2.1.1 Clock-Multiplied Microprocessor Core The MCF5307 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The frequency of the processor complex can be 2x, 3x the external bus speed. ...

Page 63

... Freescale Semiconductor, Inc. IAG IC1 Instruction Fetch IC2 Pipeline IED IB Instruction Buffer Decode & Select, DSOC Operand Fetch Operand Execution Pipeline AGEX Figure 2-1. ColdFire Enhanced Pipeline 2.1.2.1 Instruction Fetch Pipeline (IFP) Because the fetch and execution pipelines are decoupled by an eight-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls ...

Page 64

... OEP, which can issue multiply with a 32-bit accumulation plus fetch a 32-bit operand in a single cycle multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued. 2-24 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 65

... Real-time trace and debug information can be accessed through a standard interface, which allows the processor and system to be debugged at full speed without costly in-circuit emulators. The MCF5307 debug unit is a compatible upgrade to the MCF52xx debug module with enhancements that include: • ...

Page 66

... A revision. For more information, see Chapter 5, “Debug Support.” 2.2 Programming Model The MCF5307 programming model consists of three instruction and register groups—user, MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are restricted to user and MAC instructions and programming models. Supervisor-mode system software can reference all user-mode and MAC instructions and registers and additional supervisor instructions and control registers ...

Page 67

... Freescale Semiconductor, Inc Figure 2-3. ColdFire Programming Model 2.2.1 User Programming Model As Figure 2-3 shows, the user programming model consists of the following registers: • 16 general-purpose 32-bit registers, D0–D7 and A0–A7 • 32-bit program counter • 8-bit condition code register 2.2.1.1 Data Registers (D0–D7) Registers D0– ...

Page 68

... Negative condition code bit. Set if the msb of the result is set; otherwise cleared Zero condition code bit. Set if the result equals zero; otherwise cleared. 2-28 For More Information On This Product — Undefined R R/W R/W R/W Description MCF5307 User’s Manual Go to: www.freescale.com R/W R/W ...

Page 69

... MACSR indicator flag settings are based on the final result, that is, the result of the final operation involving the product and accumulator. 2.2.2 Supervisor Programming Model The MCF5307 supervisor programming model is shown in Figure 2-3. Typically, system programmers use the supervisor programming model to implement operating system functions and provide memory and I/O control. The supervisor programming model ...

Page 70

... See Section 4.10.1, “Cache Control Register (CACR).” 2-30 For More Information On This Product Condition code register (CCR — 111 0 00 R/W R/W R Description 0000_0000_0000_0000_0000_0000_0000_0000 0x801 MCF5307 User’s Manual Go to: www.freescale.com — — — — — R/W R/W R/W R/W ...

Page 71

... Freescale Semiconductor, Inc. 2.2.2.4 Access Control Registers (ACR0–ACR1) The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions. Attributes include definition of cache mode, write protect and buffer write enables. See Section 4.10.2, “Access Control Registers (ACR0–ACR1).” ...

Page 72

... For More Information On This Product lsb Bit (0 ≤ bit number ≤ 31 msb Low order byte lsb Byte (8 bits msb Lower order word lsb Word (16 bits) 0 lsb Longword (32 bits 16-Bit Address Operand Full 32-Bit Address Operand MCF5307 User’s Manual Go to: www.freescale.com 0 0 ...

Page 73

... Freescale Semiconductor, Inc. organization is shown in Figure 2- Word 0x0000_0000 Byte 0x0000_0000 Byte 0x0000_0001 Word 0x0000_0004 Byte 0x0000_0004 Byte 0x0000_0005 Word 0xFFFF_FFFC Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Figure 2-9. Memory Operand Addressing 2.5 Addressing Mode Summary Addressing modes are categorized by how they are used. Data addressing modes refer to data operands ...

Page 74

... X X 111 010 X X 111 011 X X 111 000 X X 111 001 X X 111 100 X X Operand Syntax Opcode Wildcard MCF5307 User’s Manual Go to: www.freescale.com Category Control Alterable — X — — X — — X — X — ...

Page 75

... Freescale Semiconductor, Inc. Table 2-6. Notational Conventions (Continued) Instruction An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) ...

Page 76

... Most significant bit MSB Most significant byte MSW Most significant word 2-36 For More Information On This Product, Operand Syntax Operations Subfields and Qualifiers is a 16-bit displacement) 16 Condition Code Register Bit Names MCF5307 User’s Manual Go to: www.freescale.com ...

Page 77

... Freescale Semiconductor, Inc. Table 2-6. Notational Conventions (Continued) Instruction P Branch prediction C Carry N Negative V Overflow X Extend Z Zero 2.6.1 Instruction Set Summary Table 2-7 lists implemented user-mode instructions by opcode. Table 2-7. User-Mode Instruction Set Summary Instruction Operand Syntax ADD Dy,<ea>x .L <ea>y,Dx .L ADDA <ea>y,Ax .L ADDI #<data>,Dx .L ADDQ #<data>,<ea>x .L ADDX Dy,Dx ...

Page 78

... ACC + (Ry × Rx){<< >> 1} → ACC; (<ea>y{&MASK}) → Rw ACC + (Ry × Rx){<< >> 1} → ACC ACC + (Ry × Rx){<< >> 1} → ACC; (<ea-1>y{&MASK}) → Rw <ea>y → <ea>x Rm → Rx MACSR → CCR Ry → Rm #<data> → Rm CCR → → CCR #<data> → CCR Source → destination MCF5307 User’s Manual Go to: www.freescale.com Operation ...

Page 79

... Freescale Semiconductor, Inc. Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax MOVEM #<list>,<ea-2>x .L <ea-2>y,#<list> .L MOVEQ #<data>,Dx .B → .L MSAC Ry,RxSF .L - (.W × .W) → (.L × .L) → .L MSACL Ry,RxSF,<ea-1>y, (.W × .W) → . (.L × .L) → .L, .L MULS <ea>y, → → .L MULU < ...

Page 80

... This implies that the OEP spends no time waiting for the IFP to supply opwords and/or extension words. • The OEP experiences no sequence-related pipeline stalls. For the MCF5307, the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction ...

Page 81

... Freescale Semiconductor, Inc. certain hardware resources within the processor are marked as “busy” for two clock cycles after the final DSOC cycle of the store instruction subsequent store instruction is encountered within this two-cycle window stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive store operations is two cycles. • ...

Page 82

... Destination (Ax)+ -(Ax) (d16,Ax) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 4(1/1) — 3(1/1) 3(1/1) — 3(1/1) 3(1/1) — 3(1/1) 3(1/1) 3(1/1) 4(1/1) 4(1/1) — 2(0/1) 2(0/1) — MCF5307 User’s Manual Go to: www.freescale.com (d8,Ax,Xi*SF) (xxx).wl 2(0/1) 1(0/1) 2(0/1) 1(0/1) 5(1/1) 4(1/1) 5(1/1) 4(1/1) 5(1/1) 4(1/1) — — — — — — — — — — — — — — (d8,Ax,Xi*SF) (xxx).wl 2(0/1) 1(0/1) 2(0/1) 1(0/1) 4(1/1) 3(1/1) 4(1/1) 3(1/1) 4(1/1) 3(1/1) — — — — — — — — — ...

Page 83

... Freescale Semiconductor, Inc. in the MAC execution pipeline. Table 2-12. MAC Move Execution Times Opcode Í Rn move.l <ea>,ACC 1(0/0) move.l <ea>,MACSR 2(0/0) move.l <ea>,MASK 1(0/0) move.l ACC,Rx 3(0/0) move.l MACSR,CCR 3(0/0) move.l MACSR,Rx 3(0/0) move.l MASK,Rx 3(0/0) 2.7.2 Execution Timings—One-Operand Instructions Table 2-13 shows standard timings for single-operand instructions. Table 2-13. One-Operand Instruction Execution Times Opcode Í ...

Page 84

... MCF5307 User’s Manual Go to: www.freescale.com (xxx).wl #<xxx> 5(1/0) 4(1/0) 1(0/0) 5(1/1) 4(1/1) — — — — 5(1/1) 4(1/1) — — — — 5(1/0) 4(1/0) 1(0/0) 5(1/1) 4(1/1) — — — ...

Page 85

... Freescale Semiconductor, Inc. Table 2-14. Two-Operand Instruction Execution Times (Continued) Opcode Í Rn mac.l Ry,Rx,ea,Rw — moveq #imm,Dx — msac.w Ry,Rx,ea,Rw — msac.l Ry,Rx,ea,Rw — muls.w <ea>,Dx 3(0/0) mulu.w <ea>,Dx 3(0/0) muls.l <ea>,Dx 5(0/0) mulu.l <ea>,Dx 5(0/0) or.l <ea>,Rx 1(0/0) or.l Dy,<ea> — or.l #imm,Dx 1(0/0) rems.l <ea>,Dx 35(0/0) remu.l <ea>,Dx 35(0/0) sub.l <ea>,Rx 1(0/0) sub.l Dy,<ea> — subi.l #imm,Dx 1(0/0) subq.l #imm,<ea> 1(0/0) subx.l Dy,Dx 1(0/0) 2.7.4 Miscellaneous Instruction Execution Times Table 2-15 lists timings for miscellaneous instructions. ...

Page 86

... Effective Address (An)+ -(An) (d16,An) (d8,An,Xi*SF) 1 — — 1(0/1) 1 — — 1(0/1) 1 — — 5(0/0) — — 5(0/1) 6(0/1) 14(2/0) — — 8(1/0) — — MCF5307 User’s Manual Go to: www.freescale.com (d8,An,Xi*SF) (xxx).wl #<xxx> — — — 4 3(0/1) 2(0/1) — — — — 5 — — 3(0/0) — — 18(1/2) — — — — — — ...

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... Freescale Semiconductor, Inc. if bcc is a forward branch && CCR[ then the bcc is predicted as taken else if bcc is a backward branch then the bcc is predicted as taken Table 2-17 shows timing for Bcc instructions. Table 2-17. Bcc Instruction Execution Times Opcode Correctly as Taken bcc 2.8 Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance ...

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... Fault Unimplemented line-f opcode Next Debug interrupt — Reserved Fault Format error Next Uninitialized interrupt — Reserved Next Spurious interrupt Next Level 1–7 autovectored interrupts Next Trap #0–15 instructions — Reserved Fault Unsupported instruction MCF5307 User’s Manual Go to: www.freescale.com Assignment ...

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... Freescale Semiconductor, Inc. Table 2-18. Exception Vector Assignments (Continued) Vector Numbers Vector Offset (Hex) 62–63 0F8–0FC 64–255 100–3FC 1 The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC of the instruction that immediately follows the instruction that caused the fault. ...

Page 90

... Vector number—This 8-bit field, vector[7–0], defines the exception type calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-18. 2.8.2 Processor Exceptions Table 2-21 describes MCF5307 exceptions. Table 2-21. MCF5307 Exceptions Exception Access Error Access errors are reported only in conjunction with an attempted store to write-protected memory. ...

Page 91

... Freescale Semiconductor, Inc. Table 2-21. MCF5307 Exceptions (Continued) Exception Trace ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode Exception (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this definition is the STOP instruction. If the processor is in trace mode, the instruction before the STOP executes and then generates a trace exception ...

Page 92

... PC access error or address error occurs before the first instruction executes, the processor enters the fault-on-fault halted state. Unsupported If the MCF5307 attempts to execute a valid instruction but the required optional hardware module is Instruction not present in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is Exception then passed to an exception handler that can then process the opcode as required by the system ...

Page 93

... ColdFire microprocessor family. The MAC unit provides signal processing capabilities for the MCF5307 in a variety of applications including digital audio and servo control. Integrated as an execution unit in the processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, fi ...

Page 94

... Figure 3-2 shows the registers in the MAC portion of the user programming model. 31 Figure 3-2. MAC Programming Model 3-2 For More Information On This Product, Operand Y Operand X X Shift 0,1,-1 +/- Accumulator 0 MACSR MAC status register ACC MAC accumulator MASK MAC mask register MCF5307 User’s Manual Go to: www.freescale.com ...

Page 95

... Freescale Semiconductor, Inc. These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. • Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory useful in the implementation of circular queues in operand memory. • ...

Page 96

... Loads the accumulator with a 32-bit operand Writes the contents of the accumulator to a register Write the contents of MACSR to a register Write the contents of MACSR to the processor’s CCR register Writes a value to MASK Writes the contents of MASK to a register MCF5307 User’s Manual Go to: www.freescale.com ...

Page 97

... Freescale Semiconductor, Inc. • Two’s complement signed integer: In this format, an N-bit operand represents a number within the range -2 of the least significant bit. • Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 < operand < 2 least signifi ...

Page 98

... MCF5307 User’s Manual Go to: www.freescale.com (d8,An,Xi*SF) (xxx).wl #<xxx> — — 1(0/0) — — 6(0/0) — — 5(0/0) — — — — — — — ...

Page 99

... Freescale Semiconductor, Inc. Chapter 4 Local Memory This chapter describes the MCF5307 implementation of the ColdFire Version 3 local memory specification. It consists of two major sections. • Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization ...

Page 100

... Other heavily-referenced data can be mapped into memory. The following summarizes features of the MCF5307 SRAM implementation: • 4-Kbyte SRAM, organized as 1024 x 32 bits • Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle. • ...

Page 101

... Freescale Semiconductor, Inc. Accesses are attempted in the following order: 1. SRAM 2. Cache (if space is defined as cacheable) 3. External access 4.4 SRAM Programming Model The SRAM programming model consists of RAMBAR. 4.4.1 SRAM Base Address Register (RAMBAR) The SRAM modules are configured through the RAMBAR, shown in Figure 4-1. ...

Page 102

... DMA execution where the core can execute code 4-4 For More Information On This Product, Description Read the RAM and return the data if (RAMBAR[ Write the data into the RAM else Signal a write-protect access error MCF5307 User’s Manual Go to: www.freescale.com ...

Page 103

... Freescale Semiconductor, Inc. out of internal SRAM or cache during DMA access. The ColdFire processor or an external emulator using the debug module can perform these initialization functions. 4.5.1 SRAM Initialization Code The code segment below initializes the SRAM. The code sets the base address of the SRAM at 0x2000_0000 and then initializes the RAM to zeros ...

Page 104

... It describes cache operations and how the cache interacts with other memory structures. The MCF5307 processor contains a nonblocking, 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with a 16-byte line size. The cache improves system performance by providing low-latency access to the instruction and data pipelines. This decouples processor performance from system memory performance, increasing bus availability for on-chip DMA or external devices ...

Page 105

... Freescale Semiconductor, Inc. Control ColdFire Processor Directory Array Core Data Address Address Path Figure 4-2. Unified Cache Organization The cache supports operation of copyback, write-through, or cache-inhibited modes. The cache lock feature can be used to guarantee deterministic response for critical code or data areas. A nonblocking cache services read hits or write hits from the processor while a fill (caused by a cache allocation progress ...

Page 106

... Valid, modified. Cache line contains most recent data, data at system memory location is stale. A valid line can be explicitly invalidated by executing a CPUSHL instruction. 4-8 For More Information On This Product, Way 1 Way 2 • • • • • • Line Cache Line Format Longword 0 Longword 1 Description MCF5307 User’s Manual Go to: www.freescale.com Way 3 • • • Longword 2 Longword 3 ...

Page 107

... Freescale Semiconductor, Inc. 4.8.2 The Cache at Start-Up As Figure 4-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines even though the cache may not contain the appropriate data for start up. Because reset and power-up do not invalidate cache lines automatically, the cache should be cleared explicitly by setting CACR[CINVA] before the cache is enabled (B). After the entire cache is fl ...

Page 108

... For More Information On This Product, C:Cache after loads in Way 0 Way 0 Way 1 Way 2 Way 3 Initial cacheable accesses to memory-fill positions in way 0. MCF5307 User’s Manual Go to: www.freescale.com D:First load in Way 1 Way 0 Way 1 Way 2 Way 3 A line is loaded in way 1 only if that set is full in way 0. ...

Page 109

... Freescale Semiconductor, Inc. 4.9 Cache Operation Figure 4-5 shows the general fl caching operation. Address 31 11 Tag Data/Tag Reference Set Select A[10:4] Address A[31:11] Figure 4-5. Caching Operation The following steps determine if a cache line is allocated for a given address: 1. The cache set index, A[10:4], selects one cache set. ...

Page 110

... Validity is provided only on a line basis. Unless a whole line is loaded on a cache miss, the cache controller does not validate data in the cache line. Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and perform a corresponding external write. 4-12 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 111

... Freescale Semiconductor, Inc. Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to this normal operation occurs when all of the following conditions are true during a cache-inhibited read: • The cache-inhibited fill buffer bit, CACR[DNFB], is set. • The access is an instruction read. ...

Page 112

... Memory regions can be designated as cache-inhibited, which is useful for memory containing targets such as I/O devices and shared data structures in multiprocessing systems also important to not cache the MCF5307 memory mapped registers. If the corresponding ACRn[CM] or CACR[DCM] indicates cache-inhibited, precise or imprecise, the access is cache-inhibited. The caching operation is identical for both cache-inhibited modes, which differ only regarding recovery from an external bus error ...

Page 113

... Freescale Semiconductor, Inc. 3. ACR1 access does not hit in the RAMBAR or the ACRs, the default is provided for all accesses in CACR. Cache-inhibited write accesses bypass the cache and a corresponding external write is performed. Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the following conditions are true: • ...

Page 114

... The data is 4-16 For More Information On This Product, Cache Line 0x0C 0x08 0x04 0x00 0x0C 0x08 0x04 0x00 0x0C 0x08 0x04 0x00 MCF5307 User’s Manual Go to: www.freescale.com System Memory ...

Page 115

... The cache does not support snooping (that is, cache coherency is not supported while external or DMA masters are using the bus). Therefore, on-chip DMAs of the MCF5307 cannot access local memory and do not maintain coherency with the unified cache. ...

Page 116

... Push and Store Buffer Bus Operation As soon as the push or store buffer has valid data, the internal bus controller uses the next available external bus cycle to generate the appropriate write cycles. In the event that 4-18 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 117

... Freescale Semiconductor, Inc. another cache fill is required (for example, cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline stalls until the push and store buffers are empty, then generate the required external bus transaction. Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding ...

Page 118

... Way 0 Way 1 Way 2 Way 3 While the cache is locked and after a position in ways is full, the set in Way 3 is updated. Figure 4-7. Cache Locking MCF5307 User’s Manual Go to: www.freescale.com D:Write hits to ways 0 and 1 update cache lines. Way 0 Way 1 Way 2 Way 3 While the cache is locked, ways 0 and 1 can be updated by write hits ...

Page 119

... Freescale Semiconductor, Inc. 4.10 Cache Registers This section describes the MCF5307 implementation of the Version 3 cache registers. 4.10.1 Cache Control Register (CACR) The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction and can be read or written from the debug facility. A hardware reset clears CACR, which disables the cache ...

Page 120

... Registers are accessed with the MOVEC instruction with the Rc encodings in Figure 4-9. For overlapping regions, ACR0 takes priority. Data transfers to and from these registers are longword transfers. Bits 12– and 0 are always read as zeros. 4-22 For More Information On This Product, Description MCF5307 User’s Manual Go to: www.freescale.com ...

Page 121

... Freescale Semiconductor, Inc. The SIM MBAR region should be mapped as cache-inhibited through an ACR Field Address Base Reset Uninitialized R/W Rc Figure 4-9. Access Control Register Format (ACRn) Table 4-5 describes ACRn fields. I Table 4-5. ACRn Field Descriptions Bits Name 31–24 Address Address base. Compared with address bits A[31:24]. Eligible addresses that match are base assigned the access control attributes of this register ...

Page 122

... MCF5307 User’s Manual Go to: www.freescale.com Line Index ...

Page 123

... Freescale Semiconductor, Inc. move.l d0,a0 cmpi.l #4,d0 bne setloop rts The following CACR loads assume the default cache mode is copyback. CacheLoadAndLock: move.l #0xA1000100,d0; enable and invalidate cache ... movec d0,cacr ; ... in the CACR The following code preloads half of the cache (4 Kbytes). It assumes a contiguous block of data mapped into the cache, starting at a 0-modulo-4K address. ...

Page 124

... CV3—CPU write miss CV4—CPU write hit Modified WI1—CPU read miss WV5—CINVA WV6—CPUSHL & DPI MCF5307 User’s Manual Go to: www.freescale.com CV1—CPU read miss CV2—CPU read hit CV7—CPUSHL & DPI Valid WV1— ...

Page 125

... Freescale Semiconductor, Inc. Table 4-6. Cache Line State Transitions Access Invalid ( Read (C,W)I1 Read line from miss memory and update cache; supply data to processor valid state. Read hit (C,W)I2 Not possible. Write CI3 Read line from miss memory and update (copy- cache; ...

Page 126

... Write data to memory; stay in valid state. CV4 Write data to cache modified state. WV4 Write data to memory and to cache; stay in valid state. (C,W)V5 No action invalid state. (C,W)V6 No action invalid state. (C,W)V7 No action; stay in valid state. MCF5307 User’s Manual Go to: www.freescale.com ...

Page 127

... Freescale Semiconductor, Inc. In the current state is modified. Table 4-9. Cache Line State Transitions (Current State Modified) Access Read miss CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; ...

Page 128

... Freescale Semiconductor, Inc. Cache Initialization Code 4-30 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 129

... Freescale Semiconductor, Inc. Chapter 5 Debug Support This chapter describes the Revision B enhanced hardware debug support in the MC5307. This revision of the ColdFire debug architecture encompasses the earlier revision. 5.1 Overview The debug module is shown in Figure 5-1. ColdFire CPU Core Debug Module Control PST[3:0], DDATA[3:0] BKPT Figure 5-1 ...

Page 130

... These output signals report the processor status. Table 5-2 shows the encoding of these (PST[3:0]) signals. These outputs indicate the current status of the processor pipeline and result, are not related to the current bus transfer. The PST value is updated each processor cycle. 5-2 For More Information On This Product, Description MCF5307 User’s Manual Go to: www.freescale.com ...

Page 131

... Freescale Semiconductor, Inc. Figure 5-2 shows PSTCLK timing with respect to PST and DDATA. PSTCLK PST DDATA or 5.3 Real-Time Trace Support Real-time trace, which defines the dynamic execution path fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to be displayed (debug data, DDATA) ...

Page 132

... Because this encoding defines a multiple-cycle mode, PSToutputs are driven with 0xD until exception processing completes. 0xE 1110 Processor is stopped. Appears in multiple-cycle format when the MCF5307 executes a STOP instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped mode is exited 0xF 1111 Processor is halted. Because this encoding defi ...

Page 133

... C language case statement. Typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. For such change-of-flow operations, the MCF5307 uses the debug pins to output the following sequence of information on successive processor clock cycles: 1 ...

Page 134

... CSR[IPW]). BDM commands must not be issued if the MCF5307 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined. These registers, shown in Figure 5-4, are treated as 32-bit quantities, regardless of the number of implemented bits ...

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... Freescale Semiconductor, Inc. Table 5-3. BDM/Breakpoint Registers DRc[4–0] Register Name 0x00 Configuration/status register 0x01–0x04 Reserved 0x05 BDM address attribute register 0x06 Address attribute trigger register 0x07 Trigger definition register 0x08 Program counter breakpoint register 0x09 Program counter breakpoint mask register 0x0A– ...

Page 136

... The trigger definition register (TDR) identifies the trigger as one of three cases: 1. identically the value in ABLR 2. inside the range bound by ABLR and ABHR inclusive 3. outside that same range 5-8 For More Information On This Product, Description MCF5307 User’s Manual Go to: www.freescale.com ...

Page 137

... Freescale Semiconductor, Inc. 31 Field Reset R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the BDM port using the WDMREG DRc[4– ...

Page 138

... UHE BTB — NPL R/W R/W R R/W 0x00 commands. WDMREG MCF5307 User’s Manual Go to: www.freescale.com — BKD — IPW — — — 0 — — — R IPI SSM — ...

Page 139

... HRL Hardware revision level. Indicates the level of debug module functionality. An emulator could use this information to identify the level of functionality supported. 0000 Initial debug functionality (Revision A) 0001 Revision B (this is the only valid value for the MCF5307) 19 — Reserved, should be cleared. 18 BKD Breakpoint disable ...

Page 140

... WDMREG DRc[4–0] Figure 5-9. Data Breakpoint/Mask Registers (DBR and DBMR) 5-12 For More Information On This Product, Description command, the processor executes the GO Data (DBR); Mask (DBMR) Uninitialized and commands. RDMREG WDMREG command. 0x0E (DBR), 0x0F (DBMR) MCF5307 User’s Manual Go to: www.freescale.com 0 ...

Page 141

... Freescale Semiconductor, Inc. Table 5-9 describes DBR fields. Table 5-9. DBR Field Descriptions Bits Name 31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger. Table 5-10 describes DBMR fields. Table 5-10. DBMR Field Descriptions ...

Page 142

... Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] define the second-level trigger and bits 15–0 define the first-level trigger. 5-14 For More Information On This Product, Program Counter — and commands using values shown in Section 5.5.3.3, “Command WDMREG 0x08 Description Mask — 0x09 Description MCF5307 User’s Manual Go to: www.freescale.com ...

Page 143

... Freescale Semiconductor, Inc. The debug module has no hardware interlocks prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13] before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. Section Table 5-14., “TDR Field Descriptions,” describes how to handle multiple breakpoint conditions ...

Page 144

... BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority catastrophic fault-on-fault condition automatically halts the processor. 5-16 For More Information On This Product, Description MCF5307 User’s Manual Go to: www.freescale.com ...

Page 145

... Freescale Semiconductor, Inc hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 5.6.1, “ ...

Page 146

... C4—DSO changes to next value. A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 5-18 For More Information On This Product Current NOTE: MCF5307 User’s Manual Go to: www.freescale.com Next Next State Current ...

Page 147

... Freescale Semiconductor, Inc. 5.5.2.1 Receive Packet Format The basic receive packet, Figure 5-14, consists of 16 data bits and 1 status bit Figure 5-14. Receive BDM Packet Table 5-15 describes receive BDM packet fields. Table 5-15. Receive BDM Packet Field Description Bits Name 16 S Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress ...

Page 148

... For More Information On This Product, Description to dump large blocks of memory. READ is executed to set up the starting to fill large blocks of memory. An WRITE is executed to set up the starting and return the illegal command response. NOP MCF5307 User’s Manual Go to: www.freescale.com CPU Command Section 1 State (Hex) Halted 5.5.3.3.1 0x218 {A/D, ...

Page 149

... Freescale Semiconductor, Inc. 15 Operation Figure 5-16. BDM Command Format Table 5-18 describes BDM fields. Table 5-18. BDM Field Descriptions Bit Name 15–10 Operation Specifies the command. These values are listed in Table 5-17 Reserved 8 R/W Direction of operand transfer. 0 Data is written to the CPU or to memory from the development system. ...

Page 150

... LS ADDR MEMORY "NOT READY" LOCATION NEXT CMD "NOT READY" DATA UNUSED FROM THIS TRANSFER HIGH- AND LOW-ORDER 16 BITS OF RESULT READ NOTE: MCF5307 User’s Manual Go to: www.freescale.com SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED NEXT COMMAND XXX CODE "NOT READY" XXX XXXXX ...

Page 151

... Freescale Semiconductor, Inc. • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the fi ...

Page 152

... For More Information On This Product RAREG RDREG 0x1 0x8 D[31:16] D[15:0] / Command Format RAREG RDREG XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD "NOT READY" BERR / Command Sequence RAREG RDREG MCF5307 User’s Manual Go to: www.freescale.com A/D Register ...

Page 153

... Freescale Semiconductor, Inc. 5.5.3.3.2 Write A/D Register ( The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format 0x2 Figure 5-20. Command Sequence WDREG/WAREG ??? Figure 5-21. Operand Data Longword data is written into the specifi ...

Page 154

... A[31:16] A[15:0] D[31:16] D[15:0] Command/Result Formats READ READ LS ADDR MEMORY "NOT READY" LOCATION READ LS ADDR MEMORY "NOT READY" LOCATION Command Sequence READ MCF5307 User’s Manual Go to: www.freescale.com 0x0 D[7:0] 0x0 0x0 XXX "NOT READY" XXX NEXT CMD RESULT XXX NEXT CMD " ...

Page 155

... Freescale Semiconductor, Inc. 5.5.3.3.4 Write Memory Location ( Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned ...

Page 156

... READY" LOCATION LS ADDR MS DATA "NOT READY" "NOT READY" WRITE LS DATA MEMORY "NOT READY" LOCATION Command Sequence WRITE MCF5307 User’s Manual Go to: www.freescale.com XXX "NOT READY" XXX NEXT CMD "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" XXX "NOT READY" ...

Page 157

... Freescale Semiconductor, Inc. 5.5.3.3.5 Dump Memory Block ( is used with the command to access large blocks of memory. An initial DUMP READ is executed to set up the starting address of the block and to retrieve the first result initial is not executed before the first READ The command retrieves subsequent operands. The initial address is incremented by DUMP the operand size ( and saved in a temporary register ...

Page 158

... READY" BERR READ XXX MEMORY "NOT READY" LOCATION NEXT CMD MS RESULT XXX XXX NEXT CMD "ILLEGAL" "NOT READY" BERR Command Sequence DUMP MCF5307 User’s Manual Go to: www.freescale.com NEXT CMD "NOT READY" NEXT CMD LS RESULT NEXT CMD "NOT READY" ...

Page 159

... Freescale Semiconductor, Inc. 5.5.3.3.6 Fill Memory Block ( A command is used with the FILL initial is executed to set up the starting address of the block and to supply the first WRITE operand. The command writes subsequent operands. The initial address is incremented FILL by the operand size ( and saved in a temporary register after the memory write. ...

Page 160

... READY" "CMD COMPLETE" WRITE XXX MEMORY "NOT READY" LOCATION NEXT CMD NEXT CMD "CMD COMPLETE" "NOT READY" XXX BERR Command Sequence FILL MCF5307 User’s Manual Go to: www.freescale.com XXX NEXT CMD XXX NEXT CMD BERR "NOT READY" NEXT CMD "NOT READY" ...

Page 161

... Freescale Semiconductor, Inc. 5.5.3.3.7 Resume Execution ( The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes CPU is not halted, the command is ignored ...

Page 162

... Result Data: The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation. 5-34 For More Information On This Product, ) NOP 8 7 0x0 0x0 Command Format NOP NOP NEXT CMD ??? "CMD COMPLETE" Command Sequence NOP MCF5307 User’s Manual Go to: www.freescale.com 0x0 ...

Page 163

... Freescale Semiconductor, Inc. 5.5.3.3.9 Synchronize PC to the PST/DDATA Lines ( The _ command captures the current PC and displays it on the PST/DDATA SYNC PC outputs. After the debug module receives the command, it sends a signal to the ColdFire processor that the current PC must be displayed. The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of CSR[BTB]. The specifi ...

Page 164

... Program register (PC) 1 0xC04 RAM base address register (RAMBAR) READ EXT WORD MS ADDR CONTROL MEMORY "NOT READY" REGISTER LOCATION Command Sequence RCREG MCF5307 User’s Manual Go to: www.freescale.com 0x0 0x0 Register Definition 1 1 XXX "NOT READY" NEXT CMD ...

Page 165

... Freescale Semiconductor, Inc. 5.5.3.3.11 Write Control Register ( The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats Command 0x2 0x0 0x0 Result Figure 5-38. Command Sequence: WCREG EXT WORD MS ADDR ??? "NOT READY" Figure 5-39. ...

Page 166

... D[31:16] D[15:0] Command/Result Formats RDMREG BDM Mnemonic CSR — XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD "ILLEGAL" "NOT READY" Command Sequence RDMREG MCF5307 User’s Manual Go to: www.freescale.com DRc Initial State Page 0x0 p. 5-10 — — ...

Page 167

... Freescale Semiconductor, Inc. 5.5.3.3.13 Write Debug Module Register ( The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. ...

Page 168

... The core enters emulator mode when exception processing begins. After the standard 8-byte exception stack is created, the processor 5-40 For More Information On This Product, 1 Breakpoint Status No breakpoints enabled Waiting for level-1 breakpoint Level-1 breakpoint triggered Waiting for level-2 breakpoint Level-2 breakpoint triggered MCF5307 User’s Manual Go to: www.freescale.com ...

Page 169

... Freescale Semiconductor, Inc. fetches a unique exception vector, 12, from the vector table. Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area ...

Page 170

... CSR. 5-42 For More Information On This Product BKPT 3 4 DSCLK 5 6 Developer reserved 7 8 DSI 9 10 DSO 11 12 PST3 13 14 PST1 15 16 DDATA3 17 18 DDATA1 19 20 GND 21 22 Motorola reserved 23 24 CLK_CPU MCF5307 User’s Manual Go to: www.freescale.com 1 ...

Page 171

... Freescale Semiconductor, Inc. The CSR provides capabilities to display operands based on reference type (read, write, or both). Additionally, for certain change-of-flow branch instructions, another CSR field provides the capability to display {0x2, 0x3, 0x4} bytes of the target instruction address. For both situations, an optional PST value {0x8, 0x9, 0xB} provides the marker identifying the size and presence of valid data on the DDATA output ...

Page 172

... PST = 0x1, {PST = 0x8 source}, {PST = 0x8 destination} PST = 0x1, {PST = 0xB source}, {PST = 0xB destination} PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1, {PST = 0x9 source}, {PST = 0x9 destination} PST = 0x1 PST = 0x1 MCF5307 User’s Manual Go to: www.freescale.com 1 1 ...

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... Freescale Semiconductor, Inc. Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax movem.l #list,<ea>x PST = 0x1, {PST = 0xB destination},... movem.l <ea>y,#list PST = 0x1, {PST = 0xB source},... moveq #imm,Dx PST = 0x1 msac.l Ry,Rx PST = 0x1 msac.l Ry,Rx,ea,Rw PST = 0x1, {PST = 0xB source}, {PST = 0xB destination} msac ...

Page 174

... PST = 0x4, {PST = 0x8 source operand PST = 0x4, {PST = 0xB source operand PST = 0x4, {PST = 0x9 source operand {PST = 0xB destination},// stack frame {PST = 0xB source},// vector read PSTDDATA PST = 0x1 PST = 0x1, PST = 0xF PST = 0x1 PST = 0x1, {PST = 3} MCF5307 User’s Manual Go to: www.freescale.com ...

Page 175

... Freescale Semiconductor, Inc. Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions Instruction Operand Syntax movec Ry,Rc rte stop #imm wdebug <ea>y The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled. ...

Page 176

... Freescale Semiconductor, Inc. Processor Status, DDATA Definition 5-48 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 177

... PLL module. It describes in detail the registers and signals that support the PLL implementation. • Chapter 8, “I2C Module,” describes the MCF5307 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. ...

Page 178

... Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex II-ii For More Information On This Product, Meaning MCF5307 User’s Manual Go to: www.freescale.com ...

Page 179

... Freescale Semiconductor, Inc. Table II-i. Acronyms and Abbreviated Terms (Continued) Term NOP No operation PCLK Processor clock PLL Phase-locked loop POR Power-on reset Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part II ...

Page 180

... Freescale Semiconductor, Inc. II-iv For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 181

... SIM Overview This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5307. 6.1 Features The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices. ...

Page 182

... Default bus master park register (MPARK) controls internal and external bus arbitration and enables display of internal accesses on the external bus for debugging — Supports several arbitration algorithms See Section 6.2.10, “Bus Arbitration Control.” 6-2 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

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... Address Register (MBAR).” Because SIM registers depend on the base address defined in MBAR[BA], MBAR must be programmed before SIM registers can be accessed. Although external masters cannot access the MCF5307’s on-chip memories or MBAR, they can access any of the SIM memory map and peripheral registers, such as those belonging ...

Page 184

... For More Information On This Product, [23:16] [15:8] Timer0 (ICR1) [p. 9-3] Timer1 (ICR2) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA3 (ICR9) [p. 9-3] NOTE — WP — Undefined CPU + 0x0C0F MCF5307 User’s Manual Go to: www.freescale.com [7: (ICR3) [p. 9-3] DMA1 (ICR7) [p. 9-3] Reserved Attribute Mask Bits ...

Page 185

... Freescale Semiconductor, Inc. Table 6-2 describes MBAR fields. Table 6-2. MBAR Field Descriptions Bits Field 31–12 BA Base address. Defines the base address for a 4-Kbyte address range. 11–9 — Reserved, should be cleared Write protect. Mask bit for write cycles in the MBAR-mapped register address range. ...

Page 186

... IACK cycle to proceed. The setting of SYPCR[SWTAVAL] indicates that the watchdog timer TA was asserted. Figure 6-4 shows termination of a locked bus. 6-6 For More Information On This Product, Description MCF5307 User’s Manual Go to: www.freescale.com ...

Page 187

... SYPCR[SWTAVAL] 1 SWTAVAL is set if watchdog timer TA is asserted. Figure 6-4. MCF5307 Embedded System Recovery from Unterminated Access When the watchdog timer times out and SYPCR[SWRI] is programmed for a software reset, an internal reset is asserted and RSR[SWTR] is set. To prevent the watchdog timer from interrupting or resetting, the SWSR must be serviced by performing the following sequence: 1 ...

Page 188

... For More Information On This Product SWP SWT SWTA 0000_0000 R/W MBAR + 0x01 Description SWP = /system frequency /system frequency /system frequency /system frequency MCF5307 User’s Manual Go to: www.freescale.com 1 0 SWTAVAL — ...

Page 189

... Freescale Semiconductor, Inc. Table 6-4. SYPCR Field Descriptions (Continued) Bits Name 2 SWTA Software watchdog transfer acknowledge enable 0 SWTA transfer acknowledge disabled 1 SWTA asserts transfer acknowledge enabled. After one timeout period of the unacknowledged assertion of the software watchdog timer interrupt, the software watchdog transfer acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the IACK to occur ...

Page 190

... SIM, and are described as follows: • PLLCR[ENBSTOP] must be set for the ColdFire CPU STOP instruction to be acknowledged. This bit is cleared at reset and must be set for the MCF5307 to enter low-power modes. The CPU STOP instruction stops only clocks to the core processor ...

Page 191

... Use of this field is described in detail in Section 6.2.10.1.1, “Arbitration for Internally Generated Transfers (MPARK[PARK]).” 5 IARBCTRL Internal bus arbitration control. Controls external device access to the MCF5307 internal bus. 0 Arbitration disabled (single-master system) 1 Arbitration enabled. IARBCTRL must be set if external masters are using internal resources like the DRAM controller or chip selects. ...

Page 192

... DMA transfer, bus mastership returns to the core rather than being granted to DMA channel 1. 6-12 For More Information On This Product, Description DMA MODULE Channel 0 5th Channel 1 4th Channel 2 3rd Channel 3 2nd 1st MCF5307 User’s Manual Go to: www.freescale.com ...

Page 193

... Freescale Semiconductor, Inc. Note that the internal DMA has higher priority than the core if the internal DMA has its bandwidth BWC bits set to 000 (maximum bandwidth). • Park on master core priority (PARK = 01)—The core retains bus mastership as long as it needs it. After it negates its internal bus request, the core does not have to rearbitrate for the bus unless the DMA module has requested the bus when it is idle ...

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... In a single-master system, the setting of EARBCTRL does not affect arbitration performance. Typically tied low and the MCF5307 always owns the external bus and internal register transfers are already shown on the external bus system where MCF5307 is the only master, this bit may remain cleared ...

Page 195

... Freescale Semiconductor, Inc. memories from responding to internal register transfers that go to the external bus. The AS signal and all chip-select-related strobe signals are not asserted. Do not immediately follow a cycle in which SHOWDATA is set with a cycle using fast termination. • In multiple-master systems, disabling arbitration with EARBCTRL allows performance improvement because internal register bus transfer cycles do not interfere with the external bus ...

Page 196

... Freescale Semiconductor, Inc. Programming Model 6-16 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...

Page 197

... It describes in detail the registers and signals that support the PLL implementation. 7.1 Overview The basic features of the MCF5307 PLL implementation are as follows: • The PLL locks to the clock input (CLKIN) frequency. It provides a processor clock (PCLK) that is twice the input clock frequency and a programmable system bus clock output (BCLKO) that is 1/2, 1/3, or 1/4 the PCLK frequency. • ...

Page 198

... Reduced-Power Mode The PCLK can be turned off in a predictable manner to conserve system power. To allow fast restart of the MCF5307 processor core, the PLL continues to operate at the frequency configured at reset. PCLK is disabled using the CPU STOP instruction and resumes normal operation on interrupt, as described in Section 7.2.4, “PLL Control Register (PLLCR).” ...

Page 199

... Freescale Semiconductor, Inc. 7.2.4 PLL Control Register (PLLCR) The PLL control register (PLLCR), Figure 7-2, provides control over the PLL Field ENBSTOP Reset R/W Address Figure 7-2. PLL Control Register (PLLCR) Table 7-1 describes PLLCR bits. Table 7-1. PLLCR Field Descriptions Bit Name 7 ENBSTOP Enable CPU STOP instruction. Must be set for the ColdFire CPU STOP instruction to be acknowledged ...

Page 200

... MHz – MHz 11 Not used DIVIDE[1:0] The MCF5307 samples clock ratio encodings on the lower data bits of the bus to determine the CLKIN-to-processor clock ratio. D[1:0]/DIVIDE[1:0] support the divide-ratio combinations. 00 1/4 01 Not used 10 1/2 11 1/3 Table 7-3 describes PLL module outputs. ...

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