MC68LC302 Freescale Semiconductor, Inc, MC68LC302 Datasheet
MC68LC302
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... Motorola, Inc. Motorola, Inc Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, MC68LC302 Reference Manual ...
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... MC68302; the MC68000 Family Programmer’s Reference Manual provides instruction details for the MC68LC302; and the MC68LC302 Low Power Integrated Multipro- tocol Processor Product Brief provides a brief description of the MC68LC302 capabilities. The MC68302 Integrated Multiprotocol Processor User’s Manual is required, since the MC68LC302 Low Power Integrated Multiprotocol Processor Reference Manual only de- scribes the new features of the MC68LC302 ...
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... HYBRID COMPONENTS RESELLERS 81(03)3440-3311 Elmo Semiconductor 81(045)472-2751 Minco Technology Labs Inc. 82(51)4635-035 Semi Dice Inc. 82(2)554-5188 MC68LC302 REFERENCE MANUAL (508) 481-8100 (617) 932-9700 (313) 347-6800 (612) 932-1500 (314) 275-7380 (201) 808-2400 (716) 425-4000 (516) 361-7000 (914) 473-8102 (919) 870-4355 ...
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... Block Diagram......................................................................................... 1-1 1.2 Features .................................................................................................. 1-2 1.3 LC302 Applications ................................................................................. 1-3 1.4 LC302 Differences .................................................................................. 1-3 Configuration, Clocking, Low Power Modes, and Internal Memory Map 2.1 MC68LC302 and MC68302 Signal Differences ...................................... 2-1 2.2 IMP Configuration Control....................................................................... 2-2 2.2.1 Base Address Register ........................................................................... 2-4 2.3 System Configuration Registers.............................................................. 2-5 2.4 Clock Generation and Low Power Control .............................................. 2-5 2.4.1 PLL and Oscillator Changes to IMP ........................................................ 2-5 2 ...
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... IMP Wake-Up from Low Power STOP Modes .......................................2-17 2.4.4.2.4 IMP Wake-Up Control Register (IWUCR) ..............................................2-17 2.4.4.3 Fast Wake-Up ........................................................................................2-18 2.4.4.3.5 Ring Oscillator Control Register (RINGOCR) ........................................2-19 2.4.4.3.6 Ring Oscillator Event Register (RINGOEVR). .......................................2-20 2.5 MC68LC302 Dual Port RAM..................................................................2-20 2.6 Internal Registers map...........................................................................2-23 3.1 System Control ........................................................................................3-1 3.1.1 System Control Register (SCR) ...............................................................3-2 3.1.2 System Status Bits...................................................................................3-3 3.1.3 System Control Bits .................................................................................3-3 3 ...
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... Bus Arbitration Logic ............................................................................. 3-28 3.8.3.1 Internal Bus Arbitration.......................................................................... 3-28 3.8.3.2 External Bus Arbitration......................................................................... 3-28 3.9 Dynamic RAM Refresh Controller ......................................................... 3-29 Communications Processor (CP) 4.1 MC68LC302 Key Differences from the MC68302 ................................... 4-1 4.2 Serial Channels Physical Interface.......................................................... 4-2 4.2.1 Serial Interface Registers ........................................................................ 4-2 4.2.1.1 Serial Interface Mode Register (SIMODE) .............................................. 4-2 4.2.1.2 Serial Interface Mask Register (SIMASK) ............................................... 4-4 4.3 Serial Communication Controllers (SCCs) .............................................. 4-4 4 ...
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... HDLC Mask Register .............................................................................4-21 4.3.11 BISYNC Controller .................................................................................4-22 4.3.11.1 BISYNC Memory Map............................................................................4-22 4.3.11.2 BISYNC Mode Register .........................................................................4-22 4.3.11.3 BISYNC Receive Buffer Descriptor (Rx BD)..........................................4-22 4.3.11.4 BISYNC Transmit Buffer Descriptor (Tx BD). ........................................4-22 4.3.11.5 BISYNC Event Register .........................................................................4-23 4.3.11.6 BISYNC Mask Register..........................................................................4-23 4.3.12 Transparent Controller ...........................................................................4-23 4.3.12.1 Transparent Memory Map......................................................................4-23 4.3.12.2 Transparent Mode Register ...................................................................4-24 viii Title MC68LC302 REFERENCE MANUAL Page Number MOTOROLA ...
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... Address Bus Pins (A19–A1).................................................................... 5-7 5.6 Data Bus Pins (D15—D0) ....................................................................... 5-8 5.7 Bus Control Pins...................................................................................... 5-9 5.8 Bus Arbitration Pins............................................................................... 5-10 5.9 Interrupt Control Pins ............................................................................ 5-11 5.10 MC68LC302 Bus Interface Signal Summary......................................... 5-12 5.11 Physical Layer Serial Interface Pins...................................................... 5-14 5.12 Typical Serial Interface Pin Configurations ........................................... 5-14 5.13 NMSI1 or ISDN Interface Pins............................................................... 5-14 5.14 NMSI2 Port or Port a Pins ..................................................................... 5-17 5.15 PAIO / SCP Pins ...
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... AC Electrical Specifications—PCM Timing............................................6-34 6.22 AC Electrical Specifications—NMSI Timing...........................................6-36 Mechanical Data and Ordering Information 7.1 Pin Assignments ......................................................................................7-1 7.1.1 Pin Grid Array (PGA) ...............................................................................7-1 7.1.2 Surface Mount (TQFP )............................................................................7-2 7.2 Package Dimensions ...............................................................................7-3 7.2.1 Pin Grid Array (PGA) ...............................................................................7-3 7.2.2 Surface Mount (TQFP).............................................................................7-4 7.3 Ordering Information ................................................................................7-5 x Title Section 7 MC68LC302 REFERENCE MANUAL Page Number MOTOROLA ...
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... INTRODUCTION Motorola has developed a low-cost version of the well-known MC68302 integrated multipro- tocol processor (IMP) called the MC68LC302. Simply put, the LC302 is a traditional 68302 minus the third serial communication controller (SCC3) and has a new static 68000 core, a new timer and low power modes packaged in a low profile 100 TQFP that reduces board space from the regular 68302, as well as making it suitable for use in height restricted applications such as PCMCIA ...
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... Main Controller (RISC Processor) Two Independent Full-Duplex Serial Communications Controllers (SCCs) Supporting Various Protocols: High-Level/Synchronous Data Link Control (HDLC/SDLC) Universal Asynchronous Receiver Transmitter (UART) Binary Synchronous Communication (BISYNC) Transparent Modes Autobaud Support Instead of DDCMP and V.110 Boot from SCC Capability 1-2 MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... LC302 DIFFERENCES The LC302 has some specific differences from the 68302. Most of these differences simply result from the reduction in pins from 132 on the original 68302, to 100 pins on the LC302. 1. IOM trademark mens AG MOTOROLA MC68LC302 REFERENCE MANUAL Introduction 1 -2) 1-3 ...
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... The IAC, FRZ, and AVEC pins are provided so that emulation vendors can quickly retrofit their existing 68302 emulator designs to support the LC302. 1-4 † , AVEC NOTE † are available in the PGA Package. MC68LC302 REFERENCE MANUAL † † , RMC, IAC , BERR, BR, † , MOTOROLA ...
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... This section is intended to describe configuration of the MC68LC302 and the differences between theLC302 and the MC68000 and the MC68302.This section also includes tables that show the registers of the IMP portion of the MC68LC302. All of the registers are memory mapped into the 68000 space 2 ...
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... The MC68LC302 in CPU enable mode does not have BR, BG, and BGACK pins. Instead the HALT pin is used to force the MC68LC302 off of the bus (see the HALT signal descrip- tion in 5.4 System Control Pins). While the MC68LC302 is halted, the chip selects are still functional ...
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... This 4K- byte block location is determined by writing the intended base address to the BAR in super- visor data space (FC = 5). The FC2-0 pins are internally driven by the MC68LC302 to super- visor data space. After a total system reset, the on-chip peripheral base address is undefined, and it is not possible to access the on-chip peripherals at any address until BAR is written ...
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... The FC bits in the BAR are ignored. Accesses to the IMP 4K-byte block occur with- out comparing the FC bits The FC bits in the BAR are compared. The address space compare logic uses the FC bits to detect address matches. 2-4 NOTE BASE ADDRESS NOTE MC68LC302 REFERENCE MANUAL MOTOROLA 0 12 ...
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... The MC68LC302 uses one of the IMP 32-bit reserved spaces for 3 registers added for the MC68LC302. These registers are used to con- trol the PLL, clock generation and low power modes. See 2.4 Clock Generation and Low Power Control ...
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... These bits are now in the IMP clock control register (IPLCR) on the MC68LC302, see 2.4.3.4.2 IMP PLL and Clock Control Register (IPLCR). Three-State TCLK1 (TSTCLK1) This bit is now in the DISC register on the MC68LC302, see 4.3.2 Disable SCC1 Serial Clocks Out (DISC). Three-State RCLK1 (TSRCLK1) This bit is now in the DISC register on the MC68LC302, see 4 ...
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... OSC. XTAL PIN Figure 2-2. MC68LC302 PLL Clock Generation Schematic 2.4.2.1 DEFAULT SYSTEM CLOCK GENERATION. During the assertion of hardware reset, the value of the MODCLK and VCCSYN input pins determine the initial PLL settings according to Table 2-2. After the deassertion of reset, these pins are ignored. ...
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... The clock generation features of the IMP are discussed in the following paragraphs. 2.4.3.2 ON-CHIP OSCILLATOR. A 32.768-kHz watch crystal provides an inexpensive ref- erence, but the EXTAL reference crystal frequency can be any frequency from 25 kHz to 6.0 2-8 NOTE CLKIN * MOF is Maximum Operating Frequency MC68LC302 REFERENCE MANUAL PIT CLOCK IMP SYSTEM CLOCK (0 – MOF*) BRG CLOCK ...
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... The low power clock divider bits are located in the IOMCR register. If IMP PLL is enabled, the multiplication value must be large enough to result in the VCO clock being greater than 10 MHz. MOTOROLA VCC ~390pf x MF 0.1 F 0.01 F 20pf VCCSYN XFC CLOCK GENERATION NOTE MC68LC302 REFERENCE MANUAL GNDSYN VCC ICLVCC 0.1 F ICLGND CLKO 2-9 ...
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... IMP PLL and Clock Control Register (IPLCR IPLWP CLKOMOD0–1 RESET MF7 MF6 MF5 RESET VCCSYN/MODCLK1 0 Read/Write 2-10 NOTE 12 11 PEN MF11 0 VCCSYN MF4 MF3 0 VCCSYN/MODCLK 0 MC68LC302 REFERENCE MANUAL $0F8 MF10 MF9 MF8 0 0 VCCSYN/MODCLK MF2 MF1 MF0 0 MODCLK MODCLK MOTOROLA ...
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... PEN—PLL Enable Bit The PEN bit indicates whether the IMP PLL is operating. This bit is written by the MC68LC302 based on the value of VCCSYN during reset. When the IMP PLL is disabled, the VCO is not operating in order to minimize power consumption. During hardware reset this bit is set if the VCCSYN pin specifies that the IMP PLL is enabled. The only way to clear PEN is to hold the VCCSYN pin low during a hardware reset ...
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... After RESET is negated, the MODCLK pins is ignored and becomes PA12. Table 2-2 shows the combinations of VCCSYN and MODCLK pins with the corresponding default settings. 2-12 dedicated to the analog IMP PLL circuits. The volt- CC MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... Configuration, Clocking, Low Power Modes, and Internal Memory Map 2.4.4 IMP Power Management The IMP portion of the MC68LC302 has several low power modes from which to choose. 2.4.4.1 IMP LOW POWER MODES. The MC68LC302 provides a number of low power modes for the IMP section. Each of the operation modes has different current consumption, wake-up time, and functionality characteristics. The state of the IMP’ ...
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... This bit controls whether the divide-by-two block shown in Figure 2-2 is enabled The BRG clock is divided The BRG clock is divided – functionality is lost in SLOW-GO mode DF1 DF0 and 2 . Changing the value of these bits will not MC68LC302 REFERENCE MANUAL $0FA BCD LPM1 LPM0 MOTOROLA ...
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... IMP. This register must be written with the same operand as the STOP instruction that follows. This tells the hard- ware what level of interrupt (and above) will stop the MC68LC302 from entering low power if it occurs while the clocks are being stopped. ...
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... Sample the interrupt mask bits (bits 0–2). If during this process of stopping the clocks 2-16 ;copy STOP operand high byte to addr 000000fb ;xxxx -> supervisor? ; flush execution, bus pipes ;copy STOP operand high byte to addr 000000fb ; xxxx -> error routine? NOTE MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... PB9En is set and PB9Ev is set, the IMP will wake-up from the selected power down state, and a PB9 Interrupt will be generated. The IMP cannot enter the power-down mode if MOTOROLA NOTE PB9Ev MC68LC302 REFERENCE MANUAL $0F7 PITEn PB10En PB9En 2-17 ...
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... If the SCCs use the internal clock they use external clock and the Ringo/external frequency ratio does not comply with the 1 / 2.5 maximum ration specification, then they cannot be en- abled until the real clock has resumed operation. 2-18 NOTE MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... Enable the real clock and switch the system clock from Ringo to the real clock once it is stable 10 = Enable the real clock and generate an interrupt to the CPU after the switch occurs 11 = Reserved MOTOROLA RICR MC68LC302 REFERENCE MANUAL BAR+$81A RECLMODE RINGOEN 2-19 ...
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... When any SCC, SCP, or SMC channel buffer descriptors or parameters are not used, their parameter RAM area can be used for additional memory. For detailed informa- tion about the use of the buffer descriptors and protocol parameters in a specific protocol, see Section 4 Communications Processor (CP). CP. Base + 67E contains the MC68LC302 revision number. 2-20 ...
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... Word SMC1 Word SMC2 Word SMC2 6 Word SMC1–SMC2 Word SCP Word SCC1–SCC3 Word CP MC68PM302 Revision Number MC68LC302 REFERENCE MANUAL Description ...
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... BAR pointer and are located on the internal M68000 bus. All undefined and reserved bits within registers and parameter RAM values written by the user in a given application should be written with zero to allow for future enhancements to the device. 2-22 NOTE MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... Reserved 16 Timer Timer Unit 2 Mode Register 16 Timer Timer Unit 2 Reference Register 16 Timer Timer Unit 2 Capture Register 16 Timer Timer Unit 2 Counter 8 Timer Reserved MC68LC302 REFERENCE MANUAL Description Reset Value 0000 0000 XXXX XXXX XXXX 00 XX 0000 0000 0000 0000 00 00 0000 0000 ...
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... Serial Interface Mask Register 16 SI Serial Interface Mode Register Reserved 8 PIO Pin IO Data Direction Register 8 PIO Pin IO Data Register Reserved 16 SIB Disable SCC1 Serial Clocks Reserved MC68LC302 REFERENCE MANUAL Description Reset Value 00 00 0004 0000 7E7E 0004 0000 7E7E 0000 00 ...
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... SECTION 3 SYSTEM INTEGRATION BLOCK (SIB) The MC68LC302 contains an extensive SIB that simplifies the job of both the hardware and software designer. Most of the features are taken from the MC68302 without change, fea- tures that have been added are highlighted in bold text. This section will only present the register descriptions for each block. For more information on the operation of each block, please refer to the MC68302 Users’ ...
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... Read-Modify-Write Cycle Special Treatment External Master Wait State Address Decode Conflict Enable Bus Clear Mask Freeze Watch Dog Timer Enable Freeze Timer 1 Enable Freeze Timer 2 Enable Synchronous Access Mode Hardware Watchdog Enable Hardware Watchdog Count MC68LC302 REFERENCE MANUAL 25 24 WPV ADC 17 16 ADCE BCLM 9 8 HWDCN2– ...
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... WPV will be set regardless of the value of WPVE. RMCST—RMC Cycle Special Treatment 0 = The locked read-modify-write cycles of the TAS instruction will be identical to the M68000 (AS and CS will be asserted during the entire cycle). The arbiter will issue MOTOROLA NOTE NOTE MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 3-3 ...
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... Asynchronous accesses. All accesses to the IMP internal RAM and registers (in- cluding BAR and SCR external master are asynchronous to the IMP clock. Read and write accesses are with three wait states, and DTACK is asserted by the IMP assuming three wait-state accesses. This is the default value. 3-4 MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... RAM. See Appendix C in MC68302UM/AD. VGE—Vector Generation Enable (Not supported by the MC68LC302) This bit must be written to zero. Since the MC68LC302 cannot decode an interrupt ac- knowledge cycle from an external processor without the FC pins, the user should provide either an autovector signal or a vector back to the host processor during an interrupt ac- knowledge cycle for the MC68LC302 ...
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... Basic Procedure: The MC68LC302 is booted in its 8-bit mode by externally connecting the BUSW pin to GND expected that the MC68LC302 will be executing out of EPROM or flash at this time, and that no external data memory is available in 8-bit mode. The MC68LC302 initializes the BAR register to place the 4K block of dual-port RAM and peripherals in an area that does not overlap the EPROM region ...
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... At this time other desired initialization should be completed on the MC68LC302. No bus masters (IDMA, SDMA, or external) should be enabled. While in 8-bit mode, the MC68LC302 should initialize the external memory registers that control the16-bit external memory space. External memory refresh is not enabled at this time, but all other desired external memory control features should be enabled. Note that the MC68LC302 does not access the external memory itself yet, only the external memory control registers ...
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... RESET and HALT pins being asserted.) The PA7 pin must be pulled high during system reset, if boot mode is not to be enabled. Once the MC68LC302 detects that the PA7 pin is asserted, it internally keeps the HALT signal to the 68K core asserted after system reset is complete ...
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... RAM. Every character that is received is “echoed” back out of the TXD1 pin. The MC68LC302 UART must be sent 576 bytes of data from the external UART since the LC302 will not leave the boot mode until 576 bytes are received. If the boot program is less than 576 bytes, the user is suggested to write $00 into the remaining locations ...
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... The DREQ, DACK, and DONE pins have been removed. The user must not program the IDMA for external request generation. The External Bus Exceptions, BERR and Retry, have been removed. Only HALT or an in- ternal BERR generated by the Hardware Watchdog Timer is supported. 3-10 NOTE NOTE MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... Internal request at limited rate (limited burst bandwidth) set by burst transfer (BT) bits 01 = Internal request at maximum rate (one burst External request burst transfer mode (DREQ level sensitive External request cycle steal (DREQ edge sensitive) MOTOROLA SAPI DAPI SSIZE MC68LC302 REFERENCE MANUAL System Integration Block (SIB DSIZE BT RST STR 3-11 0 ...
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... Stop channel; clearing this bit will cause the IDMA to stop transferring data at the end of the current operand transfer. The IDMA internal state is not altered Start channel; setting this bit will allow the IDMA to start (or continue if previously stopped) transferring data. STR is cleared automatically when the transfer is complete. 3-12 NOTE NOTE MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... INTE and INTN bits in the CMR). 7 Bits 7–4—These bits are reserved for future use. MOTOROLA SOURCE ADDRESS POINTER DESTINATION ADDRESS POINTER DFC 1 NOTE RESERVED DNS BES MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 0 SFC 1 0 BED DONE 0 0 3-13 ...
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... In Disable CPU mode, the IRQ1, IRQ6, and IRQ7 become the BR, BGACK, and BG signals. With the core disabled, the MC68LC302 will not be able to decode an external CPU’s inter- rupt acknowledge cycle. The user must poll the Interrupt Pending Register (IPR) during in- terrupt handling to determine which peripheral caused the interrupt ...
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... Bits 11 and 4–0—Reserved for future use. 3.5.2.2 Interrupt Pending Register (IPR) Each bit in the 16-bit IPR corresponds to an INRQ interrupt source. When an INRQ interrupt is received, the interrupt controller sets the corresponding bit in the IPR. MOTOROLA NOTE NOTE: MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 3-15 ...
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... The user's interrupt service routine should clear this bit during the servicing of the interrupt. 3-16 NOTE 12 11 SDMA IDMA TIMER3 SMC1 SDMA IDMA TIMER3 SMC1 MC68LC302 REFERENCE MANUAL SCC2 TIMER1 — SMC2 PB8 ERR SCC2 TIMER1 — ...
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... The SCP pins are now multiplexed onto PA8, PA9, and PA10. The MODCLK pin is multiplexed with the PA12 port pin. After reset, this pin becomes a gen- eral purpose I/O pin. An 8-bit port, Port N, has been added. Port N is only available when the MC68LC302 is in 8-bit mode (internal BUSW=0). 3.6.2 Port A Each of the port A pins are independently configured as a general-purpose I/O pin if the cor- responding port A control register (PACNT) bit is cleared ...
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... PA6 PA7 PA8 PA9 PA10 PA12 Table 3-3. Port B Pin Functions PBCNT Bit = 0 Input to Interrupt Pin Function Control and Timers PB3 PB5 PB6 PB7 MC68LC302 REFERENCE MANUAL Input to GND — GND RCLK2 # GND — GND — GND — GND — GND GND — ...
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... MC68LC302 REFERENCE MANUAL System Integration Block (SIB ...
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... MC68LC302 General Purpose Timer Difference The only difference between the MC68LC302 and the MC68302 general purpose timers is that Timer 1 output signal is not connected to the externally. 3.7.2 General Purpose Timers Programming Mode 3 ...
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... Each TER is an 8-bit register used to report events recognized by any of the timers. On rec- ognition of an event, the timer will set the appropriate bit in the TER, regardless of the cor- responding interrupt enable bits (ORI and CE) in the TMR. TER1 and TER2, which appear MOTOROLA MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 3-21 ...
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... Periodic Interrupt Timer (PIT) The MC68LC302 IMP provides a timer to generate periodic interrupts for use with a real- time operating system or the application software. The periodic interrupt time period can vary from 122 s to 128 s (assuming a 32.768-kHz crystal is used to generate the general system clock) ...
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... This gives a range from 122 s, with a PITR value of $0, to 250 ms, with a PITR value of $7FF (assuming 32.768 khz at the EXTAL pin. MOTOROLA NOTE PITR count value+1 = ------------------------------------------------------ - EXTAL ------------------------------------------------------ - PITR count value+1 = ------------------------------------------------ - 32768 1 --------------------- - PITR count value = ------------------------------------------ - MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 1or512 8192 3-23 ...
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... PITR6 PITR5 PITR4 RESET 0 0 Read/Write 3-24 PITR count value = ------------------------------------------ - 32768 512 --------------------------- - PITR count value = ------------------------------------------ - PTP PITR10 PITR3 PITR2 MC68LC302 REFERENCE MANUAL $0F0 PITR9 PITR8 PITR7 PITR1 PITR0 RES MOTOROLA ...
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... FC2-FC0 internally. The CS logic compares the signals to the values programmed in the registers. In Disable CPU mode or for External Bus Masters, the A23-A20 signals are internally driven to zero, so the user must program MOTOROLA NOTE NOTE NOTE MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 3-25 ...
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... Option Registers (OR3–OR0) These four 16-bit registers consist of a base address mask field, a read/write mask bit, a compare function code bit, and a DTACK generation field DTACK 3-26 BASE ADDRESS (A23–A13) BASE ADDRESS MASK (M23–M13) MC68LC302 REFERENCE MANUAL MRW ...
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... CFC should be programmed to 0. MOTOROLA Bits Description Wait State Wait State Wait States Wait States Wait States Wait States Wait States 1 1 External DTACK NOTE NOTE MC68LC302 REFERENCE MANUAL System Integration Block (SIB) 3-27 ...
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... The IPL1 pin becomes BGACK and is an output from the IDMA and SDMA to indicate bus ownership. 4. The IPL2-0 lines are no longer encoded interrupt lines.The interrupt controller will out- put the MC68LC302’s interrupt request on IOUT2. CS0, which is multiplexed with IOUT2 is not available in this mode. 5. The WEH and WEL signals become UDS and LDS respectively. ...
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... Also, the external master cannot access the internal address space of the MC68LC302. Bus Arbitration is not supported when the MC68LC302 is in one of the low power modes. The chip does not release the address and data lines. 3.9 DYNAMIC RAM REFRESH CONTROLLER The communications processor (CP) main (RISC) controller may be configured to handle the dynamic RAM (DRAM) refresh task without any intervention from the M68000 core ...
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... System Integration Block (SIB) 3-30 MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... Serial Communication Port (SCP) for Synchronous Communication • Two Serial Management Controllers (SMCs) to Support the IDL and GCI Management Channels 4.1 MC68LC302 KEY DIFFERENCES FROM THE MC68302 • SCC3 Was Removed. • The SCP Is Now Multiplexed with the PA8, PA9, and PA10 Pins. ...
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... The SCIT (Special Circuit Interface T) interface mode is valid only in GCI mode SCIT support disabled 1 = SCIT D-channel collision enabled. Bit 4 of channel 2 C/I used by the IMP for receiv- ing indication on the availability of the S interface D channel. 4 SDIAG0 SDC2 DRA MSC3 MC68LC302 REFERENCE MANUAL SDC1 B2RB B2RA MSC2 MS1 MS0 MOTOROLA ...
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... B2RB, B2RA—B2 Channel Route in IDL/GCI Mode or CH-3 Route in PCM Mode 00 = Channel not supported 01 = Route channel to SCC1 10 = Route channel to SCC2 (if MSC2 is cleared Route channel to SCC3 (Not Supported in the MCMC68LC302) B1RB, B1RA—B1 Channel Route in IDL/GCI Mode or CH-2 Route in PCM Mode 00 = Channel not supported 01 = Route channel to SCC1 ...
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... TIN1 pin, and (2) options for three stating theTCLK1, and RCLK1 pins. 4 NOTE CD9 CD8 CD7 CD6 CD5 MC68LC302 REFERENCE MANUAL CD4 CD3 CD2 CD1 CD0 MOTOROLA 0 0 DIV4 ...
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... FIFO is lost. If ENR is cleared during data reception, the receiver aborts the current character. ENR may be set or cleared regardless of whether serial MOTOROLA 12 11 BRGDIV DIAG1 MC68LC302 REFERENCE MANUAL Communications Processor (CP) Base+$8EE ...
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... OFFSET + 6 Figure 4-1. SCC Buffer Descriptor Format Even though the address bus is only 20 bits, the full 32-bit point- er must be Bits 24-32 must be zero, and bits 20-23 are used in 4 STATUS AND CONTROL DATA LENGTH LOW-ORDER DATA BUFFER POINTER NOTE MC68LC302 REFERENCE MANUAL 0 SYN1 0 MOTOROLA ...
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... Rx Internal Data Pointer Word Rx Internal Byte Count Word Rx Temp Word Tx Internal State Byte Reserved TBD# Byte Tx Internal Buffer Number 2 Words Tx Internal Data Pointer Word Tx Internal Byte Count Word Tx Temp First Word of Protocol-Specific Area Last Word of Protocol-Specific Area MC68LC302 REFERENCE MANUAL Communications Processor (CP) Description 4-7 ...
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... DATA LENGTH RX BUFFER POINTER (24-bits used, upper 8 bits must — — DATA LENGTH TX BUFFER POINTER (24-bits used, upper 8 bits must be 0) MC68LC302 REFERENCE MANUAL Description 5 COMMON SCC MODE BITS — — ...
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... SCC FIFOs. 4.3.9.1 AUTOBAUD CHANNEL RECEPTION PROCESS. The interface between the auto- baud controller and the host processor is implemented with shared data structures in the MOTOROLA IDL BRK CCR BSY MC68LC302 REFERENCE MANUAL Communications Processor (CP 4-9 ...
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... UART mode. The autobaud controller returns the nominal START bit length value for the detected baud rate from the lookup table and a pointer to the last character received that was written to the external data buffer. The host must be able to handle each character inter- 4-10 MC68LC302 REFERENCE MANUAL MOTOROLA ...
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... ENT), and programs the transmit character descriptor (overlays CON- TROL Character 8). The host is interrupted after each character is transmitted. For modem applications with the MC68LC302, SCC2 will be used as the DTE interface and autobauding to the DTE baud rate will often be required. If use of the smart echo feature is desired, the receive clock can be provided by the baud rate generator 2 (BRG2) internally by resetting the RCS bit in the SCON2 register to zero ...
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... User Defined Character2 Word Receive Control Character Register Word CONTROL Character1 Word CONTROL Character2 Word CONTROL Character3 Word CONTROL Character4 Word CONTROL Character5 Word CONTRChar6/MSW of pointer to external Rx Buffer Word CONTRChar7/LSW of pointer to external Rx Buffer Word CONTROL Character8/Transmit BD NOTE MC68LC302 REFERENCE MANUAL Description MOTOROLA ...
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... Write the DSR of the SCC with the value $7FFF in order to detect the START bit. 6. The host initiates the autobaud search process by issuing the Enter_Baud_Hunt com- mand 7. Write the SCM of the SCC with $1133 to configure it for BISYNC mode, with the REVD MOTOROLA NOTE MC68LC302 REFERENCE MANUAL Communications Processor (CP) 4-13 ...
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... STOP bit is detected in the received data. FE will be set for a 9-bit character (8 bits + parity) if the parity bit is ‘0’. The user must clear this bit when it is set. 4- Lookup Table Size Lookup Table Pointer NOTE MC68LC302 REFERENCE MANUAL EOT OV CD MOTOROLA ...
Page 82
... To do this EQ 1 must be used until satisfied. The sampling rate is the lowest speed baud rate that can be generated by the SCC baud rate generator that is over a thresh- old defined BRG Clk Rate = System Clock or TIN1 / ((Clock Divider bits in SCON MOTOROLA NOTE NOTE NOTE NOTE MC68LC302 REFERENCE MANUAL Communications Processor (CP) (EQ 1) 4-15 ...
Page 83
... Description 0 Maximum Start Length 2 Nominal Start Length 4 Maximum Start Length 6 Nominal Start Length • Maximum Start Length • Nominal Start Length Maximum Start Length Nominal Start Length NOTE MC68LC302 REFERENCE MANUAL (EQ 2) (EQ 3) (EQ 4) MOTOROLA ...
Page 84
... Even parity Odd parity Parity is indicated by the most signif- icant bit of the byte Parity=1 Parity=0 No parity Same as 7-bit, parity=0 Even parity Parity is indicated by which charac- Odd parity ters generate a FE interrupt Parity=0 Parity=1 Not Supported MC68LC302 REFERENCE MANUAL Communications Processor (CP) Notes 4-17 ...
Page 85
... M68000 should clear the status bits and issue the Enter_Baud_Hunt command again. 4.3.9.8 AUTOBAUD TRANSMISSION. The autobaud package supports two methods for echoing characters or transmitting characters. The two methods are automatic echo and smart echo. 4-18 MC68LC302 REFERENCE MANUAL autobaud MOTOROLA ...
Page 86
... Table 4-8. Transmit Character BD R (ready bit Character is not ready 1 = Character is ready to transmit CL (character len bits + parity or 8 bits with no parity bits + parity PE (parity enable parity 1 = Parity MOTOROLA MC68LC302 REFERENCE MANUAL Communications Processor (CP CHAR 4-19 ...
Page 87
... Nonmatching Address Received Counter Word Frame Retransmission Counter Word Max Frame Length Register Word Max_Length Counter Word User-Defined Frame Address Mask Word User-Defined Frame Address Word User-Defined Frame Address Word User-Defined Frame Address Word User-Defined Frame Address MC68LC302 REFERENCE MANUAL Description MOTOROLA ...
Page 88
... L TC — — — DATA LENGTH TX BUFFER POINTER (24-bits used, upper 8 bits must IDL TXE RXF BSY MC68LC302 REFERENCE MANUAL Communications Processor (CP) 5 COMMON SCC MODE BITS — — ...
Page 89
... BCS — RTR RBCS SYNF — — — — DATA LENGTH RX BUFFER POINTER (24-bits used, upper 8 bits must be 0) MC68LC302 REFERENCE MANUAL Description ENC COMMON SCC MODE BITS — MOTOROLA ...
Page 90
... RAM areas and Table 4-1 for the other parameter RAM values. MOTOROLA DATA LENGTH TX BUFFER POINTER (24-bits used, upper 8 bits must — TXE RCH BSY MC68LC302 REFERENCE MANUAL Communications Processor (CP — — — — 4-23 ...
Page 91
... DATA LENGTH RX BUFFER POINTER (24-bits used, upper 8 bits must be 0) MC68LC302 REFERENCE MANUAL Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
Page 92
... DATA LENGTH TX BUFFER POINTER (24-bits used, upper 8 bits must — TXE RCH BSY ?LOOP CI PM3 PM2 PM1 MC68LC302 REFERENCE MANUAL Communications Processor (CP — — — — — PM0 ...
Page 93
... 4.5.2.2 SMC1 TRANSMIT BUFFER DESCRIPTOR. The CP reports information about this transmit byte through the BD. 4- SMD3 SMD2 SMD1 SMD0 LOOP — MC68LC302 REFERENCE MANUAL DATA 1 0 EN2 EN1 DATA MOTOROLA 0 0 ...
Page 94
... SMC2 TRANSMIT BUFFER DESCRIPTOR. In the IDL mode, this BD is identical to the SMC1 transmit BD. In the GCI mode, SMC2 is used to control the C/I channel RESERVED MOTOROLA — MC68LC302 REFERENCE MANUAL Communications Processor (CP) DATA C C ...
Page 95
... Communications Processor (CP) 4-28 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 96
... This section defines the MC68LC302 pinout. The input and output signals of the MC68LC302 are organized into functional groups and are described in the following sec- tions. The MC68LC302 is offered in a 100-lead thin quad flat package (TQFP) and a 132- pin (13 x 13) pin grid array (PGA) for emulator applications. ...
Page 97
... The LC302 (TQFP) has 17 power supply pins. Careful attention has been paid to reducing LC302 noise, potential crosstalk, and RF radiation from the output drivers. Inputs may when without damaging the device. DD • V (6)—There are 6 power pins. DD • GND (11)—There are 11 ground pins. 5-2 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 98
... PB11 FC2-0 FRZ IAC Note: Pins in parenthesis () are available in slave mode only. Figure 5-1. LC 302 Functional Signal Groups MOTOROLA LC302 Signals Pins available in PGA Package MC68LC302 REFERENCE MANUAL Signal Description Address Bus A1-A19 Chip Select CS0/IOUT2 CS3-CS1 Data Bus/Port N D0-D7 D15-D8/PN15-8 Bus Control ...
Page 99
... In this manual, many references to the frequency “16.67 MHz” are made when the maximum operating frequency of the MC68LC302 is discussed. When using faster versions of the MC68LC302, such as 20 MHz, all references to 16.67 MHz may be re- placed with 20. Note, however, that resulting parameters such as baud rates and timer periods change accordingly. XTAL— ...
Page 100
... SYSTEM CONTROL PINS The system control pins are shown in Figure 5-3. MOTOROLA Multi. Factor EXTAL Freq. CLKIN to the (MF+1) (examples =EXTAL 4 4.192MHz 4.192MHz 401 32.768KHz 32.768KHz MC68LC302 REFERENCE MANUAL Signal Description LC302 System PLL Clock =EXTAL 16.768 MHz 13.14 MHz power rail CCSYN 5-5 ...
Page 101
... When this bidirectional, open-drain signal is driven by an external device, it will cause the LC302 bus master (M68000 core, SDMA, or IDMA) to stop at the completion of the current bus cycle. This signal is asserted with the RESET signal to cause a total MC68LC302 sys- tem reset. This signal is also used to force the LC302 off the bus if another bus master ...
Page 102
... High = 16-bit data bus, MC68000 core processor DISCPU—Disable CPU (M68000 core) The MC68LC302 can be configured to work solely with an external CPU. In this mode the on-chip M68000 core CPU should be disabled by asserting the DISCPU pin high during a total system reset (RESET and HALT asserted). DISCPU may only be changed upon a total system reset ...
Page 103
... M bytes. 5.6 DATA BUS PINS (D15—D0) The data bus pins are shown in Figure 5-5. When the MC68LC302 is in 8-bit data bus mode, D15-D8 become general purpose I/O pins, PN15-PN8. This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transmit and accept data in either word or byte lengths. For all 16-bit LC302 accesses, byte 0, the high-order byte of a word, is available on D15– ...
Page 104
... This line is an output when the LC302 is the bus master and is an input otherwise. MOTOROLA AS OE (R/W) WEH/A0 (UDS/A0) WEL/WE (LDS/DS) DTACK IAC* * This pin is available in PGA Package only Figure 5-6. Bus Control Pins MC68LC302 REFERENCE MANUAL Signal Description 5-9 ...
Page 105
... CPU mode. When the core is enabled, the bus arbitration signals are the IPL2-0 signals. BR—Bus Request This input signal indicates to the on-chip bus arbiter that an external device desires to be- come the bus master. 5-10 BR BGACK BG Figure 5-7. Bus Arbitration Pins MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 106
... The least significant bit is IPL0, and the most significant bit is IPL2. These lines must remain stable until the M68000 core MOTOROLA NOTE IPL0/IRQ1 IPL1/IRQ6 IPL2/IRQ7 FC0* FC1* FC2* AVEC* * Those pins are available in PGA Package only MC68LC302 REFERENCE MANUAL Signal Description 5-11 ...
Page 107
... A19–A16 to ensure that the interrupt is properly recognized. As IRQ1, IRQ6, and IRQ7 (dedicated mode), these inputs indicate to the MC68LC302 that an external device is requesting an interrupt. Level 7 is the highest level and cannot be masked. Level 1 is the lowest level. Each one of these inputs (except for level 7) can be programmed to be either level-sensitive or edge-sensitive ...
Page 108
... NA I/O NA I/O I IDMA Master Access To Pin Type Internal Memory Space I/O O I/O O I/O O I/O O I I/O O MC68LC302 REFERENCE MANUAL Signal Description External Master 1 Access To Internal External Memory Memory Memory Space Space Space N/A N/A NA N/A N/A NA ...
Page 109
... SCP Controller PIO—Port A Connected To SCC1 Used as ISDN D-ch SCC1 and SCC2 SCC2 Used as ISDN B-ch PA12–PA8 PIO or SCP Status/Control Exchange Connected To SCC1 Terminal with Modem SCC2 Terminal with Modem SCP Status/Control Exchange MC68LC302 REFERENCE MANUAL Connected To SCC1/SCC2 Parallel I/O Parallel I/O Used As Used As MOTOROLA ...
Page 110
... RTS1 / L1RQ / GCIDCL Table 5-8. Mode Pin Functions GCI I L1RXD I O L1TXD O I L1CLK I O SDS1 O I L1SYNC I I L1GR I O GCIDCL O MC68LC302 REFERENCE MANUAL Signal Description IDL PCM L1RXD I L1RXD L1TXD O L1TXD L1CLK I L1CLK SDS1 I L1SY0 L1SYNC I L1SY1 L1GR L1RQ O RTS 5-15 ...
Page 111
... CD1 automatically (in the SCC1 mode register), then this pin may be used as an ex- ternal interrupt source. The current value of CD1 may be read in the SCCS1 register. See 5-16 NOTE Table 5-9. PCM Mode Signals L1SY0 Data (L1RXD, L1TXD) is Routed to SCC 0 L1TXD is Three-Stated, L1RXD is Ignored 1 CH-1 0 CH-2 1 CH-3 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 112
... The PA7 signal in dedicated mode becomes serial data strobe 2 (SDS2) in IDL and GCI modes. In IDL/GCI modes, the SDS2–SDS1 outputs may be used to route the B1 and/or B2 channels to devices that do not support the IDL or GCI buses. This is configured in the SI- MOTOROLA RXD2/PA0 TXD2/PA1 RCLK2/PA2 TCLK2/PA3 CTS2/PA4 RTS2/PA5 CD2/PA6 BRG2/SDG2/PA7 MC68LC302 REFERENCE MANUAL Signal Description . DD 5-17 ...
Page 113
... RESET and HALT. The user can pull it HIGH or LOW with an external resistor. If Boot mode is not en- abled PA5 is not sampled at initialization. 5.15 PAIO / SCP PINS The NMSI3 port or port A pins or SCP pins are shown in Figure 5-11. 5-18 NMSI GCI IDL BRG2 TCLK2 TCLK2 NOTE MC68LC302 REFERENCE MANUAL PCM TCLK2 MOTOROLA ...
Page 114
... After Total System Reset this pin functions as bit 12 of port A. 5.16 TIMER PINS The timer pins are shown in Figure 5-12. 5-19 SPRXD / PA8 SPTXD / PA9 SPCLK / PA10 PA12 Figure 5-11. PAIO / SCP Pins TIN1 / PB3 TIN2 / PB5 TOUT2 / PB6 WDOG / PB7 Figure 5-12. Timer Pins MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 115
... This active-low, open-drain output indicates expiration of the watchdog timer. WDOG is asserted for a period of 16 clock (CLKO) cycles and may be externally connected to the RESET and HALT pins to reset the MC68LC302. The WDOG pin function is enabled after a total system reset. It may be reassigned as the PB7 I/O pin in the PBCNT register. ...
Page 116
... CC unconnected. Unused I/O pins may be configured as outputs after reset and left unconnect- ed. If the MC68LC302 held in reset for extended periods of time in an application (other than what occurs in normal power-on reset or board test sequences) due to a special appli- cation requirement (such as V stated signals and inputs should be pulled up or down. This decreases stress on the device transistors and saves power ...
Page 117
... Signal Description 5-22 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 118
... LDS, R/W, BR, BG, BGACK are available only in Slave Mode. The following diagrams and tables show the timing for all avail- able signals. For complete information on which signals are available in which modes (CPU disable), please refer to Section 5 of this Addendum. MOTOROLA MC68LC302 REFERENCE MANUAL input setup and hold times , and , 6-1 ...
Page 119
... TBD JA TBD JC is: J MC68LC302 REFERENCE MANUAL This device contains circuitry to Unit protect the inputs against damage due to high static voltages or elec- V tric fields; however advised that normal precautions be taken V to avoid application of any voltage higher than maximum-rated volt- ages to his high-impedance circuit ...
Page 120
... T J MOTOROLA can be obtained from )(1) • Junction to Ambient , I/O Watts—Chip Internal Power , P and can be neglected. • INT + 273 C)(2) 2 (3) + 273 C) + • MC68LC302 REFERENCE MANUAL Electrical Characteristics C/W , and the values 6-3 ...
Page 121
... Norlmal Mode at 16Mhz Low Power Standby Mode Lo Power Doze Mode Low Power Stop Mode Note: These values are preliminary estimates. Test values are TBD. 6-4 Symbol 5v Typ PD(I) 70 PD(I) 60 PDSB(I) 7 PDDZ(I) 500 PDDZ(I) 100 MC68LC302 REFERENCE MANUAL 5v Max Unit TBD mA TBD mA TBD mA TBD A TBD A MOTOROLA ...
Page 122
... I OH mA, the minimum V is calculated as MOTOROLA Symbol 3.3 Volt or 5 Volt Part 5.0 Volt Part 3.3 Volt Part rating for that pin. For +.05 V/mA(I -.400 mA)). DD OH MC68LC302 REFERENCE MANUAL Electrical Characteristics Min Max Unit ...
Page 123
... CLK TBD TBD t 60 cyc dcyc t 60 EXTcyc t TBD Crf EXTP MC68LC302 REFERENCE MANUAL Unit Condition (% 10 5 400 MHz 25 MHz Min ...
Page 124
... MF < 5 and 540pF for MF> 5. The maximum VCO frequency XFC c 480 pF XFC is: 401 x 970 = 390 nF. The recommended XFC is: 401 x 970 = 390 nF XFC is 390 nF. XFC is: 401 x 970 = 390 nF XFC MC68LC302 REFERENCE MANUAL Electrical Characteristics Min Max Unit 10 f (Note 1.) MHz MF * 340 MF * 480 380 MF * 970 is 390 nF ...
Page 125
... DICL t 0 SHDAH t 0 SHDII t — DALDI — RHr RHf t 0 SHVPH t 10 ASI t 0 CHDOI t 0 RLDBD MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz @5.0 V @5.0 V Unit Max Min Max Min Max — 50 — — 0 — 0 — ns ...
Page 126
... The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 6. When AS and R/W are equally loaded ( 20%), subtract 5 ns from the values given in these columns. MOTOROLA t 10 HRPW t — CHBCH MC68LC302 REFERENCE MANUAL Electrical Characteristics — 10 — 10 — clks 30 — ...
Page 127
... The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 volts and 2.0 volts. Figure 6-2. Read Cycle Timing Diagram 6- 150 175 152 173 18 17 176 MC68LC302 REFERENCE MANUAL 151 28 171 29 178 MOTOROLA ...
Page 128
... Each wait state is a full clock cycle inserted between S4 and S5. Figure 6-3. Write Cycle Timing Diagram MOTOROLA 14A 150 150 152 175 173 20A 177 18 20 176 MC68LC302 REFERENCE MANUAL Electrical Characteristics 151 28 53 172 25 6-11 ...
Page 129
... AS (NOTE 3) (OUTPUT) UDS–LDS (OUTPUT) 18 R/W (OUTPUT) DTACK D15–D0 Figure 6-4. Read-Modify-Write Cycle Timing Diagram 6- S10 S11 S12 DATA IN INDIVISIBLE CYCLE MC68LC302 REFERENCE MANUAL S13 S14 S15 S16 S17 S18 S19 DATA OUT MOTOROLA ...
Page 130
... CHBRZ t 30 BKLBRZ t — CHBKL t 1.5 ABHBKL t 1.5 BGLBKL t 0 BRHBGH t 2 CLBKLAL t — CHBKH t — CLBKZ MC68LC302 REFERENCE MANUAL Electrical Characteristics (see Figure 6-5 and Figure 6-6) 20 MHz 25 MHz Unit Max Min Max Min Max 30 — 25 — — 25 — — 25 — ...
Page 131
... Electrical Characteristics Figure 6-5. DMA Timing Diagram (IDMA) 6-14 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 132
... Figure 6-6. DMA Timing Diagram (SDMA) MOTOROLA MC68LC302 REFERENCE MANUAL Electrical Characteristics 6-15 ...
Page 133
... DSLDIV t 0 DKLDH t 0 ASVDSL t 0 DKLDSH t — DSHDKH t 0 DSIASI t 0 DSHRWH t — DSHDZ t 0 DSHDH t 15 DOVDKL MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz Unit Max Min Max Min Max — 0 — 0 — — 25 — — 0 — 0 — ns — ...
Page 134
... Figure 6-7. External Master Internal Asynchronous Read Cycle Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL Electrical Characteristics 6-17 ...
Page 135
... Electrical Characteristics Figure 6-8. External Master Internal Asynchronous Write Cycle Timing Diagram 6-18 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 136
... CLDTL t — ASHDTH t — DTHDTZ t — CHDOV t — ASHDZ t 0 ASHDOI t 0 ASHAI CLDIV t 15 CLDIH MC68LC302 REFERENCE MANUAL Electrical Characteristics 20 MHz 25 MHz Unit Max Min Max Min Max — 12 — 10 — ns — 25 — 20 — — 40 — — ...
Page 137
... UDS LDS (INPUT) 129 R/W (INPUT) D15–D0 (OUTPUT) DTACK (OUTPUT) Figure 6-9. External Master Internal Synchronous Read Cycle Timing Diagram 6- 110 111 119 115 125 121 MC68LC302 REFERENCE MANUAL 128 112 120 116 126 127 124 123 MOTOROLA ...
Page 138
... D15–D0 (OUTPUT) DTACK (OUTPUT) Figure 6-10. External Master Internal Synchronous Read Cycle Timing Diagram MOTOROLA 110 111 119 115 125 122 (One Wait State) MC68LC302 REFERENCE MANUAL Electrical Characteristics 128 112 120 116 126 127 124 123 6-21 ...
Page 139
... UDS LDS (INPUT) R/W (INPUT) D0–D15 (INPUT) DTACK (OUTPUT) Figure 6-11. External Master Internal Synchronous Write Cycle Timing Diagram 6- 110 111 119 115 129 117 130 121 MC68LC302 REFERENCE MANUAL 112 113 120 116 118 131 124 123 MOTOROLA ...
Page 140
... Min t — CHIAH t — CLIAL t — CHDTL t — CLDTH t — CHDOV t 0 ASHDOH 140 144 142 MC68LC302 REFERENCE MANUAL Electrical Characteristics 20 MHz 25 MHz Unit Max Min Max Min Max 40 — 35 — — 35 — — 40 — — ...
Page 141
... AFVCSA t 15 CSNAFI t 120 CSLT t 10 CSNRWI t — CSARWL t 0 CSNDII 152 151 155 158 MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz Unit Max Min Max Min Max — 50 — 40 — — ...
Page 142
... ASLCSL t — ASHCSH t 15 AVASL t 0 ASHAI t — ASLDTKL t — ASHDTKH 162 160 150 163 165 168 MC68LC302 REFERENCE MANUAL Electrical Characteristics 20 MHz 25 MHz Unit Max Min Max Min Max 30 — 25 — — 25 — — 25 — — ...
Page 143
... DSU — CHDOV 180 181 182 CPU WRITE (S6) OF PORT DATA, CONTROL, OR DIRECTION REGISTER 16.67 MHz Symbol Min t 50 IPW t 3 AEMT MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz Unit Max Min Max Min Max — 20 — 14 — — 10 — 19 — 35 — ...
Page 144
... IRQ (INPUT) Figure 6-16. Interrupts Timing Diagram MOTOROLA 190 191 MC68LC302 REFERENCE MANUAL Electrical Characteristics 6-27 ...
Page 145
... Max t 50 TPW t 50 TICLT t 2 TICHT t 3 cyc t — CHTOV t 20 FRZSU t 10 FRZHT 204 201 200 202 203 MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz Unit Min Max Min Max — 42 — 34 — ns — 42 — 34 — ns — 2 — 2 — clk — ...
Page 146
... Figure 6-18. Serial Communication Port Timing Diagram MOTOROLA (see Figure 6-18). 16.67 MHz Min Max — 10 — 251 252 253 MC68LC302 REFERENCE MANUAL Electrical Characteristics 20 MHz 25 MHz Unit Min Max Min Max clks — 24 — ...
Page 147
... V DD MC68LC302 REFERENCE MANUAL (All timing measurements ) 20 MHz 25 MHz Unit Min Max Min Max — 8 — 10 MHz 45 — 37 — ns P+10 — P+10 — ns — 17 — 14 ...
Page 148
... MOTOROLA Figure 6-19. IDL Timing Diagram MC68LC302 REFERENCE MANUAL Electrical Characteristics 6-31 ...
Page 149
... Normal SCIT Mode 192 — MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz Unit Min Max Min Max — 512 — 512 kHz ns 840 1450 840 1450 ns — — — — ns — 6.668 — ...
Page 150
... Figure 6-20. GCI Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL Electrical Characteristics 6-33 ...
Page 151
... Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate ns. 6-34 16.67 MHz Min Max — 6.66 55 — P+10 — P+10 0 — 40 — 1 — 8 — — 50 — MC68LC302 REFERENCE MANUAL N > 0; see Figure 6- MHz 25 MHz Unit Min Max Min Max — 8.0 — 10.0 MHz 45 — 37 — ns — P+10 — — 0 — ...
Page 152
... NOTE: (*) If L1SYn is guaranteed to make a smooth low to high transition (no spikes) while the clock is high, setup time can be defined as shown (min 20 ns). Figure 6-22. PCM Timing Diagram (SYNC Prior to 8-Bit Data) MOTOROLA 304 305 309 MC68LC302 REFERENCE MANUAL Electrical Characteristics n-1 n 303 302 307 n n 307 6-35 ...
Page 153
... MC68LC302 REFERENCE MANUAL 20 MHz 25 MHz 25 MHz External Internal External Clock Clock Clock — 8 — 8.33 — 10 P+10 — 45 — P+10 — 45 — 45 — 35 — — — — 14 — ...
Page 154
... Figure 6-23. NMSI Timing Diagram MOTOROLA MC68LC302 REFERENCE MANUAL Electrical Characteristics 6-37 ...
Page 155
... Electrical Characteristics 6-38 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 156
... VCCA1 VCCA1 E A9 A12 A13 D A10 A14 A18 C A11 A19 GNDQ3 B A15 D13 D12 MOTOROLA MC68LC302 USER’S MANUAL SUPPLEMENT GNDQ1 GNDP2 WEL VCCQ1 IPL0 EXTAL TN2 WEH OE VCCQ1 IPL1 XTAL VCCP1 IPL2 NC TOUT2 AS GNDQ1 PB10 GNDP NC NC MC68LC302RC ...
Page 157
... VCCP1 (UDS)WEH (LDS)WEL GNDP2 AS (R/W)OE VCCQ1 GNDQ1 (BR) IPL0 (BGACK)IPL1 (BG) IPL2 EXTAL XTAL CLK0 DISCPU BUSW GNDSYN XFC 25 VCCSYN 26 7-2 MC68LC302 USER’S MANUAL SUPPLEMENT MC68LC302PU Top View 76 A16 75 A17 A18 A19 D15 D14 D13 D12 GNDD1 D11 D10 D9 D8 VCCQ2 GNDQ2 VCCD1 D7 D6 ...
Page 158
... C 2.54 3.81 0.100 0.150 D 0.43 0.55 0.017 0.022 G 2.54 BSC 0.100 BSC K 4.32 4.95 0.170 0.195 MOTOROLA MC68LC302 USER’S MANUAL SUPPLEMENT Mechanical Data and Ordering Information NOTES AND B ARE DATUMS AND DATUM SURFACE. 2. POSITIONAL TOLERANCE FOR LEADS (132 PL). ...
Page 159
... VIEW –H– –T– SEATING PLANE 0.05 (0.002 VIEW AA 7-4 MC68LC302 USER’S MANUAL SUPPLEMENT N 0.20 (0.008 TIPS 76 75 –M– –N– 0.08 (0.003 VIEW AA R1 2XR 0.25 (0.010) ...
Page 160
... ORDERING INFORMATION Package Type Pin Grid Array (RC Suffix) Surface Mount (PU Suffix) MOTOROLA MC68LC302 USER’S MANUAL SUPPLEMENT Mechanical Data and Ordering Information Frequency Temperature (MHz) 16. 16. 16. ...
Page 161
... Mechanical Data and Ordering Information 7-6 MC68LC302 USER’S MANUAL SUPPLEMENT MOTOROLA ...
Page 162
... BRG Clock 2-12 BRG Divide by two System Clock 2-14 BSR 3-6 Buffer Buffer Descriptor 4-6 Descriptors 2-20, 3-29 Buffer Descriptor 4-6 Buffer Descriptors Table 4-6 Bus Arbitration 3-28, 5-11 Bandwidth 3-12 Error 2-4 Grant (BG) 5-11 Grant Acknowledge (BGACK) 5-11 Master 3-28 Request (BR) 5-10 Signal Summary 5-13 Bus Arbitration Logic 3-28 External Bus Arbitration 3-28 Internal Bus Arbitration 3-28 MC68LC302 REFERENCE MANUAL B INDEX-1 ...
Page 163
... EMWS (External Master Wait State) 3-4, 3-5, 3-28 Enable Receiver 4-5 Enable Transmitter 4-6 Exception PB8 3-29 EXTAL 5-2, 5-4 External Bus Master 3-28 External Bus Arbitration using HALT 3-28 Master Wait State (EMWS) 3-5 External Bus Arbitration 3-28 External Master Wait State 3-4 FCR 3-13 Freeze Control 3-5 FRZ 5-7 Function Codes 3-13, 5-12 Comparison 2-4 FC2-FC0 2-4, 5-12 Register 3-13 MC68LC302 REFERENCE MANUAL E F MOTOROLA ...
Page 164
... IPL0 5-11 IPL1 5-11 IPL2 5-11 IPL2-IPL0 5-11 IPLCR 2-7, 2-10 IPR 3-15 IPWRD 2-15 IRQ1 5-12 ISDN 5-14 ISR 3-16 IWUCR 2-17 Loopback Control 4-3 Loopback Mode Internal Loopback 4-3 Loopback Control 4-3 Loopback mode 4-5 Low Power 2-13 68000 bus 2-13 Low Power Drive Control Register 2-13 Low Power Drive Control Register (LPDCR) MC68LC302 REFERENCE MANUAL Index L INDEX-3 ...
Page 165
... IMP 2-13 Low Power Support 2-15 FAST WAKE-UP 2-18 STOP/ DOZE/ STAND_BY Mode 2-16 Wake-Up from Low Power STOP Modes 2-17 Low-Power Clock Divider 2-9 LPDCR 2-15 LPM1–0 2-15 M MC68000/MC68008 Modes 2-1 MC68LC302 System Clock Generation IOMCR 2-6 IPLCR 2-6 IWUCR 2-6 MODCLK 2-7 PITR 2-6 VCCSYN 2-7 MF 11–0 2-11 MODCLK 2-12 MODCLK/PA12 5-5 MODCLK1–0 2-7 Multiplication Factor 2-11 ...
Page 166
... Serial Channels Physical Interface 4-2 Serial Communication Controllers 4-4 Serial Communication Port 4-25, 6-29 Serial Management Controllers 4-26 SMC1 Receive Buffer Descriptor 4-26 SMC1 Transmit Buffer Descriptor 4-26 SMC2 Receive Buffer Descriptor 4-27 SMC2 Transmit Buffer Descripto 4-27 Signals AS 3-3, 3-25 BERR 2-4, 3-3, 3-4, 3-5, 3-6 BG 3-28, 5-11 BGACK 5-11 BR 3-28, 3-29, 5-10 BUSW 2-1, 5-7 CD1 5-16 CLKO 5-4 CS 2-4, 3-3 CS0 3-26, 3-28, 5-21 CTS1 5-17 DISCPU 3-28, 5-7 MC68LC302 REFERENCE MANUAL Index S INDEX-5 ...
Page 167
... TRR1, TRR2 3-21 TTL Levels 5-2 TXD1/L1TXD 5-15 UART Controller 4-7 UART Event Register 4-9 UART Mask Register 4-9 UART Memory Map 4-7 UART Mode Register 4-8 UART Receive Buffer Descriptor 4-8 UART Transmit Buffer Descriptor 4-8 VCCSYN 2-12, 5-5 VCO 2-10, 2-11 Vector Generation Enable 3-5 Wake_Up Clock cycles, IMP 2-13 MC68LC302 REFERENCE MANUAL MOTOROLA ...
Page 168
... Wake-up PB10 2-18 PIT 2-18 PIT Event 2-18 Watchdog (WDOG) 3-18, 5-20 Hardware 3-5 Timer 3-22 Watchdog (WDOG) See Signals Watchdog (WDOG) See Timers WCN 3-22 WEH (UDS/A0) 5-9 WEL (LDS/DS) 5-10 Write Protect Violation 3-3 WRR 3-22 X XFC 2-12, 5-5 XTAL 5-4 MOTOROLA MC68LC302 REFERENCE MANUAL Index INDEX-7 ...
Page 169
... Index INDEX-8 MC68LC302 REFERENCE MANUAL MOTOROLA ...