ADSP2181 Analog Devices, ADSP2181 Datasheet
ADSP2181
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ADSP2181 Summary of contents
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... Final Systems ICE-Port is a trademark of Analog Devices, Inc. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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... See the Designing An EZ-ICE-Compatible Target System sec- tion of this data sheet for exact specifications of the EZ-ICE target board connector. EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc. Additional Information This data sheet provides a general overview of ADSP-2181 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’ ...
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ADSP-2181 can fetch an operand from program memory and the next instruction in the same cycle. In addition to the address and data bus for external memory connection, the ADSP-2181 has a 16-bit Internal DMA port (IDMA port) for connection ...
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ADSP-2181 • SPORTs support serial data word lengths from bits and provide optional A-law and -law companding according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word ...
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Table I. Interrupt Priority and Interrupt Vector Addresses Interrupt Vector Source of Interrupt Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power-Down (Nonmaskable) 002C IRQ2 0004 IRQL1 0008 IRQL0 000C SPORT0 Transmit 0010 SPORT0 Receive 0014 IRQE 0018 ...
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ADSP-2181 When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to in- coming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock ...
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Memory Architecture The ADSP-2181 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O. Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ...
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ADSP-2181 There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as ...
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When the BWCOUNT register is written with a nonzero value, the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a ...
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ADSP-2181 If Go Mode is enabled, the ADSP-2181 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2181 is performing an external memory access when the external device asserts the BR ...
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The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca- tion—you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spac- ing should be ...
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ADSP-2181–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter V Hi-Level Input Voltage IH V Hi-Level CLKIN Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level Output ...
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ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0 Input Voltage . ...
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ADSP-2181 Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI CLKIN Width Low t CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High ...
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Parameter Interrupts and Flag Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low t IFS IRQx, FI, or PFx Hold after CLKOUT High t IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay ...
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ADSP-2181 Parameter Bus Request/Grant Timing Requirements: BR Hold after CLKOUT High Setup before CLKOUT Low t BS Switching Characteristics: CLKOUT High to xMS RD, WR Disable xMS, RD SDB Disable to BG Low ...
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Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, ...
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ADSP-2181 Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, xMS Setup before WR Low t ASW Data ...
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Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to ...
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ADSP-2181 Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA ...
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Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write ...
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ADSP-2181 Parameter IDMA Write, Long Write Cycle Timing Requirements: IACK Low before Start of Write t IKW IAD15–0 Data Setup before IACK Low t IKSU IAD15–0 Data Hold after IACK Low t IKH Switching Characteristics: Start of Write to IACK ...
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Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Setup before IACK Low IKDS t ...
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ADSP-2181 Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read ...
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OUTPUT DRIVE CURRENTS Figure 19 shows typical I-V characteristics for the output drivers of the ADSP-2181. The curves represent the current drive capability of the output drivers as a function of output voltage. 120 100 ...
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ADSP-2181 CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2181 100 150 C – Figure 22. Range of Output Rise Time vs. Load Capaci- tance, ...
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ENVIRONMENTAL CONDITIONS Ambient Temperature Rating – (PD ) AMB CASE Case Temperature in C CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal Resistance ...
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ADSP-2181 128 1 IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP PWD ...
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TQFP Pin TQFP Number Name Number 1 IAL 33 2 PF3 34 3 PF2 35 4 PF1 36 5 PF0 IOMS 8 40 BMS 9 41 DMS 10 42 CMS ...
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ADSP-2181 128 1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP 32 33 128-Lead PQFP Package ...
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PQFP Pin PQFP Number Name Number 1 PF0 IOMS 4 36 BMS 5 37 DMS 6 38 CMS GND 40 9 VDD 41 PMS ...
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ADSP-2181 128-Lead Metric Plastic Quad Flatpack (PQFP) (S-128) 31.45 (1.238) 30.95 (1.219) 28.10 (1.106) 4.07 27.90 (1.098) (0.160) MAX 24.87 (0.979) 24.73 (0.974) 1.03 (0.041) 128 0.65 (0.031) 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.10 (0.004 MAX ...