ADSP21062 Analog Devices, ADSP21062 Datasheet
ADSP21062
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ADSP21062 Summary of contents
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... SHIFTER SHARC is a registered trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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... Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator (Jumpers in Place Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 EZ-ICE is a registered trademark of Analog Devices, Inc. Multiprocessing Glueless Connection for Scalable DSP Multiprocessing Architecture Distributed On-Chip Bus Arbitration for Parallel Bus ...
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S GENERAL NOTE This data sheet represents production released specifications for the ADSP-21062 (5 V) and ADSP-21062L (3.3 V) processors, for both 33 MHz and 40 MHz speed grades. The product name “ADSP-21062” is used throughout this data sheet to ...
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ADSP-21062/ADSP-21062L ADSP-21000 FAMILY CORE ARCHITECTURE The ADSP-21062 includes the following architectural features of the ADSP-21000 family core. The ADSP-21062 processors are code- and function-compatible with the ADSP-21020. Independent, Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter all per- ...
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Off-Chip Memory and Peripherals Interface The ADSP-21062’s external port provides the processor’s inter- face to off-chip memory and peripherals. The 4-gigaword off- chip address space is included in the ADSP-21062’s unified address space. The separate on-chip buses—for PM addresses, PM ...
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ADSP-21062/ADSP-21062L 1x CLOCK RESET Figure 3. Shared Memory Multiprocessing System ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 011 ID 2-0 CONTROL CPA 1-2 4 ADSP-2106x ...
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... Analog Devices sales office, distributor or the Literature Center. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard- ware tools include SHARC PC plug-in cards, multiprocessor SHARC VME boards, and daughter card modules with multiple SHARCs and additional memory ...
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ADSP-21062/ADSP-21062L PIN FUNCTION DESCRIPTIONS ADSP-21062 pin definitions are listed below. All pins are iden- tical on the ADSP-21062 and ADSP-21062L. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, ...
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Pin Type Function SBTS Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, I/S data, selects and strobes in a high impedance state for the following cycle. If the ADSP-21062 attempts to access external ...
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ADSP-21062/ADSP-21062L Pin Type Function TFSx I/O Transmit Frame Sync (Serial Ports 0, 1). RFSx I/O Receive Frame Sync (Serial Ports 0, 1). LxDAT I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has internal pull-down resistor ...
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TARGET BOARD CONNECTOR FOR EZ-ICE PROBE The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ- ICE probe requires the ADSP-2106x’s CLKIN, TMS, ...
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ADSP-21062/ADSP-21062L Figure 6 shows JTAG scan path connections for systems that contain multiple ADSP-2106x processors. Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform operations such as starting, stopping, ...
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ADSP-21062–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (5 V) Parameter V Supply Voltage DD T Case Operating Temperature CASE 1 V High Level Input Voltage IH1 2 V High Level Input Voltage IH2 Low Level Input Voltage IL NOTES 1 ...
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ADSP-21062/ADSP-21062L POWER DISSIPATION ADSP-21062 (5 V) These specifications apply to the internal power portion of V tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see the technical ...
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ADSP-21062L–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (3.3 V) Parameter V Supply Voltage DD T Case Operating Temperature CASE 1 V High Level Input Voltage IH1 2 V High Level Input Voltage IH2 Low Level Input Voltage IL NOTES 1 ...
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ADSP-21062/ADSP-21062L POWER DISSIPATION ADSP-21062L (3.3 V) These specifications apply to the internal power portion of V tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see the technical ...
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ABSOLUTE MAXIMUM RATINGS (5 V DEVICE)* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0 Input Voltage ...
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ADSP-21062/ADSP-21062L Parameter Clock Input Timing Requirements: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t CLKIN Rise/Fall (0.4 V–2.0 V) CKRF Parameter Reset Timing Requirements: RESET Pulsewidth Low t WRST RESET Setup Before CLKIN ...
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Parameter Timer Switching Characteristic: t CLKIN High to TIMEXP DTEX CLKIN t DTEX TIMEXP Parameter Flags Timing Requirements: t FLAG3-0 Setup Before CLKIN High SFI IN t FLAG3-0 Hold After CLKIN High HFI IN Delay After RD/WR Low t FLAG3-0 ...
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ADSP-21062/ADSP-21062L Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing external memory space. These switching Parameter Timing Requirements: t ...
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Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing external memory space. These switching Parameter Timing Requirements: t ACK ...
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ADSP-21062/ADSP-21062L Synchronous Read/Write—Bus Master Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-21062 (in multiprocessor memory space). These synchronous switching characteristics are also valid during asyn- chronous memory reads and ...
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CLKIN t DADCCK ADRCLK t DADRO ADDRESS MSx, SW PAGE ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE WR DATA (OUT) REV ADRCKH t DAAK t DPGC t DRWL t DRWL t SDDATO Figure 15. Synchronous Read/Write—Bus ...
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ADSP-21062/ADSP-21062L Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21062 bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor Parameter Timing Requirements: Address, SW Setup Before CLKIN t SADRI Address, SW Hold Before CLKIN t HADRI RD/WR ...
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CLKIN ADDRESS SW ACK READ ACCESS RD DATA (OUT) WRITE ACCESS WR DATA (IN) REV SADRI t DACKAD t SRWLI t SDDATO t SRWLI Figure 16. Synchronous Read/Write—Bus Slave –25– ADSP-21062/ADSP-21062L t HADRI t ACKTR t t HRWLI ...
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ADSP-21062/ADSP-21062L Multiprocessor Bus Request and Host Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-21062s (BRx host processor (HBR, HBG). Parameter Timing Requirements: HBG Low to RD/WR/CS Valid t HBGRCSV HBR Setup Before CLKIN ...
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CLKIN t SHBRI HBR HBG (OUT) BRx (OUT) CPA (OUT) (O/D) HBG (IN) BRx (IN) CPA (IN) (O/D) t SRPBAI RPBA HBR AND CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D ...
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ADSP-21062/ADSP-21062L Asynchronous Read/Write—Host to ADSP-21062 Use these specifications for asynchronous host processor accesses of an ADSP-21062, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-21062, the host can Parameter Read Cycle Timing Requirements: ...
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READ CYCLE ADDRESS/CS RD DATA (OUT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 18b. Asynchronous Read/Write—Host to ADSP-21062 REV SADRDL t ...
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ADSP-21062/ADSP-21062L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN Parameter Timing Requirements: SBTS Setup Before CLKIN t STSCK SBTS Hold Before CLKIN t ...
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DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand- shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer ...
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ADSP-21062/ADSP-21062L CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO ...
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Link Ports: 1 CLK Speed Operation Parameter Receive Timing Requirements: t Data Setup Before LCLK Low SLDCL t Data Hold After LCLK Low HLDCL t LCLK Period (1 Operation) LCLKIW t LCLK Width Low LCLKRWL t LCLK Width High LCLKRWH ...
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ADSP-21062/ADSP-21062L Link Ports: 2 CLK Speed Operation Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup ...
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TRANSMIT CLKIN t DLCLK t t LCLKTWH LCLKTWL LCLK 1x OR LCLK 2x t DLDCH t HLDCH LDAT(3:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH RECEIVE CLKIN ...
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ADSP-21062/ADSP-21062L Serial Ports Parameter External Clock Timing Requirements: t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK SDRE t Receive Data Hold After RCLK HDRE t TCLK/RCLK Width SCLKW t TCLK/RCLK ...
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NOTES 1 Referenced to sample edge. 2 RFS hold after RCK when MCE = 1, MFD = minimum from drive edge. TFS hold after TCK for late external TFS minimum from drive edge. ...
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ADSP-21062/ADSP-21062L RCLK RFS DT TCLK TFS DT EXTERNAL RFS with MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t (SEE NOTE 2 HOFSE/I ON PREVIOUS PAGE) t SFSE/I t DDTE DDTENFS HDTE/I 1ST BIT t DDTLFSE LATE ...
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JTAG Test Access Port and Emulation Parameter Timing Requirements: t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK Low SSYS t System Inputs ...
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ADSP-21062/ADSP-21062L OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-21062. The curves represent the current drive capability of the output drivers as a function of output voltage. POWER DISSIPATION Total power dissipation has ...
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Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate t using the equation given above. Choose V DECAY to be the difference between the ADSP-21062’s output voltage and the input threshold ...
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ADSP-21062/ADSP-21062L 100 5.25V, – ° 5.0V, +25 C –25 –50 ° 4.75V, +85 C –75 5.0V, +25 –100 –125 –150 –175 –200 0 0.75 1.50 2.25 3.00 SOURCE VOLTAGE – V Figure 28. ADSP-21062 Typical ...
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Y = 0.0391X + 0. RISE TIME 4 3 FALL TIME 100 120 LOAD CAPACITANCE – pF Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. ...
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ADSP-21062/ADSP-21062L 225-Ball Plastic Ball Grid Array (PBGA) Package Descriptions Ball # Name Ball # BMS A01 D01 A02 ADDR30 D02 DMAR2 A03 D03 A04 DT1 D04 A05 RCLK1 D05 A06 TCLK0 D06 A07 RCLK0 D07 A08 ADRCLK D08 CS A09 ...
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Plastic Ball Grid Array (PBGA) Package Pinout BR3 DATA42 DATA44 DATA47 BR2 DATA39 DATA43 DATA45 DATA36 DATA38 DATA41 DATA46 DATA34 DATA35 DATA37 DATA40 DATA31 DATA32 DATA30 DATA33 DATA27 DATA28 DATA26 DATA29 DATA23 DATA24 DATA25 DATA22 ...
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ADSP-21062/ADSP-21062L 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.101 (2.57) 0.091 (2.32) 0.081 (2.06) NOTES 1.THE ACTUAL POSITION OF THE BALL ARRAY IS WITHIN 0.12 (0.30) OF ITS IDEAL POSITION RELATIVE TO THE EDGE OF THE PACKAGE. 2.THE ACTUAL POSITION OF ...
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Pin Pin Pin Pin No. Name No. Name 1 TDI 41 ADDR20 TRST 2 42 ADDR21 3 VDD 43 GND 4 TDO 44 ADDR22 5 TIMEXP 45 ADDR23 EMU 6 46 ADDR24 7 ICSA 47 VDD 8 FLAG3 48 GND ...
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ADSP-21062/ADSP-21062L 0.030 (0.75) 0.024 (0.60) TYP 0.020 (0.50) SEATING PLANE LEAD PITCH 0.01969 (0.50) TYP LEAD WIDTH 0.011 (0.27) 0.009 (0.22) TYP 0.007 (0.17) 0.004 (0.10) MAX 0.010 (0.25) MIN Case Part Number Temperature Range ADSP-21062KS-133 +85 ...