VSC7125 Vitesse Semiconductor Corp., VSC7125 Datasheet
VSC7125
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VSC7125 Summary of contents
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... TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7125 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one twentieth of the incoming baud rate and detects Fibre Channel “ ...
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... Serializer The VSC7125 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differ- ential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specifi ...
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... RCLK and RCLKN. If serial input data is not present, or does not meet the required baud rate, the VSC7125 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than +1% ...
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... Receiving Two Consecutive K28.5+TChar Transmission Words RCLK RCLKN COM_DET R0:9 Potentially Corrupted Page 4 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION K28.5 TChar TChar TChar K28.5 TChar TChar VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 TChar K28.5 TChar G52121-0, Rev. 4.1 4/23/98 ...
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... Data Sheet VSC7125 REFCLK T0:9 Data Valid 10 Bit Data AC Characteristics Table 1: Transmit AC Characteristics Parameters Description T0:9 Setup time to the rising T 1 edge of REFCLK T0:9 hold time after the T 2 rising edge of REFCLK T ,T TX+/TX- rise and fall time SDR SDF Latency from rising edge of T REFCLK to T0 appearing on ...
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... — 2.4 15bc + 2ns 34bc + 2ns — 2.4 — 40 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 Units Conditions Measured between the ns. 1.4V point of RCLK or RCLKN and a valid level of R0:9. All outputs ns. driving 10pF load. Nominal delay is 10 bit times. Tested on sample ps. basis Whether or not locked to ...
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... Data Sheet VSC7125 RCLK RCLKN R0:9 Data Valid REFCLK Table 3: Reference Clock Requirements Parameters Description FR Frequency Range FO Frequency Offset DC REFCLK duty cycle T ,T REFCLK rise and fall time RCR RCF REFCLK Jitter Power REFCLK 5 MHz Jitter PhaseNoise 100 Hz REFCLK Jitter Power REFCLK ...
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... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION TTL Input and Output Rise and Fall Time 80% 20 Bit Time Amplitude Eye Width% Parametric Test Load Circuit TTL A.C. Output Load 75 V – 2.0V DD VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 V ih(min) V il(max G52121-0, Rev. 4.1 4/23/98 ...
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... V DD INPUT R GND REFCLK and TTL Inputs A G52121-0, Rev. 4.1 4/23/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION DATA 106.25MHz DATA VSC7125 TX TX+ REFCLK 1.0625 Gb/s TX- Single-Ended Measurement T0:9 Figure 9: Input Structures INPUT Current Limit INPUT R VITESSE SEMICONDUCTOR CORPORATION 1 ...
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... VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 Units Conditions I = -1.0 mA — +1 – 2 mVp-p (TX – 2 mVp-p (TX+ - TX-) Internally biased to Vdd/2 mVp-p ...
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... Data Sheet VSC7125 Package Pin Descriptions V SSD DDD DDD SSD V SSD N/C (Top View) Table 4: Pin Identification Pin # Name INPUTS - TTL 2-4, 6-9, 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of T0:9 11-13 REFCLK. The data bit corresponding transmitted first. ...
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... VDDT TTL Output Ground 32, 33, 46 VSST PECL I/O Power Supply 53, 60, 63 VDDP 16,17,27, N/C No Connection. These pins are not internally connected. 48,49,64 Page 12 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 G52121-0, Rev. 4.1 4/23/98 ...
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... Data Sheet VSC7125 Package Information 0.30 RAD. TYP. 0.20 RAD G52121-0, Rev. 4.1 4/23/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 64-pin PQFP Package Dimensions TYP e 0 TYP A . TYP . 0.17 MAX. 0.25 L VITESSE SEMICONDUCTOR CORPORATION 1 ...
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... Gbits/sec Fibre Channel Transceiver Package Thermal Considerations The VSC7125 is packaged in either PQFP PQFP with internal heat spreaders. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is as shown in Figure 11. ...
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... Data Sheet VSC7125 Ordering Information The part number for this product is formed by a combination of the device number and the package style: Device Type: VSC7125: 1.0625 Gbps Transceiver Package Style (64-pin) QN: 14x14mm PQFP QU: 10x10mm PQFP Marking Information The package is marked with three lines of text as shown below (QU Package): Pin Identifi ...
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... Gbits/sec Fibre Channel Transceiver Page 16 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7125 G52121-0, Rev. 4.1 4/23/98 ...