VSC8111 Vitesse Semiconductor Corp., VSC8111 Datasheet

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VSC8111

Manufacturer Part Number
VSC8111
Description
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

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Part Number:
VSC8111QB
Manufacturer:
VITESSE
Quantity:
12 388
Part Number:
VSC8111QB
Manufacturer:
VITESSE
Quantity:
127
VSC8111
G52142-0, Rev 4.2
8/31/98
Data Sheet
Features
General Description
unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high
speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-
ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.
VSC8111 Block Diagram
TXDATAOUT+/-
TXCLKOUT+/-
RXDA TAIN+/-
The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication
RXCLKIN+/-
• Operates at Either STS-3/STM-1 (155.52 Mb/s) or
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52 Mhz
• Dual 8 Bit Parallel TTL Interface
• SONET/SDH Frame Detection and Recovery
EQULOOP
FACLOOP
STS-12/STM-4 (622.08 Mb/s) Data Rates
or 622.08 Mhz High Speed Clock
LOSPOL
LOSTTL
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
0
1
LOS (Internal Signal)
VITESSE
SEMICONDUCTOR CORPORATION
Q
D Q
D
VITESSE SEMICONDUCTOR CORPORATION
1
0
1
0
1
Mux/Demux with Integrated Clock Generation
0
ATM/SONET/SDH 155/622 Mb/s Transceiver
0
1
0
1
• Loss of Signal (LOS) Control
• Provides Equipment, Facilities and Split Loop-
• Meets Bellcore, ITU and ANSI Specifications for
• Single 3.3V Supply Voltage
• Low Power - 1.4 Watts Maximum
• 100 PQFP Package
back Modes as well as Loop Timing Mode
Jitter Performance
Divide-by-8
Divide-by-8
Divide-by-3/12
FRAMER
DEMUX
CMU
MUX
1:8
8:1
D Q
Q D
1
0
8
8
LOS
OOF
FP
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
RX50MCK
LOOPTIM0
REFCLK
LOOPTIM1
EQULOOP
Page 1

Related parts for VSC8111

VSC8111 Summary of contents

Page 1

... SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip- ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for ATM physical layers and SONET/SDH systems applications. ...

Page 2

... The VSC8111 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface (UNI) devices such as the PM5355 S/UNI-622 (or PM5312 STTX). The VSC8111 transmit section converts 8 bit parallel data at 77.76 Mb/s or 19.44 Mb serial bit stream at 622.08 Mb/s or 155.52 Mb/s, respectively. It also provides a Facility Loopback function which loops the received high speed data and clock directly to the transmit outputs ...

Page 3

... RXCLKIN- 1 CMU Loss of Signal During a LOS condition, the VSC8111 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. The receive section is clocked by the transmit section’s G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...

Page 4

... ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation PLL clock multiplier. The VSC8111 has two TTL inputs LOSTTL and LOSPOL one to force the part into a Loss of Signal state, the other to control the polarity. The LOSTTL and LOSPOL inputs are XNOR’d to gener- ate an internal LOS control signal. See Figure 2. Optics have either a PECL or TTL output, usually called “ ...

Page 5

... Data Sheet VSC8111 lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In ...

Page 6

... OUT frequency. Clock Multiplier Unit The VSC8111 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed- back system ...

Page 7

... Data Sheet VSC8111 Clock Multiplier Unit Table 2: Reference Frequency Selection and Output Frequency Control STS12 G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 155/622 Mb/s Transceiver ...

Page 8

... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description (1) (1) (1) (1) (2) (3) (3) (3) (3) T RXCLK T T RXSU RXH Description VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 Min Typ Max Units -20 +20 ppm ...

Page 9

... Data Sheet VSC8111 Table 5: Receive High Speed Data Input Timing Table (STS-3 Operation) Parameter T Receive clock period RXCLK T Serial data setup time with respect to RXCLKIN RXSU T Serial data hold time with respect to RXCLKIN RXH Figure 8: Transmit Data Input Timing Diagram TXLSCKOUT ...

Page 10

... RXLSCKOUT T Pulse width of frame detection pulse FP PW Page 10 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION T RXCLKIN T RXLSCK Description Description VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 RXVALID Min Typ Max Units - 1.608 - ns - 12. 4.0 - ...

Page 11

... Skew between the falling edge of TXCLKOUT+ and T SKEW valid data on TXDATAOUT Data Latency The VSC8111 contains several operating modes, each of which exercise different logic paths through the part. Table 12 bounds the data latency through each path with an associated clock signal. Table 12: Data Latency Circuit Mode Transmit ...

Page 12

... V DD 600 — 600 — 1.5 — — 400 — V 1.5 – — – 1.0 – 2.4 — VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 Max Units Conditions 10-90% — ns 10-90% — ns 20-80% — ps 20-80% — ps Max Units Conditions — – 0.9V V — — V — – 1.3V V ...

Page 13

... Data Sheet VSC8111 Table 14: PECL and TTL Inputs and Outputs Parameters Description Output LOW V OL voltage (TTL) Input HIGH V IH voltage (TTL) Input LOW V IL voltage (TTL) Input HIGH I IH current (TTL) Input LOW current I IL (TTL) Power Dissipation Table 15: Power Supply Currents (Outputs Open) ...

Page 14

... Extended Operating Temperature Range* (T)..................................................................................... 0 Industrial Operating Temperature Range* (T) ................................................................................... -40 * Lower limit of specification is ambient temperature and upper limit is case temperature. Page 14 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION (1) VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 +0. 0. +125 C o ...

Page 15

... Data Sheet VSC8111 Package Pin Description Table 16: Pin Definitions Signal Pin FACLOOP 1 VDD 2 N/C 3 RESET 4 LOOPTIM0 VDD 9 TXDATAOUT+ 10 TXDATAOUT- 11 VSS 12 TXCLKOUT+ 13 TXCLKOUT- 14 VDD 15 N/C 16 N/C 17 VSS 18 RXCLKIN+ 19 RXCLKIN- 20 VDD 21 OOF 22 N/C 23 RXDATAIN+ 24 RXDATAIN VDD N/C 30 G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • ...

Page 16

... Loss of Signal Polarity +3.3V +3.3V Power Supply GND Ground I TTL Reference clock input, refer to table 3 I TTL Enable loop timing operation; active HIGH +3.3V +3.3V Power Supply GND Analog Ground (CMU) GND Analog Ground (CMU) No connection No connection VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 Pin Description G52142-0, Rev 4.2 8/31/98 ...

Page 17

... Data Sheet VSC8111 Table 16: Pin Definitions Signal Pin CP1 63 CN1 64 CN2 65 CP2 66 VDDA 67 VDDA 68 VDDA 69 VSSA 70 VSSA 71 VSS 72 N/C 73 N/C 74 VSS 75 VDD 76 N/C 77 N/C 78 N/C 79 N/C 80 VDD 81 TXLSCKOUT 82 TXLSCKIN 83 VSS 84 TXIN7 85 TXIN6 86 VSS 87 TXIN5 88 TXIN4 89 N/C 90 TXIN3 91 TXIN2 92 VSS 93 TXIN1 94 TXIN0 95 G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...

Page 18

... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION I/O Level No connection I TTL 155Mb/s or 622Mb/s mode select, refer to table 2 No connection +3.3V +3.3V Power Supply I TTL Equipment loopback, active high VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 Pin Description G52142-0, Rev 4.2 8/31/98 ...

Page 19

... Data Sheet VSC8111 Package Information PIN 100 PIN 1 RAD 2.92 EXPOSED HEATSINK (NOTE 2) 9.0 X 9.0 (N0TE 2) PIN NOTES: (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; square or oval. (3) All units in millimeters unless otherwise noted G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...

Page 20

... ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation The VSC8111 is manufactured in a 100PQFP package which is supplied by two different vendors. The crit- ical dimensions in the drawing represent the superset of dimensions for both packages. The significant differ- ence between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink ...

Page 21

... Commercial Temperature ambient case VSC8111QB1 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Extended Temperature ambient to 110 C case VSC8111QB2 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Industrial Temperature, -40 C ambient case Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confi ...

Page 22

... Since the byte clock (TXLSCKOUT) clocks both the VSC8111 and the UNI devices important to pay close attention to the routing of this signal. The UNI device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data out for the PM5355), which utilizes most of the 12 ...

Page 23

... Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for conve- nience. The VSC8111 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics mod- ule, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should be employed ...

Page 24

... R4 C1, C2, C3, C4 TTL Input Structure The TTL inputs of the VSC8111 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol- erances (see Table 14). The input structure, shown in Figure 13, uses a current limiter to avoid overdriving the input FETs. Layout of the High Speed Signals The routing of the High Speed signals should be done using good high speed design practices ...

Page 25

... Data Sheet VSC8111 V +3 INPUT R GND REFCLK and TTL Inputs G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Figure 13: Input Structures INPUT Current Limit INPUT R VITESSE SEMICONDUCTOR CORPORATION ...

Page 26

... ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Page 26 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 G52142-0, Rev 4.2 8/31/98 ...

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