AT90S8515

Manufacturer Part NumberAT90S8515
Description8-bit microcontroller with 8K bytes in-system programmable flash, 2.7-6.0V
ManufacturerATMEL Corporation
AT90S8515 datasheet
 
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Instruction Set Summary (Continued)

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Instruction Set Summary (Continued)

Mnemonic
Operands
Description
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move between Registers
LDI
Rd, K
Load Immediate
LD
Rd, X
Load Indirect
LD
Rd, X+
Load Indirect and Post-inc.
LD
Rd, -X
Load Indirect and Pre-dec.
LD
Rd, Y
Load Indirect
LD
Rd, Y+
Load Indirect and Post-inc.
LD
Rd, -Y
Load Indirect and Pre-dec.
LDD
Rd, Y+q
Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+
Load Indirect and Post-inc.
LD
Rd, -Z
Load Indirect and Pre-dec.
LDD
Rd, Z+q
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-inc.
ST
-X, Rr
Store Indirect and Pre-dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-inc.
ST
-Y, Rr
Store Indirect and Pre-dec.
STD
Y+q, Rr
Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-inc.
ST
-Z, Rr
Store Indirect and Pre-dec.
STD
Z+q, Rr
Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, b
Set Bit in I/O Register
CBI
P, b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left through Carry
ROR
Rd
Rotate Right through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit Load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Two’s Complement Overflow
CLV
Clear Two’s Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half-carry Flag in SREG
CLH
Clear Half-carry Flag in SREG
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
0841G–09/01
AT90S8515
Operation
Flags
Rd ← Rr
None
Rd ← K
None
Rd ← (X)
None
Rd ← (X), X ← X + 1
None
X ← X - 1, Rd ← (X)
None
Rd ← (Y)
None
Rd ← (Y), Y ← Y + 1
None
Y ← Y - 1, Rd ← (Y)
None
Rd ← (Y + q)
None
Rd ← (Z)
None
Rd ← (Z), Z ← Z + 1
None
Z ← Z - 1, Rd ← (Z)
None
Rd ← (Z + q)
None
Rd ← (k)
None
(X)=← Rr
None
(X)=← Rr, X ← X + 1
None
X ← X - 1, (X) ← Rr
None
(Y) ← Rr
None
(Y) ← Rr, Y ← Y + 1
None
Y ← Y - 1, (Y) ← Rr
None
(Y + q) ← Rr
None
(Z) ← Rr
None
(Z) ← Rr, Z ← Z + 1
None
Z ← Z - 1, (Z) ← Rr
None
(Z + q) ← Rr
None
(k) ← Rr
None
R0 ← (Z)
None
Rd ← P
None
P ← Rr
None
STACK ← Rr
None
Rd ← STACK
None
I/O(P,b) ← 1
None
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)
Z,C,N,V
Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n = 0..6
Z,C,N,V
Rd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0)
None
SREG(s) ← 1
SREG(s)
SREG(s) ← 0
SREG(s)
T ← Rr(b)
T
Rd(b) ← T
None
C ← 1
C
C ← 0
C
N ← 1
N
N ← 0
N
Z ← 1
Z
Z ← 0
Z
I ← 1
I
I=← 0
I
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
T ← 0
T
H ← 1
H
H ← 0
H
None
(see specific descr. for Sleep function)
None
(see specific descr. for WDR/timer)
None
# Clocks
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
107