AT90S8515

Manufacturer Part NumberAT90S8515
Description8-bit microcontroller with 8K bytes in-system programmable flash, 2.7-6.0V
ManufacturerATMEL Corporation
AT90S8515 datasheet
 
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Page 29/112:

External Interrupts

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External Interrupts

Interrupt Response Time
MCU Control Register –
MCUCR
0841G–09/01
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The external interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the external interrupt is
enabled and is configured as level-triggered, the interrupt will trigger as long as the pin
is held low.
The external interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the interrupt flag has been set, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is
decremented by 2. The vector is normally a relative jump to the interrupt routine, and
this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is
popped back from the stack, the Stack Pointer is incremented by 2 and the I-flag in
SREG is set. When the AVR exits from an interrupt, it will always return to the main pro-
gram and execute one more instruction before any pending interrupt is served.
Note that the Status Register (SREG) is not handled by the AVR hardware, for neither
interrupts nor subroutines. For the interrupt handling routines requiring a storage of the
SREG, this must be performed by user software.
For interrupts triggered by events that can remain static (e.g., the Output Compare
Register1 A matching the value of Timer/Counter1), the interrupt flag is set when the
event occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag
will not be set until the event occurs the next time. Note that an external level interrupt
will only be remembered for as long as the interrupt condition is active.
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
5
$35 ($55)
SRE
SRW
SE
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bit 7 – SRE: External SRAM Enable
When the SRE bit is set (one), the external data SRAM is enabled and the pin functions
AD0 - 7 (Port A), A8 - 15 (Port C), WR and RD (Port D) are activated as the alternate pin
functions. Then the SRE bit overrides any pin direction settings in the respective data
direction registers. See “SRAM Data Memory – Internal and External” on page 12 for a
description of the external SRAM pin functions. When the SRE bit is cleared (zero), the
external data SRAM is disabled and the normal pin and data direction settings are used.
• Bit 6 – SRW: External SRAM Wait State
When the SRW bit is set (one), a one-cycle wait state is inserted in the external data
SRAM access cycle. When the SRW bit is cleared (zero), the external data SRAM
access is executed with the normal three-cycle scheme. See Figure 43 and Figure 44.
AT90S8515
4
3
2
1
SM
ISC11
ISC10
ISC01
ISC00
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
MCUCR
0
29