GS9021 Gennum Corporation, GS9021 Datasheet
GS9021
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GS9021 Summary of contents
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... The GS9021 implements error detection and handling (EDH) according to SMPTE RP-165. Interfacing to the parallel inputs of either the GS9002, GS9022 or GS9032 serial digital encoders, the GS9021 is primarily used on the transmit end of the SDI interface. The GS9021 provides EDH insertion and extraction for 4ƒsc NTSC, 4ƒsc PAL and all component PAL and NTSC standards including 4:2:2 (13 ...
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ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Lead Temperature (soldering, 10 sec) DC ELECTRICAL CHARACTERISTICS V = 5.0V 70°C unless otherwise shown PARAMETER SYMBOL Supply ...
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AC ELECTRICAL CHARACTERISTICS V = 5.0V 70°C unless otherwise shown PARAMETER SYMBOL Input Clock Frequency Clock Pulse Width Low t PWL Clock Pulse Width High t PWH Input Setup Time t S Input Hold ...
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... I²C mode, this pin must be set LOW. I Parallel port chip select. When CS is LOW and R/W is HIGH, the GS9021 drives the address/data bus. When CS is LOW and R/W is LOW, the user should drive the address/data bus. When CS is HIGH, the address/data bus high impedance state (Hi - Z). In I² ...
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PIN DESCRIPTIONS NUMBER SYMBOL 28, 29 S[1:0] 30-34 FL[4:0] 35 F_R/W 36 FLAG_MAP 37-39, 42-48 DOUT[9: 51-53 F[2:0] 54 RESET 55 R/T 58 CRC_MODE 59 VBLANKS/L 60 BYPASS_EDH 61 LSB_TOP 62 BLANK_EN 63 FLYWDIS 64 CLIP_TRS ...
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... PIN PCLKIN The PCLKIN pin is the input used to clock the video data into the GS9021, and serves as the reference to which all synchronous inputs and outputs are timed. The following table shows which pins are synchronous with PCLKIN and which are not. Timing for synchronous I/O is found in Figures 1 and 2 ...
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... DOUT[9:0] output pins. The latency through the device is 8 clock cycles and is illustrated in Figure 3. The default position of the LSB is DOUT0. Asserting the LSB_TOP pin HIGH on the GS9021 reverses the order of the output bits, placing the LSB at DOUT9 and simplifying board layout in some applications. Figure 11 shows a simple application circuit illustrating the connections to the GS9032 ...
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... The SWITCHFLYW control signal is used in applications where the data input to the GS9021 is switched between two synchronous signals. In this case, the two signals may be slightly misaligned and would normally require the flywheel to completely re-synchronize. In this scenario, the re-synchronization time would be undesirable. Asserting the ...
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... EDH packet when the corresponding OVERWRITE CONTROL bit is asserted HIGH. See Table 3 for Host Interface WRITE table. The GS9021 also allows the user to overwrite the 7 reserved words of the OUTGOING EDH packet. When RO_CTRL (Reserved Word Overwrite Control) is asserted HIGH, the GS9021 overwrites the reserved words in the OUTGOING EDH packet with those specified in the HOSTIF write table ...
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CRC Calculation And Updating PIN LOGIC OPR Since the device has the potential of modifying the full-field and active picture data with features like ITU-R-601 clipping and TRS insertion, the full field and active picture CRC values must be ...
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... When the F_R/W pin is LOW, the flag port is in write mode and the FL[4:0] pins are configured as inputs. After writing to the flag port, the GS9021 inserts the written flags into the next outgoing EDH packet. Note that external flag overwriting via the flag port takes precedence over HOSTIF overwriting but the flag port write only affects the next outgoing EDH packet ...
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Write Mode, F_R S[1:0] FL4 FL3 FL2 00 FF UES FF IDA FF IDH 01 AP UES AP IDA AP IDH 10 ANC ANC ANC UES IDA IDH 11 IN/OUT APV FFV The IN/OUT bit has no effect ...
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... F_R/W pin must be asserted HIGH (set F_R/W at least one cycle ahead of FLAG_MAP). After a delay of t FL[4:0] and S[1:0] pins of the FLAG PORT become outputs and can be connected to the chip which you wish the GS9021 to write the FLAG data to. In this mode the GS9021 automatically increments the ...
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... TRS Insertion, and • ANC Header updating It is important to note that these processing functions occur in the GS9021 in the order listed above. When implementing applications which use the EDH core (ie. BYPASS_EDH set LOW), TRS blanking, data blanking, and TRS insertion will indicate a downstream FF/AP EDH ...
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... However, by setting BLANK_EN low, CLIP_TRS high and forcing the standard in the HOST write table, the GS9021 can be used to generate a blank, TRS formatted video stream (with or without EDH), just by supplying a clock to the device. The frequency of the clock being supplied should be less than or equal to the standard selected ...
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... AC timing tables, are relative to this edge and must be met (see Figure 8a) HOST BIT C) The GS9021 drives the P[7:0] bus when the R/W pin is HIGH and the CS pin is LOW. At all other times, the P[7:0] port high impedance state. The host interface enable and disable times are shown in Figure 8b and are specified in the AC timing information ...
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... An internal power-on-reset cell is also present in the device so that device initialization occurs on power-up. Figure 10a illustrates the reset circuitry. The internal power-on reset circuit of the GS9021 is sensitive to the rise time of the power supply, hence an external power on reset chip or , EDH 0 board level reset line is strongly recommended ...
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... LAT Fig. 3 Data Latency through the GS9021 18 COMMENTS / SUGGESTIONS Use this MODE if you wish to insert EDH not present. If EDH is present, clear all flags and update CRC. Use this MODE on the output EDH chip when mapping flags from an ...
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19 521 - ...
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521 - ...
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OS OH CLOCK DOUT [9:0] 000 3FF 000 EAV F [2: Fig. 4a FVH Timing for Component Video CLOCK DOUT [9:0] 3FF 000 F [2:0] H Fig and H Timing ...
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... FL[4: S[1: GS9020 or GS9021 CRC_MODE = 0 R (GS9021) GS9020 or GS9021 CRC_MODE = 0 FLAG MAP = 1 F_R R (GS9021) Fig. 6b Example of FLAG_MAP Mode Implementation 521 - F_R/W FL [4:0] PCLKIN AP FF ANC ANC Flags held at ANC between EDH packets FEN Double clocking Fig ...
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... Fig. 8b HOSTIF Parallel Port Output Enable and Disable Times WRITE CYCLE P[7:0] ADDRESS R/W A Fig. 7 Illustration of Data Blanking HEN GS9021 DRIVING READ CYCLE DATA IN ADDRESS Fig. 8c HOSTIF Parallel Port Read/Write Cycles 23 BLANKED SAMPLES HDIS DATA DATA t 4 ...
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... Switch (Optional) Fig. 10b Acceptable external reset circuit when a master reset is not available 521 - FIELD LINES VALID TIME TO READ/WRITE EDH INFORMATION TO/FROM GS9021 Fig. 9 Host Interface Read/Write Timing t MAX INTERNAL POWER on RESET CELL RESET PIN t RESET Fig. 10a Reset Circuitry ...
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... FIELD0 51 FIELD1 52 FIELD2 53 RESET 54 R/T 55 GND 56 VDD 57 CRC_MODE 58 VBLANKS/L 59 BYPASS_EDH 60 LSB_TOP 61 BLANK_EN 62 FLYWDIS 63 CLIP_TRS 64 INPUT CLOCK & DATA VIDEO Fig. 11 GS9021 - GS9032 Application Circuit AMP0 22 SS0 21 1k LOCK 20 R25 SD1_EN 19 VEE 18 VCC 17 SS1 16 SS2 15 NC(COSC) 14 VCC 13 VEE 12 FL2 32 FL1 31 FL0 ...
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... Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. 521 - ±1 BSC 16 ...