PSD913F2 STMicroelectronics, PSD913F2 Datasheet
PSD913F2
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PSD913F2 Summary of contents
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... High Endurance: – 100,000 Erase/Write Cycles of Flash Memory – 1,000 Erase/Write Cycles of PLD January 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD913F2 PSD934F2 PSD954F2 For 8-bit MCUs PRELIMINARY DATA Figure 1. Packages ...
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... Port Configuration Registers (PCRs) ............................................................................................................47 Port Data Registers.......................................................................................................................................49 Ports A and B – Functionality and Structure .................................................................................................49 Port C – Functionality and Structure .............................................................................................................51 Port D – Functionality and Structure .............................................................................................................51 i PSD9XX Family PSD913F2 PSD934F2 Table of Contents For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask ...
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... PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Power Management............................................................................................................................................54 Automatic Power Down (APD) Unit and Power Down Mode ........................................................................54 Other Power Savings Options.......................................................................................................................58 Reset and Power On Requirement ...............................................................................................................59 Programming In-Circuit using the JTAG Interface ..............................................................................................60 Standard JTAG Signals.................................................................................................................................61 JTAG Extensions ..........................................................................................................................................61 Security and Flash Memories Protection ......................................................................................................61 Absolute Maximum Ratings ...
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... AC Testing Input/Output Waveforms...........................................................................................................................81 AC Testing Load Circuit...............................................................................................................................................81 Programming ...............................................................................................................................................................81 Pin Assignments..........................................................................................................................................................82 Package Information....................................................................................................................................................84 Selector Guide.............................................................................................................................................................87 Part Number Construction ...........................................................................................................................................87 Ordering Information....................................................................................................................................................88 Document Revisions....................................................................................................................................................89 iii PSD9XX Family PSD913F2 PSD934F2 Table of Contents For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com PSD954F2 ...
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... Mbit of Flash memory • A secondary 256 Kbit Flash memory • Over 2,000 gates of Flash programmable logic • 256 Kbit SRAM • Reconfigurable I/O ports • Programmable power management. PSD913F2, PSD934F2, PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers 1 ...
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PSD9XX Family 1.0 The PSD9XX family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. Introduction (Cont.) In-System Programming (ISP) JTAG An IEEE 1149.1 compliant JTAG interface is included on the PSD ...
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Preliminary Information 2.0 A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by Key Features the microcontroller automatically when the address is decoded and a read or ...
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PSD9XX Family Figure 1. PSD9XX Block Diagram 4 Preliminary Information ...
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... I/O pins. The following table summarizes all the devices in the PSD9XX family. Family Additional devices will be introduced. Table 1. PSD9XX Product Matrix Part # PSD9XX I/O Family Device Pins GPLD Output PSD9XX PSD913F2 27 PSD934F2 27 PSD954F2 27 Flash Serial ISP Main Memory Flash Memory No. of JTAG/ISC Kbit ...
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PSD9XX Family 5.0 PSD9XX devices contain several major functional blocks. Figure 1 shows the architecture of the PSD9XX device family. The functions of each block are described PSD9XX briefly in the following sections. Many of the blocks perform multiple functions ...
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Preliminary Information PSD9XX 5.4 I/O Ports Architectural The PSD9XX has 27 I/O pins divided among four ports (Port and D). Each I/O pin can be individually configured for different functions. Ports and D can ...
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PSD9XX Family PSD9XX 5.7 In-System Programming Architectural Using the JTAG signals on Port C, the entire PSD9XX device can be programmed or erased without the use of the microcontroller (ISP). The main Flash memory can also be Overview programmed in-system ...
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Preliminary Information 6.0 The PSD9XX family is supported by PSDsoft Express, a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and Development click environment. The designer does not need to ...
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PSD9XX Family 7.0 The following table describes the pin names and pin functions of the PSD9XX. Pins that have multiple names and/or functions are defined using PSDsoft. Table 5. PSD9XX Pin Name Pin Descriptions ADIO0-7 ADIO8-15 CNTL0 CNTL1 10 Pin* ...
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Preliminary Information Table 5. Pin Name Pin* Type PSD9XX Pin CNTL2 Descriptions (cont.) Reset PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 (PLCC This pin can be used ...
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PSD9XX Family Table 5. Pin Name Pin* PSD9XX Pin PC2 Descriptions (cont.) PC3 PC4 PC5 PC6 12 Type (PLCC) 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O ...
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Preliminary Information Table 5. Pin Name Pin* PSD9XX Pin PC7 Descriptions (cont.) PD0 PD1 PD2 V CC GND * The pin numbers in this table are for the PLCC package only. See the package information section for pin numbers on ...
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PSD9XX Family 8.0 Table 7 shows the offset addresses to the PSD9XX registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the PSD9XX internal PSD9XX registers. ...
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... The memory select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 8 summarizes which versions of the PSD9XX contain which memory blocks. Table 8. Memory Blocks Device PSD913F2 PSD934F2 PSD954F2 9.1.1 Main Flash and Secondary Flash Memory Description The main Flash memory block is divided evenly into eight sectors. The secondary Flash memory is divided into four sectors of eight Kbytes each ...
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PSD9XX Family The 9.1.1.1 Memory Block Selects PSD9XX The decode PLD in the PSD9XX generates the chip selects for all the internal memory blocks (refer to the PLD section). Each of the eight Flash memory sectors have a Functional Flash ...
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Preliminary Information The 9.1.1.3.1 Instructions PSD9XX An instruction is defined as a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard write operation. The Functional instruction is executed when the ...
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PSD9XX Family The Table 9. Instructions PSD9XX Functional Instruction Blocks Read (Note 5) (cont.) Read Main Flash ID (Notes 6,13) Read Sector Protection (Notes 6,8,13) Program a Flash Byte Erase One Flash Sector Erase Flash Block (Bulk Erase) Suspend Sector ...
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... A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select signal (FSi) must be active. The PSD9XX main Flash memory ID is E7h (PSD934/954F2) and E4h (PSD913F2). 9.1.1.5.3 Read the Flash Memory Sector Protection Status The Flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 9) ...
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PSD9XX Family The 9.1.1.5.5 Data Polling Flag DQ7 PSD9XX When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the bit being entered for Programming/Writing on DQ7. Once the Program instruction or the Functional Write operation is ...
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Preliminary Information The 9.1.1.6 Programming Flash Memory PSD9XX Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all Functional ...
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PSD9XX Family The Figure 3. Data Polling Flow Chart PSD9XX Functional Blocks (cont.) 9.1.1.6.2 Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or Erase instruction is in progress or has completed. ...
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Preliminary Information The 9.1.1.6.2 Data Toggle PSD9XX It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to Flash with Functional the byte ...
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PSD9XX Family The 9.1.1.7 Unlock Bypass Instruction (PSD934F2 and PSD954F2 only) PSD9XX The unlock bypass feature allows the system to program bytes to the flash memories faster than using the standard program instruction. The unlock bypass instruction is Functional initiated ...
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Preliminary Information The 9.1.1.8.3 Flash Erase Suspend Instruction PSD9XX When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any address when an appropriate Chip Select Functional (FSi or ...
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... Bit Definitions: Sec<i>_Prot Sec<i>_Prot Security_Bit 9.1.1.9.2 Reset Instruction – PSD913F2 The Reset instruction consists of one write cycle (see Table 9). It can also be optionally preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to AAAh). The Reset instruction must be executed after: 1 ...
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Preliminary Information The 9.1.1.9.4 Reset Pin Input – PSD934F2, PSD954F2 PSD9XX The reset pulse input from the pin will abort any operation in progress and reset the Flash memory to Read Mode. When the reset occurs during a programming or ...
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PSD9XX Family The Figure 5. Priority Level of Memory and I/O Components PSD9XX Functional Blocks (cont.) 9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151, ...
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Preliminary Information The 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces PSD9XX 9.1.3.2.1 Separate Space Modes Functional Code memory space is separated from data memory space. For example, the PSEN Blocks signal is used to access the ...
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PSD9XX Family The 9.1.4 Page Register PSD9XX The eight bit Page Register increases the addressing capability of the microcontroller by a factor 256. The contents of the register can also be read by the microcontroller. Functional The ...
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Preliminary Information The 9.2 PLDs PSD9XX The PLDs bring programmable logic functionality to the PSD9XX. After specifying the chip selects or logic equations for the PLDs in PSDsoft, the logic is programmed into the Functional device and available upon power-up. ...
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PSD9XX Family Figure 9. PLD Block Diagrams 8 DATA BUS DECODE PLD 57 PURPOSE PLD 57 Figure 10. DPLD Logic Array I /O PORTS (PORT A,B,C) PGR0 - PGR7 2:0 ] (ALE,CLKIN,CSI) PDN ...
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Preliminary Information The 9.2.1 Decode PLD (DPLD) PSD9XX The DPLD, shown in Figure 10, is used for decoding the address for internal PSD components. The DPLD can generate the following chip selects: Functional Blocks • 8 sector selects for the ...
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PSD9XX Family Figure 11. General Purpose PLD and I/O Port 34 PLD INPUT BUS Preliminary Information ...
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Preliminary Information The 9.3 Microcontroller Bus Interface PSD9XX The “no-glue logic” PSD9XX Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their Functional bus types and control signals are shown ...
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PSD9XX Family The Figure 12. An Example of a Typical 8-Bit Multiplexed Bus Interface PSD9XX Functional Blocks (cont.) CONTROLLER RESET Figure 13. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface MICRO - CONTROLLER RESET 36 MICRO - AD [ ...
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Preliminary Information The 9.3.3 Microcontroller Interface Examples Figures 14 through 18 show examples of the basic connections between the PSD9XX PSD9XX and some popular microcontrollers. The PSD9XX Control input pins are labeled as to the Functional microcontroller function for which ...
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PSD9XX Family The Table 19. 80C251 Configurations PSD9XX Configuration Functional Blocks (cont.) 9.3.3.3 80C51XA The Philips 80C51XA microcontroller family supports 16-bit multiplexed bus that can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are ...
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Preliminary Information Figure 14. Interfacing the PSD9XX with an 80C31 80C31 31 EA/ RESET RESET 12 INT0 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 ...
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PSD9XX Family Figure 16. Interfacing the PSD9XX to the 80C251, with Read and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD ...
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Preliminary Information Figure 18. Interfacing the PSD9XX with a 68HC11 (Muxed Address/Data Bus) 68HC11 RESET RESET 19 IRQ 18 XIRQ 2 MODB 34 PA0 33 PA1 32 PA2 43 PE0 44 PE1 45 PE2 46 ...
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PSD9XX Family The 9.4 I/O Ports PSD9XX There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, ...
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DATA OUT REG. DATA OUT ADDRESS ADDRESS D Q ALE G GPLD OUTPUT READ MUX P D DATA IN B CONTROL REG DIR REG PORT PIN OUTPUT MUX OUTPUT SELECT PLD- ...
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PSD9XX Family The 9.4.2 Port Operating Modes PSD9XX The I/O Ports have several modes of operation. Some modes can be defined in PSDsoft, some by the microcontroller writing to the Control Registers in CSIOP space, and Functional some by both. ...
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Preliminary Information The Table 21. Port Operating Mode Settings PSD9XX Functional Blocks Mode (cont.) MCU I/O PLD I/O Data Port (Port A) Address Out (Port A,B) Address In (Port A,B,C,D) JTAG ISP * NA = Not Applicable 9.4.2.1 MCU I/O ...
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PSD9XX Family The 9.4.2.3 Address Out Mode PSD9XX For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external Functional devices. Either ...
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Preliminary Information The 9.4.3 Port Configuration Registers (PCRs) PSD9XX Each port has a set of PCRs used for configuration. The contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses Functional given ...
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PSD9XX Family The 9.4.3.3 Drive Select Register PSD9XX The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should ...
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Preliminary Information The 9.4.4 Port Data Registers PSD9XX The Port Data Registers, shown in Table 28, are used by the microcontroller to write data to or read data from the ports. Table 28 shows the register name, the ports having ...
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DATA OUT REG ADDRESS ADDRESS 7 15:8 ] ALE G GPLD OUTPUT READ MUX CONTROL REG DIR REG DATA OUT ...
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Preliminary Information The 9.4.6 Port C – Functionality and Structure PSD9XX Port C can be configured to perform one or more of the following functions (see Figure 21): Functional MCU I/O Mode Blocks PLD Input – Input to the PLDs. ...
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PSD9XX Family The Figure 21. Port C Structure PSD9XX Functional Blocks (cont.) 52 BUS DATA INTERNAL Preliminary Information ...
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DATA OUT REG. DATA OUT GPLD OUTPUT READ MUX DATA IN DIR REG PORT D PIN OUTPUT MUX OUTPUT SELECT PLD-INPUT ...
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PSD9XX Family The 9.5 Power Management PSD9XX The PSD9XX offers configurable power saving options. These options may be used individually or in combinations, as follows: Functional Blocks All memory types in a PSD (Flash, Secondary Flash Block, and SRAM) are ...
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Preliminary Information The 9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.) PSD9XX Power Down Mode Functional By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled. Blocks The device will enter Power ...
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PSD9XX Family The Figure 23. APD Logic Block PSD9XX Functional Blocks APD EN PMMR0 BIT 1=1 (cont.) ALE RESET CSI CLKIN Figure 24. Enable Power Down Flow Chart 56 TRANSITION DETECTION CLR APD COUNTER EDGE DETECT DISABLE MAIN FLASH/ SECONDARY ...
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Preliminary Information The Table 31. Power Management Mode Registers (PMMR0, PMMR2)** PSD9XX PMMR0 Functional Bit 7 Blocks * (cont.) *** Bits and 7 are not used, and should be set to 0, bit 5 should be set ...
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PSD9XX Family The Table 32. APD Counter Operation PSD9XX APD Functional Enable Bit Blocks 0 (cont 9.5.2 Other Power Saving Options The PSD9XX offers other reduced power saving options that are independent of the Power Down Mode. ...
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Preliminary Information The 9.5.3 Reset and Power On Requirement PSD9XX 9.5.3.1 Power On Reset Functional Upon power up the PSD9XX requires a reset pulse of tNLNH-PO (minimum 1 ms) after Blocks V is steady. During this time period the device ...
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PSD9XX Family The Table 33. Status During Power On Reset, Warm Reset and Power Down Mode PSD9XX Port Configuration Functional MCU I/O Blocks PLD Output (cont.) Address Out Data Port Register PMMR0 Register* All other registers * SR_cod ...
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Preliminary Information The 9.6.1 Standard JTAG Signals PSD9XX The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated ...
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PSD9XX Family Absolute Symbol Maximum T STG Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent Operating Range Range Commercial Industrial Commercial Industrial Recommended Symbol Operating Conditions ...
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Preliminary Information AC/DC The following tables describe the AD/DC parameters of the PSD9XX family: Parameters DC Electrical Specification AC Timing Specification • PLD Timing – Combinatorial Timing • Microcontroller Timing – Read Timing – Write Timing – Power Down and ...
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PSD9XX Family AC/DC Figure 26a. PLD I Parameters (cont.) Example of PSD9XX Typical Power Calculation at V Conditions Highest Composite PLD input frequency MCU ALE frequency (Freq ALE) Operational Modes Number of product terms used Turbo Mode Calculation (typical numbers ...
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Preliminary Information AC/DC Example of Typical Power Calculation at V Parameters Conditions (cont.) Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power ...
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PSD9XX Family PSD9XX DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin ...
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Preliminary Information Microcontroller AC Symbols for PLD Timing. Interface – Example: AC/DC Parameters Signal Letters (5V ± 10% Versions) A – Address Input C – CEout Output D – Input Data E – E Input L – ALE Input N ...
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PSD9XX Family Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) Read Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address ...
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Preliminary Information Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) Write Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address ...
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PSD9XX Family Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) Power Down Timing (5 V ± 10%) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD t Enable to Internal PDN CLWH Valid ...
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Preliminary Information Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) Flash Program, Write and Erase Times Symbol Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase (Not Preprogrammed) t Sector Erase (Preprogrammed to 00) WHQV3 t ...
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PSD9XX Family PSD9XXFV DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin ...
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Preliminary Information Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) Read Timing (3 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data ...
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PSD9XX Family Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) Write Timing (3 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t ...
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Preliminary Information Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) Power Down Timing (3 V Versions) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t CLWH to Internal PDN Valid Signal NOTE: ...
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PSD9XX Family Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) Flash Program, Write and Erase Times Symbol Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase (Not Preprogrammed) t Sector Erase (Preprogrammed to 00) WHQV3 t Sector ...
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Preliminary Information Figure 27. Read Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS) E R/W t AVPV * t and t are not required for 80C251 in Page Mode or 80C51XA in Burst ...
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PSD9XX Family Figure 28. Write Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t ...
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Preliminary Information Figure 29. Combinatorial Timing – PLD CPLD INPUT CPLD OUTPUT Figure 30. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO ISCCH t ISCCL t t ISCPSU ISCPH PSD9XX Family t ISCPZV t ISCPCO t ISCPVZ ...
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PSD9XX Family Figure 31. Reset Timing OPERATING LEVEL V CC RESET Figure 32. Key to Switching Waveforms WAVEFORMS 80 t NLNH–PO t OPR POWER ON RESET INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM LO TO ...
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Preliminary Information Pin Capacitance ° MHz A Symbol OUT C VPP NOTES: 1. These parameters are only sampled and are not 100% tested. 2. Typical values are for T Figure 33. ...
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PSD9XX Family PSD9XX 52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type J) Pin Pin No. Assignments ...
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Preliminary Information PSD9XX 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M) Pin Pin No. Assignments 1 (cont ...
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PSD9XX Family PSD9XX Figure 35. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLCC) Package Information Figure 36. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) 84 (Package Type PD2 PD1 9 10 ...
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Preliminary Information Figure 35A. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type Family: Plastic Leaded Chip Carrier Symbol Min A 4.19 A1 2.54 A2 3.66 B ...
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PSD9XX Family Figure 36A. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type Index 3 Mark B Family: Plastic Quad Flatpack (PQFP) Symbol Min 0° A – A2 1.95 B 0.22 C ...
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... NVM TYPE, SIZE & CONFIGURATION 1 = EEPROM, 256Kb 2 = FLASH, 256Kb 2nd Array MCU PLDs/Decoders PSD Data Path PLD Inputs @ Input Macrocells 3 V Output Macrocells PLD Outputs PSD913F1V 9 57 PSD913F2V 9 57 PSD934F2V 9 57 PSD954F2V ...
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... PSD9XX Family Ordering Information Part Number PSD913F2-70J PSD913F2-70M PSD913F2-90J PSD913F2-90M PSD913F2-90JI PSD913F2-90MI PSD934F2-70J PSD934F2-70M PSD934F2-90J PSD934F2-90M PSD934F2-90JI PSD934F2-90MI PSD954F2-70J PSD954F2-70M PSD954F2-90JI PSD954F2-90MI PSD913F2V-15J PSD913F2V-15M PSD913F2V-20JI PSD913F2V-20MI PSD934F2V-15J PSD934F2V-15M PSD934F2V-20JI PSD934F2V-20MI PSD954F2V-90J PSD954F2V-90M PSD954F2V-12JI PSD954F2V-12MI 88 Speed Temperature (ns) Package Type 70 52 Pin PLCC 70 ...
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... PSD913F2, PSD934F2, PSD954F2 REVISION HISTORY Table 1. Document Revision History Date Rev. Dec-1999 1.0 Document written in the WSI format Jun-2000 1.1 3V devices added Nov-2000 1.2 PSD954F2 added Front page, and back two pages format, added to the PDF file 04-Jan-2002 1.1 References to Waferscale, WSI, EasyFLASH and PSDsoft 2000 ...
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... All other names are the property of their respective owners STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © 2002 STMicroelectronics - All Rights Reserved www.st.com PSD913F2, PSD934F2, PSD954F2 3/3 ...