MC68HC11KW1 Freescale Semiconductor, Inc, MC68HC11KW1 Datasheet

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MC68HC11KW1

Manufacturer Part Number
MC68HC11KW1
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC11KW1/D
HC11
MC68HC11KW1
TECHNICAL
DATA
!MOTOROLA

Related parts for MC68HC11KW1

MC68HC11KW1 Summary of contents

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... HC11 MC68HC11KW1 TECHNICAL DATA MC68HC11KW1/D !MOTOROLA ...

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...

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... MC68HC11KW1 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & ...

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Conventions Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an ...

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... E clock output (E) ..................................................................................................2-4 2.5 XOUT.....................................................................................................................2-4 2.6 Interrupt request (IRQ) ..........................................................................................2-4 2.7 Nonmaskable interrupt (XIRQ) ..............................................................................2-5 2.8 MODA and MODB (MODA/LIR and MODB/VSTBY) .............................................2-5 2.9 VRH and VRL ........................................................................................................2-6 2.10 R/W........................................................................................................................2-6 2.11 Port signals ............................................................................................................2-6 2.11.1 Port A ...............................................................................................................2-6 2.11.2 Port B ...............................................................................................................2-8 2.11.3 Port C ...............................................................................................................2-8 2.11.4 Port D ...............................................................................................................2-8 2.11.5 Port E ...............................................................................................................2-9 2.11.6 Port F ...............................................................................................................2-9 2.11.7 Port G...............................................................................................................2-9 2.11.8 Port H ...............................................................................................................2-10 2.11.9 Port J................................................................................................................2-10 2.11.10 Port K ...............................................................................................................2-10 MC68HC11KW1 TABLE OF CONTENTS TITLE 1 INTRODUCTION 2 PIN DESCRIPTIONS Page Number TPG MOTOROLA i ...

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... Single chip operating mode .............................................................................4-1 4.1.2 Expanded operating mode...............................................................................4-1 4.1.3 Special test mode ............................................................................................4-2 4.1.4 Special bootstrap mode ...................................................................................4-2 4.2 On-chip memory....................................................................................................4-3 4.2.1 Mapping allocations .........................................................................................4-3 4.2.1.1 RAM ...........................................................................................................4-4 4.2.1.2 Bootloader ROM ........................................................................................4-4 4.2.2 Registers..........................................................................................................4-4 4.3 System initialization ...............................................................................................4-10 4.3.1 Mode selection.................................................................................................4-10 4.3.1.1 HPRIO — Highest priority I-bit interrupt & misc. register ...........................4-11 MOTOROLA TABLE OF CONTENTS ii TITLE 3 4 MC68HC11KW1 Page Number TPG ...

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... EEPROM .........................................................................................................4-41 4.6.1.1 PPROG — EEPROM programming control register ..................................4-41 4.6.1.2 EEPROM bulk erase ..................................................................................4-43 4.6.1.3 EEPROM row erase ...................................................................................4-43 4.6.1.4 EEPROM byte erase ..................................................................................4-44 4.6.2 CONFIG register programming ........................................................................4-44 4.6.3 RAM and EEPROM security ............................................................................4-45 RESETS AND INTERRUPTS 5.1 Resets ...................................................................................................................5-1 5.1.1 Power-on reset .................................................................................................5-1 5.1.2 External reset (RESET) ...................................................................................5-2 MC68HC11KW1 TABLE OF CONTENTS TITLE 5 Page Number TPG MOTOROLA iii ...

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... DDRA — Data direction register for port A ......................................................6-2 6.2 Port B.....................................................................................................................6-3 6.2.1 PORTB — Port B data register ........................................................................6-3 6.2.2 DDRB — Data direction register for port B ......................................................6-3 6.3 Port C ....................................................................................................................6-4 6.3.1 PORTC — Port C data register........................................................................6-4 6.3.2 DDRC — Data direction register for port C......................................................6-4 6.4 Port D ....................................................................................................................6-5 6.4.1 PORTD — Port D data register........................................................................6-5 MOTOROLA TABLE OF CONTENTS iv TITLE 6 MC68HC11KW1 Page Number TPG ...

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... SCCR1 — SCI control register 1 .....................................................................7-7 7.6.3 SCCR2 — SCI control register 2 .....................................................................7-9 7.6.4 SCSR1 — SCI status register 1.......................................................................7-10 7.6.5 SCSR2 — SCI status register 2.......................................................................7-11 7.6.6 SCDRH, SCDRL — SCI data high/low registers .............................................7-12 7.7 Status flags and interrupts.....................................................................................7-12 7.7.1 Receiver flags ..................................................................................................7-13 MC68HC11KW1 TABLE OF CONTENTS TITLE 7 Page Number TPG MOTOROLA v ...

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... Timer 2 ..................................................................................................................9-15 9.2.1 Output compare ...............................................................................................9-18 9.2.2 Input capture....................................................................................................9-18 9.2.3 F23FRC — Compare force register for Timers 2 and 3. ..................................9-18 9.2.4 T2C4 — Timer 2 channel 4 register.................................................................9-19 9.2.5 T2OC1–T2OC3 — Timer 2 output compare registers .....................................9-19 9.2.6 TCNT2 — Timer 2 counter register..................................................................9-20 MOTOROLA TABLE OF CONTENTS vi TITLE 8 9 TIMING SYSTEM Page Number TPG MC68HC11KW1 ...

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... PWPER1–4 — PWM timer period registers 1 to 4...........................................9-43 9.7.8 PWDTY1–4 — PWM timer duty cycle registers 1 to 4.....................................9-44 9.7.9 Boundary cases ...............................................................................................9-44 ANALOG-TO-DIGITAL CONVERTER 10.1 Conversion process .............................................................................................10-2 10.2 Channel assignments ..........................................................................................10-2 10.3 Single channel operation .....................................................................................10-3 10.3.1 4-conversion, single scan...............................................................................10-4 10.3.2 4-conversion, continuous scan.......................................................................10-4 10.3.3 8-conversion, single scan...............................................................................10-4 MC68HC11KW1 TABLE OF CONTENTS TITLE 10 Page Number TPG MOTOROLA vii ...

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... Analog-to-digital converter characteristics...................................................... A-10 A.5.3 Serial peripheral interface timing .................................................................... A-11 A.5.4 Non-multiplexed expansion bus timing ........................................................... A-14 A.6 EEPROM characteristics ...................................................................................... A-15 MECHANICAL DATA B.1 Packaging ............................................................................................................. B-1 DEVELOPMENT SYSTEMS C.1 EVS — Evaluation system.................................................................................... C-1 C.2 MMDS11 — Motorola modular development system ........................................... C-2 C.3 SPGMR11 — Serial peripheral system ................................................................ C-2 MOTOROLA TABLE OF CONTENTS viii TITLE MC68HC11KW1 Page Number TPG ...

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... MC68HC11KW1 100-pin TQFP..............................................................................2-1 2-2 External reset circuitry............................................................................................2-2 2-3 Oscillator connections ............................................................................................2-3 2-4 RAM stand-by connections.....................................................................................2-5 3-1 Programming model ...............................................................................................3-1 3-2 Stacking operations ................................................................................................3-3 4-1 MC68HC11KW1 memory map ...............................................................................4-3 4-2 RAM and register overlap.......................................................................................4-14 4-3 Memory map example of memory expansion.........................................................4-25 4-4 Schematic example of memory expansion .............................................................4-26 4-5 Memory map example of memory expansion.........................................................4-27 4-6 Schematic example of memory expansion .............................................................4-28 5-1 Processing fl ...

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... Port G control timing...............................................................................................A-8 A-9 Port write timing diagram........................................................................................A-9 A-10 SPI master timing (CPHA = 0) ...............................................................................A-12 A-11 SPI master timing (CPHA = 1) ...............................................................................A-12 A-12 SPI slave timing (CPHA = 0) ..................................................................................A-13 A-13 SPI slave timing (CPHA = 1) ..................................................................................A-13 A-14 Expansion bus timing .............................................................................................A-15 B-1 100-pin TQFP .........................................................................................................B-1 B-2 100-pin TQFP mechanical dimensions...................................................................B-2 MOTOROLA xii TITLE LIST OF FIGURES Page Number TPG MC68HC11KW1 ...

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... Highest priority interrupt selection ..........................................................................5-11 5-4 Interrupt and reset vector assignments ..................................................................5-12 5-5 Stacking order on entry to interrupts ......................................................................5-13 6-1 Port configuration ...................................................................................................6-1 7-1 Example SCI baud rate control values ...................................................................7-7 8-1 SPI clock rates........................................................................................................8-7 9-1 Timer 1 resolution and capacity..............................................................................9-3 9-2 RTI periodic rates ...................................................................................................9-31 9-3 Pulse accumulator timing .......................................................................................9-34 MC68HC11KW1 TITLE LIST OF TABLES Page Number TPG MOTOROLA xiii ...

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... Table Number 9-4 Clock A and clock B prescalers .............................................................................. 9-40 10-1 Channel assignments........................................................................................... 10-3 C-1 M68HC11 development tools ................................................................................ C-1 MOTOROLA xiv TITLE LIST OF TABLES Page Number TPG MC68HC11KW1 ...

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... INTRODUCTION The MC68HC11KW1 8-bit microcontroller is a member of the M68HC11 family of HCMOS microcontrollers. It has 640 bytes of EEPROM and 768 bytes of RAM. Making use of a 100-pin TQFP package, a non-multiplexed expanded bus is a feature of this device. The main timer system includes three input captures, four output compares and a software selectable input capture or output compare ...

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... Four 8-bit PWM timer channels • Available in 100-pin TQFP package 1.2 Mask option There is a single mask option on the MC68HC11KW1, which is programmed during manufacture and must be specified on the order form: • Security option (available/unavailable). See Section 4.6.3 MOTOROLA 1-2 INTRODUCTION ...

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... RESET mode LIR/MODA select VSTBY/MODB XTAL EXTAL Oscillator R/W E XOUT 3 VDD VSS 3 Non-multiplexed address and data buses Port B Figure 1-1 MC68HC11KW1 block diagram MC68HC11KW1 OC1/PAI Pulse accumulator OC1/OC2 OC1/OC3 Timer 2 Timer 1 OC1/OC4 IC4/OC1/OC5 IC1 Periodic interrupt IC2 COP watchdog IC3 SS Timer 3 SCK ...

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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 1-4 INTRODUCTION TPG MC68HC11KW1 ...

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... PIN DESCRIPTIONS The MC68HC11KW1 is available packaged in a 100-pin thin quad flat pack (TQFP), as shown in Figure 2-1. Most pins on this MCU serve two or more functions, as described in the following paragraphs. PK4/OC1 1 PK3/ECIN 2 PK2 3 PK1 4 PK0 5 PH0/PWM1 6 PH1/PWM2 7 PH2/PWM3 8 PH3/PWM4 9 PH4/CSIO 10 PH5/CSGP1 11 PH6/CSGP2 12 PH7/CSPROG 13 R/W 14 ...

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... Figure 2-2 illustrates a typical reset circuit that includes an external switch together with a low voltage inhibit circuit, to prevent power transitions, or RAM or EEPROM corruption. Manual reset 4.7 k MOTOROLA 2 RESET MC34064 GND 4 µ RESET MC34164 GND 3 Figure 2-2 External reset circuitry PIN DESCRIPTIONS 4 M68HC11 RESET TPG MC68HC11KW1 ...

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... Common crystal M68HC11 connections EXTAL (b) External oscillator M68HC11 connections EXTAL M68HC11 10 M crystal XTAL (c) One crystal driving two MCUs Figure 2-3 Oscillator connections MC68HC11KW1 EXTAL 4• crystal XTAL External oscillator XTAL 220 4• Note: capacitor values include all stray capacitance. ...

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... Bypassing requirements vary, depending on how heavily the MCU pins are loaded. The MC68HC11KW1 has four VDD pins and four VSS pins. One pair of these pins is reserved for supplying power to the analog-to-digital converter (VDDAD, VSSAD); the remaining pins are used for the internal logic, and to supply power to the port logic on either half of the chip ...

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... VDD power applied to the MCU. Reset must be driven low before V remain low until V has been restored to a valid level 4.8 V NiCd Figure 2-4 RAM stand-by connections MC68HC11KW1 and V is greater than one MOS threshold STBY DD rather than V . This allows RAM contents to be retained DD 4 ...

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... Port signals The MC68HC11KW1 includes 80 pins that are arranged into ten 8-bit ports ( and K). All the port pins are bidirectional, except for PG7, PG6 and port E pins [7:0]; these are input only. Most of the bidirectional ports serve a purpose other than I/O, depending on the operating mode or peripheral function selected ...

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... PH6 PH5 PH4 PH[3:0] PJ7 PJ6 PJ5 PJ4 PJ3 PJ[2,0] PK7 PK6 PK5 PK4 PK3 PK[2,0] MC68HC11KW1 Expanded multiplexed and special test mode PA7/PAI and/or OC1 PA6/OC2 and/or OC1 PA5/OC3 and/or OC1 PA4/OC4 and/or OC1 PA3/OC5/IC4 and/or OC1 PA2/IC1 PA1/IC2 PA0/IC3 PB[7:0] ADDR[15:8] PC[7:0] DATA[7:0] PD[7, 6] PD5/SS ...

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... PORTD can be read at any time; inputs return the pin level and outputs return the pin driver input level. If PORTD is written, the data is stored in internal latches. The pins are driven only if port D is configured for general purpose output. MOTOROLA 2-8 PIN DESCRIPTIONS TPG MC68HC11KW1 ...

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... PORTG can be read at any time and always returns the pin level. If PORTG is written, the data is stored into an internal latch. The pin is driven only configured as an output. Pins [5:0] have on-chip pull-up devices that can be enabled or disabled via the port pull-up assignment register (PPAR). Refer to Section 6, Section 10 (A/D) and Section 4. MC68HC11KW1 PIN DESCRIPTIONS 2 TPG ...

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... Out of reset, port K pins [7:0] are general purpose high-impedance inputs. When the functions associated with these pins are disabled, the bits in DDRK govern the I/O state of the associated pin. For further information, refer to Section 6 and Section 9 (Timing system). MOTOROLA 2-10 PIN DESCRIPTIONS TPG MC68HC11KW1 ...

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... M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers are shown in Figure 3-1 and are discussed in the following paragraphs. 7 Accumulator Condition code register Figure 3-1 Programming model MC68HC11KW1 CENTRAL PROCESSING UNIT Accumulator B 0 A:B Double accumulator Index register X ...

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... SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free location in the stack. Figure 3 summary of SP operations. MOTOROLA 3-2 CENTRAL PROCESSING UNIT TPG MC68HC11KW1 ...

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... High order byte of 16-bit extended address ll Low order byte of 16-bit extended address rr Signed relative offset ($80 to $7F (–128 to +127)); offset is relative to the address following the offset byte Figure 3-2 Stacking operations MC68HC11KW1 CENTRAL PROCESSING UNIT BSR, Branch to subroutine Main program PC ...

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... Refer to Table 3-2, which shows the condition codes that are affected by a particular instruction. MOTOROLA 3-4 Table 3-1 Reset vector comparison POR or RESET pin Clock monitor $FFFE, $FFFF $FFFC, $FFFD $BFFE, $BFFF $BFFE, $BFFF CENTRAL PROCESSING UNIT COP watchdog $FFFA, $FFFB $BFFE, $BFFF TPG MC68HC11KW1 ...

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... Normally, the I-bit is zero after a return from interrupt is executed. Although the I-bit can be cleared within an interrupt service routine, ‘nesting’ interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. Refer to Section 5. MC68HC11KW1 CENTRAL PROCESSING UNIT 3 TPG ...

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... A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. MOTOROLA 3-6 CENTRAL PROCESSING UNIT TPG MC68HC11KW1 ...

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... In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses. MC68HC11KW1 CENTRAL PROCESSING UNIT 3 TPG ...

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... Instruction set Refer to Table 3-2, which shows all the M68HC11 instructions in all possible addressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E clock cycles. MOTOROLA 3-8 CENTRAL PROCESSING UNIT TPG MC68HC11KW1 ...

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... Clear bit(s) M • (MM) (msk) BCS (rel) Branch if carry set BEQ (rel) Branch if equal to zero BGE (rel) Branch if zero N BGT (rel) Branch if > zero BHI (rel) Branch if higher MC68HC11KW1 CENTRAL PROCESSING UNIT Instruction Addressing mode Opcode Operand A INH 1B — IX INH 3A — IY ...

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... TPG MC68HC11KW1 ...

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... INX Increment index register INY Increment index register JMP (opr) Jump see Figure 3-2 JSR (opr) Jump to subroutine see Figure 3-2 LDAA (opr) Load accumulator A MC68HC11KW1 CENTRAL PROCESSING UNIT Instruction Addressing mode Opcode Operand IMM DIR EXT ...

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... TPG MC68HC11KW1 ...

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... Store accumulator B STD (opr) Store accumulator D A STOP Stop internal clocks STS (opr) Store stack pointer SP STX (opr) Store index register X IX STY (opr) Store index register Y IY MC68HC11KW1 CENTRAL PROCESSING UNIT Instruction Addressing mode Opcode Operand A A INH 32 — INH 33 — ...

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... TPG MC68HC11KW1 ...

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... ROM. Test is a special expanded mode that allows privileged access to internal resources. 4.1.1 Single chip operating mode In single chip operating mode, the MC68HC11KW1 microcontroller has no external address or data bus. Ports B, C and F are available for general-purpose parallel I/O. 4.1.2 Expanded operating mode In expanded operating mode, the MCU can access a 64K byte physical address space. The address space includes the same on-chip memory addresses used for single chip mode, in addition to external memory and peripheral devices ...

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... In bootstrap mode, the interrupt vectors point to RAM. This allows the use of interrupts through a jump table. Further baud rate options are available on the MC68HC11KW1 by using a different value for the synchronization byte, as shown in Table 4-1. Refer also to Motorola application note AN1060, M68HC11 Bootstrap Mode (the bootloader mode is similar to that used on the MC68HC11K4) ...

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... On-chip memory The MC68HC11KW1 MCU includes 768 bytes of on-chip RAM and 640 bytes of EEPROM. The bootloader ROM occupies a 448 byte block of the memory map. The CONFIG register is implemented as a separate EEPROM byte. Start address $0000 $00A0 $03A0 $0D80 $1000 $BE40 $C000 $FFC0 — ...

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... RAM The MC68HC11KW1 has 768 bytes of fully static RAM that are used for storing instructions, variables and temporary data during program execution. RAM can be placed at any 4K boundary in the 64K byte address space by writing an appropriate value to the INIT register. ...

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... Capture 4/compare 5 (TI4/O5) low $001F Timer control 1 (TCTL1) $0020 Timer control 2 (TCTL2) $0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000 Timer interrupt mask 1 (TMSK1) $0022 MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 6 bit 5 bit 4 bit 3 bit 2 PA7 PA6 ...

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... ADER 0000 0000 0000 0000 CR1 CR0 0001 0000 (2) (1) (bit 0) undefined EEPG 0000 0000 M FCM FCOP 0 0000 x000 NOCO 1 EEON 11xx xx1x P (10) (9) (8) undefined uu00 0000 (10) (9) (8) undefined uu00 0000 TPG MC68HC11KW1 ...

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... Pulse width polarity select (PWPOL) $0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000 Pulse width scale (PWSCAL) $0062 Pulse width enable (PWEN) $0063 TPWSL DISCP Pulse width count 1 (PWCNT1) $0064 MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 6 bit 5 bit 4 bit 3 bit 2 (14) ...

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... R1T1 R0T0 undefined PH2 PH1 PH0 undefined PG2 PG1 PG0 undefined OL3 OM4 OL4 0000 0000 (10) (9) (bit 8) 0000 0000 (2) (1) (bit 0) 0000 0000 (10) (9) (bit 8) 1111 1111 (2) (1) (bit 0) 1111 1111 (10) (9) (bit 8) 1111 1111 TPG MC68HC11KW1 ...

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... Timer 3 mask (T3MSK) $009C Timer 3 flag (T3FLG) $009D OC1F OC2F OC3F Port K data (PORTK) $009E Data direction K (DDRK) $009F KEY x State on reset depends on mode selected u State of bit on reset is undefined MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 6 bit 5 bit 4 bit 3 bit 2 (bit 7) (6) (5) (4) ...

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... RAM contents to be maintained in the absence MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-10 Register Must be written in name first 64 cycles through a pull-up resistor of 4 The MODA pin also functions as Write once only (1) — (2) — No Yes (3) No (4) — (5) — (6) No (6) No TPG MC68HC11KW1 ...

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... MODB MODA 1 0 Single chip 1 1 Expanded 0 0 Special bootstrap 0 1 Special test PSEL[4:0] — Priority select bits (refer to Section 5) MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Control bits in HPRIO (latched at reset) Mode RBOOT SMOD MDA 0 ...

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... Pull-ups can be enabled using PPAR. 0 (clear) – All pull-ups disabled (not controlled by PPAR). MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-12 Address bit 7 bit 6 bit 5 bit 4 bit 3 $003F 1 1 CLKX PAREN NOSEC State bit 2 bit 1 bit 0 on reset NOCO 1 EEON 11xx xx1x P TPG MC68HC11KW1 ...

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... REG[3:0] — 160-byte register block position These four bits specify the upper hexadecimal digit of the address for the 160-byte block of internal registers. The register block is positioned at the beginning of any 4K page in the memory map. Refer to Table 4-5. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 ...

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... RAM A Register block $x09F $x0A0 RAM B RAM B $x2FF $x300 RAM A $x39F Register and RAM mapped to the same 4K boundary. Figure 4-2 RAM and register overlap TPG MC68HC11KW1 ...

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... The time protected control bits IRQE, DLY, FCME and CR[1:0] can be written only once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the possibility of any accidental changes to the system configuration. They may be written at any time in special modes. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 ...

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... Clock monitor enabled; cannot be disabled until next reset. 0 (clear) – Clock monitor follows the state of the CME bit. When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize STOP mode, FCME should always be cleared. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-16 TPG MC68HC11KW1 ...

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... In single chip modes this bit determines whether the E clock drives out from the chip. 1 (set) – E pin is driven low. 0 (clear) – E clock is driven out from the chip. Refer to the following table for a summary of the operation immediately following reset. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 bit 4 bit 3 ...

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... XCLK with EXTAL = 16 MHz MHz MHz 0 6 2.7 MHz MHz Address bit 7 bit 6 bit 5 bit 4 bit 3 $0035 BULKP BIT6 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1111 1111 IRVNE can be written Once Once Unlimited Unlimited State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

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... Each of these five bits protects a block of EEPROM against writing or erasure, as follows: Table 4-8 EEPROM block protect Bit name BPRT0 BPRT1 BPRT2 BPRT3 BPRT4 MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Block Block size protected $xD80–$xD9F 32 bytes $xDA0–$xDDF 64 bytes $xDE0–$xE5F 128 bytes $xE60– ...

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... Refer to the following table: MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-20 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0024 TOI RTII PAOVI PAII 0 PR[1:0] Prescale factor State bit 2 bit 1 bit 0 on reset 0 PR1 PR0 0000 0000 TPG MC68HC11KW1 ...

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... These bits are used to select the prescaler divide-by ratio for Timer 3. They can only be written to once after reset. If PR3B and PR3A are both cleared, then Timer 3 is synchronized to the prescaled Timer 1 rate. PR3B MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 ...

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... Memory expansion logic The MC68HC11KW1 has the ability to extend the address range of the M68HC11 CPU beyond the physical 64K byte limit of the 16 CPU address lines. The extra addressing capability is provided by a register-based paging scheme using expansion address lines and the physical 64K bytes of CPU address space. Two additional on-chip blocks are provided with the MC68HC11KW1. The fi ...

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... ADDR14 must be inverted to allow 32K bytes of contiguous memory. The MC68HC11KW1 CPU drives the inverted CPU ADDR14 signal onto the XA14 pin when the window is active. In this case, the XA14 signal must be connected to the address line 14 of the memory device. ...

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... OPERATING MODES AND ON-CHIP MEMORY 4-24 Window size 16K bytes 32K bytes 32K bytes (window based at $4000) ADDR[13:0] ADDR[14:0] XA14 XA15 ADDR[13:0] ADDR[14:0] XA[15:14] XA[16:15] ADDR[13:0] ADDR[14:0] XA[16:14] XA[17:15] ADDR[13:0] ADDR[14:0] XA[17:14] XA[18:15] ADDR[13:0] — XA[18:14] — — — — — ADDR[13:0] XA[15:14] ADDR[13:0] XA[16:14] ADDR[13:0] XA[17:14] ADDR[13:0] XA[18:14] — — — — TPG MC68HC11KW1 ...

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... Chip select 1 XA[15:13] $6000 MMWBR = $04 MMSIZ = $42 $FFC0 Vectors $FFFF CSCTL = $00 GPCS1A = $00 GPSC1C = $06 GPCS2A = $00 GPCS2C = $00 Figure 4-3 Memory map example of memory expansion MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Window 1 $00000 $02000 $04000 $06000 $08000 $0A000 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 XA[15:13] XA[15:13] XA[15:13] XA[15:13] XA[15:13] ...

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... A15 XA14 XA17 A14 XA13 XA16 A13 ADDR12 A12 XA15 ADDR11 A11 XA14 ADDR10 A10 XA13 ADDR9 A9 ADDR8 A8 ADDR7 A7 ADDR6 A6 ADDR5 A5 ADDR4 A4 ADDR3 A3 ADDR2 A2 ADDR1 A1 ADDR0 27C512 VCC OE CE VSS DATA7 D7 DATA6 D6 DATA5 D5 DATA4 D4 DATA3 D3 DATA2 D2 DATA1 D1 DATA0 D0 TPG MC68HC11KW1 ...

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... PGAR = $1F XA[17:13] MMWBR = $84 window 1 @ $4000, window 2 @ $8000 MMSIZ = $42 window bytes, window 2 = 16K bytes Figure 4-5 Memory map example of memory expansion MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Window 1 $00000 $02000 $04000 $06000 $08000 $0A000 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 ...

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... DATA7 D7 DATA6 D6 DATA5 D5 DATA4 D4 DATA3 D3 DATA2 D2 DATA1 D1 DATA0 6226 (High DATA7 D7 DATA6 D6 DATA5 D5 DATA4 D4 DATA3 D3 DATA2 D2 DATA1 D1 DATA0 6226 (Low DATA7 D7 DATA6 D6 DATA5 D5 DATA4 D4 DATA3 D3 DATA2 D2 DATA1 D1 DATA0 D0 TPG MC68HC11KW1 ...

Page 73

... Window disabled – window can have byte banks 1 0 16K – window can have 16K byte banks 1 1 32K – window can have 32K byte banks MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 bit 4 bit 3 ...

Page 74

... State bit 2 bit 1 bit 0 on reset 0 0000 0000 TPG MC68HC11KW1 ...

Page 75

... On-chip registers, RAM, and EEPROM have higher priority than expansion windows window overlaps RAM, registers or EEPROM, they appear in all banks at their CPU address. – Window 1 has a higher priority than window 2, therefore any overlapped portion of window 2 is inaccessible. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 ...

Page 76

... CSCTL register. When an MCU pin is not used for chip select functions, it can be used for general-purpose I/O. The MC68HC11KW1 has four software configured chip selects that are enabled in expanded modes. The chip select for I/O (CSIO) is used for I/O expansion. The program chip select (CSPROG) is used with an external memory that contains the reset vectors and program ...

Page 77

... Polarity of the active state is programmable for active high or active low. Clock stretching can be set from zero to three cycles. Refer to Section 4.5.4 for descriptions of bits IOEN, IOPL, IOCSA, and IOSZ. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY GCSPR = 1 ...

Page 78

... IOPL IOCSA IOSZ GCSPR PCSEN PCSZA PCSZB 0000 0100 Table 4-13 Program chip select size PCSZA PCSZB Size (bytes) Address range 0 0 64K $0000 – $FFFF 0 1 32K $8000 – $FFFF 1 0 16K $C000 – $FFFF $E000 – $FFFF State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 79

... G1A18 G1A17 G1A16 G1A15 G1A14 G1A13 G1A12 G1A11 0000 0000 Gen. purpose chip select 1 addr. (GPCS1A) G1A[18:11] — General-purpose chip select 1 address These bits select the starting address of general-purpose chip select 1 range. Refer to Table 4-15. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Condition Priority ...

Page 80

... These bits select the size for general-purpose chip select 1. Refer to Table 4-15. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-36 Address bit 7 bit 6 bit 5 bit 4 bit 3 $005D G1DG2 G1DPC G1POL G1AV G1SZA G1SZB G1SZC G1SZD 0000 0000 State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 81

... G2DPC — General-purpose chip select 2 drives program chip select 1 (set) – CSGP2 and CSPROG are OR'ed and driven out the CSPROG pin. 0 (clear) – Does not affect program chip select. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Valid bits Size (bytes) (MXGS1 = 0) (MXGS1 = 1) ...

Page 82

... None 1 1 128K None 0 0 256K None 0 1 512K None 1 0 Follow Window 1 None 1 1 Follow Window 2 None Default to 512K None Valid bits (MXGS2 = 1) None G2A[18:11] G2A[18:12] G2A[18:13] G2A[18:14] G2A[18:15] G2A[18:16] G2A[18:17] G2A18 None None None None TPG MC68HC11KW1 ...

Page 83

... GP2SA, GP2SB — CSGP2 stretch select PCSA, PCSB — CSPROG stretch select In normal modes (SMOD = 0), PCSB is set on reset to give a one cycle stretch. In special modes (SMOD = 1), PCSB is cleared on reset. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY General 2 CS pin asserted when address is in: ...

Page 84

... OR'ed and driven out the CSPROG pin. G2DPC in GPCS2C allows CSGP2 and CSPROG to be logically OR'ed and driven out the CSPROG pin. MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses or 512K expansion addresses. MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses or 512K expansion addresses. TPG MC68HC11KW1 ...

Page 85

... If both ODD and EVEN are set to one then all odd and even rows in half of the EEPROM will be programmed with the same data, within one programming cycle. BYTE — EEPROM byte erase mode 1 (set) – Erase only one byte of EEPROM. 0 (clear) – Row or bulk erase mode used. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY 4.3.2.6). bit 7 bit 6 bit 5 bit 4 bit 3 ...

Page 86

... EEPROM must be erased by a separate erase operation before programming. The following MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-42 Table 4-19 Erase mode selection Byte Row Action 0 0 Bulk erase (all 640 bytes Row erase (16 bytes Byte erase 1 1 Byte erase TPG MC68HC11KW1 ...

Page 87

... CLR $003B Turn off high voltage and set to READ mode 4.6.1.3 EEPROM row erase The following example shows how to perform a fast erase of 16 bytes of EEPROM: ROWE LDAB #$0E ROW=ERASE=EELAT=1 STAB $003B Set to ROW erase mode MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY 4 TPG MOTOROLA 4-43 ...

Page 88

... Write any data to address to be erased BYTE=ERASE=EELAT=EEPGM=1 Turn on high voltage Delay tEEPROG Turn off high voltage and set to READ mode Address bit 7 bit 6 bit 5 bit 4 $003F 1 1 CLKX PAREN NOSEC State bit 3 bit 2 bit 1 bit 0 on reset NOCO 1 EEON 11xx xx1x P TPG MC68HC11KW1 ...

Page 89

... Note: A mask option on the MC68HC11KW1 determines whether or not the security feature is made available. If the feature is available, then the secure mode can be invoked by programming the NOSEC bit to zero. Otherwise, the NOSEC bit is permanently set to one, disabling security ...

Page 90

... If the MODA and MODB pins are configured for special test mode, the part will start in bootstrap mode. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-46 Address bit 7 bit 6 bit 5 bit 4 bit 3 $003F 1 1 CLKX PAREN NOSEC State bit 2 bit 1 bit 0 on reset NOCO 1 EEON 11xx xx1x P TPG MC68HC11KW1 ...

Page 91

... RESET pin low whenever V voltage level detector, or other external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internal circuitry during power on. Refer to Figure 2-3. MC68HC11KW1 RESETS AND INTERRUPTS 5 is below the minimum operating level. This external ...

Page 92

... For example, with MHz, the uncertainty is –0/+8.192 ms. See also the M68HC11 Reference Manual, (M68HC11RM/AD). MOTOROLA 5-2 15 and then further scaled by the factor shown in Table 5-1 COP timer rate select 15 by EXTAL = 16 MHz: timeout 1 8.192 ms 4 32.768 ms 16 131.072 ms 64 524.288 MHz RESETS AND INTERRUPTS (1) 15 TPG MC68HC11KW1 ...

Page 93

... STOP mode was initiated. Before executing a STOP instruction, clear the CME bit in the OPTION register to zero to disable the clock monitor. After recovery from STOP, set the CME bit to logic one to enable the clock monitor. MC68HC11KW1 RESETS AND INTERRUPTS bit 7 ...

Page 94

... CME — Clock monitor enable 1 (set) – Clock monitor enabled. 0 (clear) – Clock monitor disabled. MOTOROLA 5-4 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0039 ADPU CSEL IRQE DLY CME FCME RESETS AND INTERRUPTS State bit 2 bit 1 bit 0 on reset CR1 CR0 0001 0000 TPG MC68HC11KW1 ...

Page 95

... SMOD = 0 (single chip or expanded mode), these bits can only be written using the EEPROM programming sequence, and none of the bits are readable or active until latched via the next reset. Bits [ — Not implemented; always read one. MC68HC11KW1 RESETS AND INTERRUPTS 15 before it enters the COP watchdog system. These control ...

Page 96

... These initial states then control on-chip peripheral systems to force them to known start-up states, as described in the following paragraphs. MOTOROLA 5-6 Normal mode Special test or bootstrap vector $FFFE, $FFFF $BFFE, $BFFF $FFFC, $FFFD $BFFC, $BFFD $FFFA, $FFFB $BFFA, $BFFB RESETS AND INTERRUPTS TPG MC68HC11KW1 ...

Page 97

... All nine timer interrupts are disabled because their mask bits have been cleared. The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin. MC68HC11KW1 RESETS AND INTERRUPTS 5 TPG ...

Page 98

... The TDRE and TC status bits in the SCI status register are both set, indicating that there is no transmit data in either the transmit data register or the transmit serial shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits are cleared. MOTOROLA 5-8 RESETS AND INTERRUPTS TPG MC68HC11KW1 ...

Page 99

... Illegal opcode interrupt — see Section 5.4.3 for details of handling – Software interrupt (SWI) — see Section 5.4.4 for details of handling The maskable interrupt sources have the following priority arrangement: 5) IRQ 6) Real-time interrupt 7) Timer 1 input capture 1 MC68HC11KW1 RESETS AND INTERRUPTS 5 TPG MOTOROLA 5-9 ...

Page 100

... Bootloader ROM enabled, at $BE40–$BFFF. 0 (clear) – Bootloader ROM disabled and not in map. MOTOROLA 5-10 Address bit 7 bit 6 bit 5 bit 4 bit 3 $003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110 RESETS AND INTERRUPTS State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 101

... X MC68HC11KW1 RESETS AND INTERRUPTS Interrupt source promoted 0 X Reserved (default to IRQ) 0 Reserved (default to IRQ) 1 Reserved (default to IRQ) 0 IRQ (external pin) 1 Real-time interrupt 0 Timer 1 input capture 1 1 Timer 1 input capture 2 0 Timer 1 input capture 3 1 Timer 1 output compare 1 ...

Page 102

... RESETS AND INTERRUPTS Local mask — TO3I C4I OC1I OC2I OC3I TO2I C4I OC1I OC2I OC3I RIE RIE TIE TCIE ILIE SPIE PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII None None None None NOCO P CME None TPG MC68HC11KW1 ...

Page 103

... Interrupts Excluding reset type interrupts, the MC68HC11KW1 has 23 interrupt vectors that support 32 interrupt sources. The 20 maskable interrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) is clear. The three nonmaskable interrupt sources are illegal opcode trap, software interrupt, and XIRQ pin ...

Page 104

... SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhibited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit, once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or until user software clears the I bit in the CCR. MOTOROLA 5-14 RESETS AND INTERRUPTS TPG MC68HC11KW1 ...

Page 105

... NOCOP being set. Timers 2 and 3 can be stopped under the control of bits in the TCTL4 and TCTL6 registers, respectively. Several other systems can also reduced power consumption state depending on the state of software-controlled configuration control bits. Power consumption by the analog-to-digital (A/D) converter is not affected significantly by the WAIT condition. MC68HC11KW1 RESETS AND INTERRUPTS 5 TPG ...

Page 106

... This same delay also applies to power-on-reset, regardless of the state of the DLY control bit, but does not apply to a reset while the clocks are running. See Section 4.3.2.4. MOTOROLA 5- are supplied then the interval worst case current consumption power is maintained. The CPU state and I/O pin DD RESETS AND INTERRUPTS TPG MC68HC11KW1 ...

Page 107

... Delay (4064 cycles) Load program counter with contents of $FFFE, $FFFF (vector fetch) 1A Yes Figure 5-1 Processing flow out of reset ( MC68HC11KW1 RESETS AND INTERRUPTS Priority Clock monitor fail (CME = 1) COP watchdog (NOCOP = 0) Load program counter Load program counter with contents of with contents of ...

Page 108

... Legal No opcode? Yes Yes Stack WAI? CPU registers No Interrupt Yes SWI? No Yes Yes RTI? Set I-bit No Resolve interrupt Execute this priority and fetch vector instruction for highest pending source (Figure 5-3) Start next instruction 1A sequence RESETS AND INTERRUPTS No yet? TPG MC68HC11KW1 ...

Page 109

... Yes IC1I = 1? No Yes IC2I = 1? No Yes IC3I = 1? No Yes OC1I = Figure 5-3 Interrupt priority resolution ( MC68HC11KW1 RESETS AND INTERRUPTS Set X-bit in CCR. XIRQ pin Yes Fetch vector at low? $FFF4, $FFF5 No Fetch vector Fetch vector at $FFF2, $FFF3 Yes Fetch vector at ...

Page 110

... Yes Yes TO2F = 1? No RESETS AND INTERRUPTS 2B Fetch vector at $FFE6, $FFE7 Fetch vector at $FFE4, $FFE5 Fetch vector at $FFE2, $FFE3 Fetch vector at $FFE0, $FFE1 Fetch vector at $FFD4, $FFD5 Fetch vector at $FFD2, $FFD3 Fetch vector at $FFDE, $FFDF Fetch vector at $FFD0, $FFD1 2D TPG MC68HC11KW1 ...

Page 111

... No Spurious interrupt — take IRQ vector † Flag polling is required to determine the source of this interrupt (refer to Section 9). ‡ Refer to Figure 5-6 for further details on SCI interrupts. Figure 5-5 Interrupt priority resolution ( MC68HC11KW1 RESETS AND INTERRUPTS Yes Fetch vector at PAOVF = 1? $FFDC, $FFDD ...

Page 112

... No No valid SCI interrupt request Figure 5-6 Interrupt source resolution within the SCI subsystem MOTOROLA 5-22 Yes RIE = Yes TIE = Yes TCIE = 1? No Yes ILIE = RESETS AND INTERRUPTS Yes Yes Yes Valid SCI interrupt request TPG MC68HC11KW1 ...

Page 113

... PARALLEL INPUT/OUTPUT The MC68HC11KW1 has input/output lines and 10 input-only lines, depending on the operating mode. To enhance the I/O functions, the data bus of this microcontroller is non-multiplexed. The following table is a summary of the configuration and features of each port. Table 6-1 Port configuration Input ...

Page 114

... PA5 PA4 PA3 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000 PARALLEL INPUT/OUTPUT State bit 2 bit 1 bit 0 on reset PA2 PA1 PA0 undefined State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 115

... Data direction B (DDRB) $0002 DDB[7:0] — Data direction for port B 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 PARALLEL INPUT/OUTPUT Alternative function ADDR8 ADDR9 In expanded or test mode, the pins ...

Page 116

... PC5 PC4 PC3 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000 PARALLEL INPUT/OUTPUT State bit 2 bit 1 bit 0 on reset PC2 PC1 PC0 undefined State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 117

... Data direction D (DDRD) $0009 DDD[7:0] — Data direction for port D 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 PARALLEL INPUT/OUTPUT Alternative function RXD See Section 7 for TXD more information. ...

Page 118

... AN5 See Section 10 for more information. PE4 AN6 PE5 AN7 PE6 AN8 PE7 AN9 Address bit 7 bit 6 bit 5 bit 4 bit 3 $000A PE7 PE6 PE5 PE4 PE3 PARALLEL INPUT/OUTPUT State bit 2 bit 1 bit 0 on reset PE2 PE1 PE0 undefined TPG MC68HC11KW1 ...

Page 119

... Data direction F (DDRF) $0003 DDF[7:0] — Data direction for port F 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 PARALLEL INPUT/OUTPUT Alternative function ADDR0 ADDR1 In expanded or test mode, the pins ...

Page 120

... See Section 4 for XA15 more information. XA16 XA17 XA18 See Section 10 for AN0 more information. AN1 Address bit 7 bit 6 bit 5 bit 4 bit 3 $007E PG7 PG6 PG5 PG4 PG3 PARALLEL INPUT/OUTPUT State bit 2 bit 1 bit 0 on reset PG2 PG1 PG0 undefined TPG MC68HC11KW1 ...

Page 121

... This allows unused lines to serve as general-purpose I/O. For more information, refer to Section 4.4. Bits [7:6] — Not implemented; always read zero PGAR[5:0] — Port G pin assignment 1 (set) – Corresponding port G pin is expansion address line (XA[18:13]). 0 (clear) – Corresponding port G pin is general-purpose I/O. MC68HC11KW1 PARALLEL INPUT/OUTPUT bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 0 ...

Page 122

... PH5 PH4 PH3 Address bit 7 bit 6 bit 5 bit 4 bit 3 $007D DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 0000 0000 PARALLEL INPUT/OUTPUT State bit 2 bit 1 bit 0 on reset PH2 PH1 PH0 undefined State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 123

... Data direction J (DDRJ) $008F DDJ[7:0] — Data direction for port J 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 PARALLEL INPUT/OUTPUT C4 OC3 See Section 9 for OC2 more information. OC1 ECIN ...

Page 124

... PK4 PK3 Address bit 7 bit 6 bit 5 bit 4 $009F DDK7 DDK6 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 0000 0000 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset PK2 PK1 PK0 undefined State bit 3 bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 125

... I/O and set as high impedance inputs). Note: The pull-up resistors are disabled when the PAREN bit in the CONFIG register is equal to ‘0’. The approximate value of these resistors is 14–17Kohms. MC68HC11KW1 PARALLEL INPUT/OUTPUT bit 7 bit 6 bit 5 ...

Page 126

... These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if enabled by the CLKX bit in CONFIG. MOTOROLA 6-14 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0038 LIRDV CWOM 0 IRVNE LSBF SPR2 XDV1 XDV0 000x 0000 PARALLEL INPUT/OUTPUT State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 127

... COP system disabled. 0 (clear) – COP system enabled (forces reset on timeout). EEON — EEPROM enable (refer to Section 4) 1 (set) – EEPROM is present in the memory map. 0 (clear) – EEPROM is disabled from the memory map. MC68HC11KW1 PARALLEL INPUT/OUTPUT bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 NOCO ...

Page 128

... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 6-16 PARALLEL INPUT/OUTPUT TPG MC68HC11KW1 ...

Page 129

... A block diagram of the enhanced baud rate generator is shown in Figure 7-1. See Table 7-1 for example baud rate control values. EXTAL 13-bit counter Reset EQ 13-bit compare SCBDH/L: SCI baud control Figure 7-1 SCI baud rate generator circuit diagram MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE 7 Alternative Pin function PD0 RXD PD1 ...

Page 130

... An advanced data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and majority sampling logic determines the value and integrity of each bit. MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-2 TPG MC68HC11KW1 ...

Page 131

... WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK SCSR1 OR RIE RDRF RIE TDRE TIE Figure 7-2 SCI block diagram MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE SCDRH/SCDRL T8 (transmit buffer) 10/11-bit TX shift register LOOPS EXTAL M PE Transmitter PT control TE SBK Flag control WAKE ...

Page 132

... When a receiver finds that the message is not intended for it, it sets the RWU bit. Once set, the RWU control bit disables all but the necessary receivers for the remainder of the message, thus reducing software overhead MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-4 TPG MC68HC11KW1 ...

Page 133

... SCI. If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if 9-bit data format is used, the upper register should be written first to ensure that it is transferred to the transmitter shift register with the lower register. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE 7 ...

Page 134

... Address bit 7 bit 6 bit 5 bit 4 bit 3 $0070 BTST BSPL SYNC SBR12 SBR11 SBR10 SBR9 SBR8 0000 0000 $0071 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0000 0100 EXTAL SCI baud rate = ----------------------------- - 16 2BR State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 135

... Bit 5 — Not implemented; always reads zero M — Mode (select character format) 1 (set) – Start bit, 9 data bits, 1 stop bit. 0 (clear) – Start bit, 8 data bits, 1 stop bit. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE EXTAL frequency: 16 MHz Dec value Hex value 4545 $11C1 ...

Page 136

... Parity odd (an odd number of ones causes parity bit to be zero, an even number of ones causes parity bit to be one). 0 (clear) – Parity even (an even number of ones causes parity bit to be zero, an odd number of ones causes parity bit to be one). MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-8 TPG MC68HC11KW1 ...

Page 137

... Wake-up enabled and receiver interrupts inhibited. 0 (clear) – Normal SCI receiver. SBK — Send break 1 (set) – Break codes generated as long as SBK is set. 0 (clear) – Break generator off. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 TIE TCIE ...

Page 138

... The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1 with IDLE set and then reading SCDR. MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-10 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0074 TDRE TC RDRF IDLE OR State bit 2 bit 1 bit 0 on reset 1100 0000 TPG MC68HC11KW1 ...

Page 139

... In the SCSR2 only bit 0 is used, to indicate receiver active. The other seven bits always read zero. Bits [7:1] — Not implemented; always read zero RAF — Receiver active flag (read only) 1 (set) – A character is being received. 0 (clear) – A character is not being received. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 ...

Page 140

... When TIE and TDRE are one, an interrupt is requested. MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-12 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0076 $0077 R7T7 R6T6 R5T5 R4T4 R3T3 State bit 2 bit 1 bit 0 on reset undefined R2T2 R1T1 R0T0 undefined TPG MC68HC11KW1 ...

Page 141

... The last receiver status flag and interrupt source come from the IDLE flag. The RXD line is idle if it has constantly been at logic one for a full character time. The IDLE flag is set only after the RXD line has been busy and becomes idle. This prevents repeated interrupts for the time RXD remains idle. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE 7 ...

Page 142

... Yes IDLE = valid SCI interrupt request Figure 7-3 Interrupt source resolution within SCI MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-14 Yes Yes RIE = Yes Yes TIE = Yes TCIE = 1? No Yes Yes ILIE = Valid SCI interrupt request TPG MC68HC11KW1 ...

Page 143

... The SPI status block represents the SPI status functions (transfer complete, write collision, and mode fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those functions that control the SPI system through the serial peripheral control register (SPCR). MC68HC11KW1 SERIAL PERIPHERAL INTERFACE 8 ...

Page 144

... Shift control logic Clock logic MSTR SPE SPIE SPCR – SPI control register Internal bus Figure 8-1 SPI block diagram SERIAL PERIPHERAL INTERFACE MISO S PD2 M M MOSI PD3 S Pin control logic S SCK PD4 M SS PD5 SPDR – SPI data register TPG MC68HC11KW1 ...

Page 145

... Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register. MC68HC11KW1 SERIAL PERIPHERAL INTERFACE 3 4 ...

Page 146

... SS must go high between successive characters in an SPI message. When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is only one SPI slave MCU, its SS line can be tied to V used. MOTOROLA 8-4 as long as only CPHA = 1 clock mode is SS SERIAL PERIPHERAL INTERFACE TPG MC68HC11KW1 ...

Page 147

... SCK cycle. The transfer ends when SPIF is set, for a slave in which CPHA=1. 8.5 SPI registers The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage functions. Refer to the following information for a description of how these registers are organized. MC68HC11KW1 SERIAL PERIPHERAL INTERFACE 8 TPG MOTOROLA ...

Page 148

... MSTR — Master mode select 1 (set) – Master mode 0 (clear) – Slave mode MOTOROLA 8-6 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0028 SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu SERIAL PERIPHERAL INTERFACE State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 149

... OPT2 register, and that its state on reset is zero. Table 8-1 SPI clock rates E clock SPR[2:0] divide ratio MC68HC11KW1 SERIAL PERIPHERAL INTERFACE SPI clock frequency ( baud rate) for 4MHz 2 2.0 MHz 4 1.0 MHz 16 250 kHz 32 125 kHz 8 ...

Page 150

... To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to Section 8.3.4 and Section 8.4. Bits [5, 3:0] — Not implemented; always read zero. MOTOROLA 8-8 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0029 SPIF WCOL 0 MODF 0 SERIAL PERIPHERAL INTERFACE State bit 2 bit 1 bit 0 on reset 0000 0000 TPG MC68HC11KW1 ...

Page 151

... No visibility of internal reads on external bus. In single chip mode this bit determines whether the E clock drives out from the chip. 1 (set) – E pin is driven low. 0 (clear) – E clock is driven out from the chip. MC68HC11KW1 SERIAL PERIPHERAL INTERFACE bit 7 bit 6 bit 5 bit 4 bit 3 ...

Page 152

... SPCR, this bit specifies the SPI clock rate. Refer to Table 8-1. XDV[1, 0] — XOUT clock divide select (refer to Section 4) These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if enabled by the CLKX bit in CONFIG. 8 MOTOROLA 8-10 SERIAL PERIPHERAL INTERFACE TPG MC68HC11KW1 ...

Page 153

... TIMING SYSTEM The MC68HC11KW1 contains three 16-bit timers. Figure 9-1 provides a diagram of the entire timing system. The main timer, Timer 1, is described in the following paragraphs; refer to Section 9.2 and Section 9.3 for descriptions of Timer 2 and Timer 3. 9.1 Timer 1 Timer 1 is the standard M68HC11 timing system, composed of several clock divider chains. The main clock divider chain includes a 16-bit free-running counter, driven by a programmable prescaler ...

Page 154

... TIMING SYSTEM SCI receiver clock SCI transmitter clock ÷ 16 (baud rate) E clock Internal bus clock PH2 (for CPU, PWM, A/D and memory) SPI Pulse accumulator Real time interrupt Set Q FF2 Reset Q Force COP reset T2OF TCNT2 IC/OC TCNT3 T3OF IC/OC T1OF TCNT1 IC/OC TPG MC68HC11KW1 ...

Page 155

... I/ output compare pins. When one of these pins is being used for an output compare function, it cannot be written directly were a general-purpose output. Each of the output compare functions (OC[5:2]) is related to one of the port A output pins. Output MC68HC11KW1 ) is tapped off from the free-running counter chain. The COP Clock 16 ...

Page 156

... PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. MOTOROLA 9-4 TIMING SYSTEM TPG MC68HC11KW1 ...

Page 157

... Interrupt requests 1–9 (these are further qualified by the I-bit in the CCR) ‡ Port A pin actions are controlled by OC1M, OC1D, PACTL, TCTL1 and TCTL2 registers Figure 9-2 Timer 1 capture/compare block diagram MC68HC11KW1 TOI & TOF Taps for RTI, COP and PA ...

Page 158

... EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000 EDGxB EDGxA Configuration 0 0 ICx disabled 0 1 ICx captures on rising edges only 1 0 ICx captures on falling edges only 1 1 ICx captures on any edge TIMING SYSTEM State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 159

... PA3 pin. To enable input capture pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To use output compare register, set the I4/O5 bit to a logic level zero. Refer to Section 9.6.1. The TI4/O5 register pair resets to ones ($FFFF). MC68HC11KW1 bit 7 bit 6 bit 5 ...

Page 160

... OC1M, and the output compare 1 data register, OC1D. OC1M specifies which port A outputs are to be used, and OC1D specifies what data is placed on these port pins. MOTOROLA 9-8 TIMING SYSTEM TPG MC68HC11KW1 ...

Page 161

... The CFORC bits should not normally be used on an output compare function that is programmed to toggle its output on a successful compare, because a normal compare occurring immediately before or after the force would produce a double toggle. This may be undesirable if it happens quickly, since the resulting output pulse would be very short. MC68HC11KW1 bit 7 bit 6 bit 5 ...

Page 162

... OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 Address bit 7 bit 6 bit 5 bit 4 bit 3 $000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset 0000 0000 State bit 2 bit 1 bit 0 on reset 0000 0000 TPG MC68HC11KW1 ...

Page 163

... OM[2:5] — Output mode OL[2:5] — Output level OMx OLx These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 (14) (13) (12) ...

Page 164

... If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. MOTOROLA 9-12 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0022 OC1I OC2I OC3I OC4I I4/O5I TIMING SYSTEM State bit 2 bit 1 bit 0 on reset IC1I IC2I IC3I 0000 0000 TPG MC68HC11KW1 ...

Page 165

... Selected edge has been detected on corresponding port pin. 0 (clear) – Selected edge has not been detected on corresponding port pin. These flags are set each time a selected active edge is detected on the ICx input line MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 ...

Page 166

... Timer 1 prescale rate is used for Timer 3. MOTOROLA 9-14 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0024 TOI RTII PAOVI PAII 0 PR[1:0] Prescaler TIMING SYSTEM State bit 2 bit 1 bit 0 on reset 0 PR1 PR0 0000 0000 TPG MC68HC11KW1 ...

Page 167

... The functions of Timer 2 share I/O with the pins of port J as follows: The Timer 2 prescaler stage divider with the E clock as its input. Prescaling factors can be selected by the P2RA and P2RB bits in the TCTL4 register. Timer 2 also offers an MC68HC11KW1 bit 7 bit 6 ...

Page 168

... Immediately before the switch it was sourced by the internal E clock, so the first 16-stage count cycle has an offset equal to the number of E clock cycles after reset before the first write to TCTL4. The T2STP bit can be used to reset the counter to zero, if required. 9 MOTOROLA 9-16 TIMING SYSTEM TPG MC68HC11KW1 ...

Page 169

... T2FLG status flags † Interrupt requests 1, 2 & 3 (these are further qualified by the I-bit in the CCR). ‡ Port J pin actions are controlled by the TCTL3 and TCTL4 registers. Figure 9-3 Timer 2 capture/compare block diagram MC68HC11KW1 TO2I TCNT2 (hi) TCNT2 (lo) TO2F 16-bit free running counter ...

Page 170

... This may be undesirable if it happens quickly, since the resulting output pulse would be very short. MOTOROLA 9-18 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0031 FT3C1 FT3C2 FT3C3 FT3C4 FT2C1 FT2C3 FT2C3 FT2C4 0000 0000 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 171

... Coherency requires a complete 16-bit read or write. However, if coherency is not needed, byte accesses can be used. For output compare functions, write a comparison value to output compare registers T2OC1–T2OC3 and TI1/O4. When TCNT2 value matches the comparison value, the specified pin actions occur. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 ...

Page 172

... Clear OCx output line Set OCx output line to 1 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset (10) (9) (bit 8) 0000 0000 (3) (2) (1) (bit 0) 0000 0000 State bit 2 bit 1 bit 0 on reset OL3 OM4 OL4 0000 0000 TPG MC68HC11KW1 ...

Page 173

... These control bits configure the input clock source for the Timer 2 counter. They can be written to only once after reset. ECEB ECEA MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Configuration 0 IC1 disabled 1 IC1 captures on rising edges only ...

Page 174

... When I1/O4 in TCTL4 is set, C4I is the input capture 1 interrupt enable bit. When I1/O4 in TCTL4 is zero, C4I is the output compare 4 interrupt enable bit. MOTOROLA 9-22 Address bit 7 bit 6 bit 5 bit 4 bit 3 $008C OC1I OC2I OC3I C4I TO2I TIMING SYSTEM State bit 2 bit 1 bit 0 on reset 0000 0000 TPG MC68HC11KW1 ...

Page 175

... Selected edge has not been detected on pin PJ7. TO2F — Timer 2 overflow flag 1 (set) – TCNT2 has overflowed from $FFFF to $0000. 0 (clear) – No Timer 2 overflow has occurred. Bits [2:0] — Not implemented; always read zero. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 C4F ...

Page 176

... PK3 ECIN PK4 OC1 PK5 OC2 PK6 OC3 PK7 C4 Address bit 7 bit 6 bit 5 bit 4 bit 3 $009A (bit 15) (14) (13) (12) (11) $009B (bit 7) (6) (5) (4) (3) TIMING SYSTEM State bit 2 bit 1 bit 0 on reset (10) (9) (bit 8) 1111 1111 (2) (1) (bit 0) 1111 1111 TPG MC68HC11KW1 ...

Page 177

... T3FLG status flags † Interrupt requests 1 and 2 (these are further qualified by the I-bit in the CCR). ‡ Port K pin actions are controlled by the TCTL5 and TCTL6 registers. Figure 9-4 Timer 3 capture/compare block diagram MC68HC11KW1 TCNT3 (hi) TCNT3 (lo) TO3I 16-bit TO3F free running counter F23FRC ...

Page 178

... State bit 2 bit 1 bit 0 on reset (10) (9) (bit 8) 0000 0000 (2) (1) (bit 0) 0000 0000 TPG MC68HC11KW1 ...

Page 179

... This pair of bits configures the input capture edge detector circuits for IC1. IC1 functions only if the I1/O4 bit is set. EDGB EDGA Note: The maximum frequency of the input clock must be less than E/2 when counting on one edge, and less that E/4 when counting on both edges. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 OM1 OL1 OM2 OL2 ...

Page 180

... PR3B PR3A Prescaler 0 0 Use Timer 1 rate ECEA Configuration 0 Timer 2 uses internal clock and prescaler 1 Count on rising edges of external clock only 0 Count on falling edges of external clock only 1 Count on any edge of external clock TIMING SYSTEM TPG MC68HC11KW1 ...

Page 181

... When I1/O4 in TCTL4 is zero, C4I is the output compare 4 interrupt enable bit. TO3I — Timer 3 overflow interrupt enable 1 (set) – Timer 3 overflow interrupt requested when T3OF is set. 0 (clear) – T3OF interrupts disabled. Bits [2:0] — Not implemented; always read zero. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 OC1I ...

Page 182

... TCNT3 has overflowed from $FFFF to $0000. 0 (clear) – No Timer 3 overflow has occurred. Bits [2:0] — Not implemented; always read zero. MOTOROLA 9-30 Address bit 7 bit 6 bit 5 bit 4 bit 3 $009D OC1F OC2F OC3F C4F TO2F TIMING SYSTEM State bit 2 bit 1 bit 0 on reset 0000 0000 TPG MC68HC11KW1 ...

Page 183

... TMSK2 enable the corresponding interrupt sources. TOI — Timer overflow interrupt enable (refer to Section 9.1.3.9) RTII — Real-time interrupt enable 1 (set) – Real time interrupt requested when RTIF is set. 0 (clear) – Real time interrupts disabled. MC68HC11KW1 E = 4MHz E = xMHz 1.02ms ...

Page 184

... PAIF — Pulse accumulator input edge interrupt flag (refer to Section 9.6) Bits [3:0] — Not implemented; always read zero MOTOROLA 9-32 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0025 TOF RTIF PAOVF PAIF 0 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset 0000 0000 TPG MC68HC11KW1 ...

Page 185

... COP function. 9.6 Pulse accumulator The MC68HC11KW1 has an 8-bit counter that can be configured to operate either as a simple event counter, or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Figure 9-5. ...

Page 186

... Table 9-3 Pulse accumulator timing PACNT E clock Cycle time 64/E overflow 250 ns 16.0 µs 4.096 ms TOF RTIF PAOVF PAIF 0 TOI 0 RTII 0 PAOVI 0 PAII 0 0 PR1 PR0 Overflow 2:1 Clock PACNT MUX Enable PACTL Internal data bus TIMING SYSTEM & 1 Interrupt requests & 2 TPG MC68HC11KW1 ...

Page 187

... I4/O5 — Input capture 4/output compare 5 1 (set) – Input capture 4 function is enabled (no OC5). 0 (clear) – Output compare 5 function is enabled (no IC4). RTR[1:0] — RTI interrupt rate selects (refer to Section 9.4) MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 0 PAEN PAMOD PEDGE 0 I4/O5 ...

Page 188

... TOF RTIF PAOVF PAIF 0 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset (2) (1) (bit 0) undefined State bit 2 bit 1 bit 0 on reset 0 PR1 PR0 0000 0000 State bit 2 bit 1 bit 0 on reset 0000 0000 TPG MC68HC11KW1 ...

Page 189

... By configuring the PWMs for 16-bit mode with E equal to 4MHz, PWM periods greater than one minute are possible. In 16-bit mode, duty cycle resolution parts per million can be achieved (at a PWM frequency of 60Hz). In the same system, a PWM frequency of 1kHz corresponds to a duty cycle resolution of 0.025%. MC68HC11KW1 Pin Alternative function PH0 PW1 ...

Page 190

... When concatenated, channel 1 is the high-order byte and the channel 2 pin (PH1) is the output. MOTOROLA 9-38 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0060 CON34 CON12 PCKA2 PCKA1 0 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset PCKB3 PCKB2 PCKB1 0000 0000 TPG MC68HC11KW1 ...

Page 191

... PWDTY3 8-bit comparator PWPER3 reset 8-bit comparator PWDTY4 8-bit comparator PWPER4 reset carry Figure 9-6 PWM timer block diagram MC68HC11KW1 PCKB1 PCKB2 PCKB3 Prescale select ÷ 16, 32, 64, 128 Prescale select 8-bit counter ÷ PCKA1 PCKA2 8-bit comparator ...

Page 192

... PCKB[3:1] — Prescaler for clock B Determines the frequency of clock B. Refer to Table 9-4. Table 9-4 Clock A and clock B prescalers 9 PCKA[2: MOTOROLA 9-40 Clock A PCKB[ TIMING SYSTEM Clock B E E/2 E/4 E/8 E/16 E/32 E/64 E/128 TPG MC68HC11KW1 ...

Page 193

... PWSCAL — PWM timer prescaler register Address Pulse width scale (PWSCAL) $0062 Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by two. If PWSCAL = $00, clock A is divided by 256, then divided by two to generate clock S. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 ...

Page 194

... PWEN[4:1] — Pulse width channels 4–1 1 (set) – Channel enabled on the associated port pin. 0 (clear) – Channel disabled. MOTOROLA 9-42 Address bit 7 bit 6 bit 5 bit 4 bit 3 $0063 TPWSL DISCP 0 0 PWEN4PWEN3PWEN2PWEN1 0000 0000 TIMING SYSTEM State bit 2 bit 1 bit 0 on reset TPG MC68HC11KW1 ...

Page 195

... This register can be written at any time, and the written value will take effect from the start of the next PWM timer cycle. Reads of this register return the most recent value written. MC68HC11KW1 bit 7 bit 6 ...

Page 196

... PWDTYx PWPERx Figure 9-7 PWM duty cycle TIMING SYSTEM State bit 2 bit 1 bit 0 on reset (2) (1) (bit 0) 1111 1111 (2) (1) (bit 0) 1111 1111 (2) (1) (bit 0) 1111 1111 (2) (1) (bit 0) 1111 1111 TPG MC68HC11KW1 ...

Page 197

... The analog-to-digital converter system consists of a single 10-bit successive approximation type converter and a 16-channel multiplexer. Ten of the channels are connected to pins on the MC68HC11KW1 (ports E and G), two are unused and the remaining four channels are dedicated to internal reference points or test functions. The A/D converter shares input pins with port E and ...

Page 198

... CC, CB, CA) in the ADCTL register. The CONV8 bit selects either four or eight conversions. All “reserved” channels are connected to V MOTOROLA 10-2 converts to $FFC0 (full scale) and RH converts to $0000. An input voltage greater than V RL ANALOG-TO-DIGITAL CONVERTER will convert the supply voltage and TPG MC68HC11KW1 ...

Page 199

... SCAN bit determines whether continuous or single scanning is selected. The channel is selected by the CD – CA bits in the ADCTL register. If channels eight and nine are selected, then the result registers previously used for two of the other channels become overwritten with channel eight and nine results. MC68HC11KW1 ANALOG-TO-DIGITAL CONVERTER CONV8 = 0 CONV8 = 1 ...

Page 200

... CC). In the second two variations, the CONV8 bit is set and a group of eight channels is selected, depending on the state of the CD bit. The state of the SCAN bit determines whether continuous or single scanning is selected. Refer to Table 10-1. MOTOROLA 10-4 ANALOG-TO-DIGITAL CONVERTER TPG MC68HC11KW1 ...

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