MPC993 Freescale Semiconductor, Inc, MPC993 Datasheet

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MPC993

Manufacturer Part Number
MPC993
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Part Number:
MPC993FA
Manufacturer:
MOTOROLA/摩托罗拉
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20 000
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MPC993FAR2
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dynamic Switch
PLL Clock Driver
clock tree designs. The device receives two differential LVPECL clock
signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signals frequency and phase
while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer
performance.
input clock (input clock stuck HIGH or LOW for at least 3 feedback clock edges), an input bad flag will be set and the device will
automatically switch from the bad reference clock input to the good one. During this dynamic switch of the input references, the
MPC993 outputs will slew, with minimal period disturbances to the new phase.
9/97
Motorola, Inc. 1997
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control/Statis I/O
3.3V Operation
32–Lead TQFP Packaging
The MPC993 is a PLL clock driver designed specifically for redundant
The MPC993 continuously monitors the two input signals to identify faulty reference clocks. Upon identification of a faulty
50ps Cycle–Cycle Jitter
Sel_Clk
Ext_FB
Ext_FB
CLK0
CLK0
CLK1
CLK1
MR
1
OR
Figure 1. Block Diagram
Dynamic Switch
Logic
PLL
PLL_En
2
4
REV 0
32–LEAD PLASTIC TQFP PACKAGE
MPC993
CASE 751D–04
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
FA SUFFIX

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MPC993 Summary of contents

Page 1

... Cycle–Cycle Jitter The MPC993 continuously monitors the two input signals to identify faulty reference clocks. Upon identification of a faulty input clock (input clock stuck HIGH or LOW for at least 3 feedback clock edges), an input bad flag will be set and the device will automatically switch from the bad reference clock input to the good one ...

Page 2

... Input LOW Voltage (LVCMOS Outputs Input LOW Current I EE Power Supply Current MOTOROLA PRELIMINARY MPC993 Figure 2. 32–Lead Pinout (Top View) Parameter GNDA GND 2 VCC Inp0bad ...

Page 3

... CLKn to Q (Locked (Note 2.)) Y–150 Within Bank All Outputs 75MHz Output (Note 3.) 150MHz Output (Note 3.) 75MHz Output (Note 4.) 150MHz Output (Note 4.) out of phase. Delta period change per cycle is averaged over the Pin Definition 3 MPC993 Min Typ Max Unit 480 MHz 2000 ...

Page 4

... Alarm_Reset pin being negated. If both of the input signals go bad simultaneously the MPC993 PLL will lose lock and the VCO will drift to an indeterminate frequency. Once the MPC993 switches from a bad clock it will continue to use the new clock until the Alarm_Reset pin is asserted. The device will not switch back to a “ ...

Page 5

... F D É É SECTION AE– MPC993 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...

Page 6

... Mfax is a trademark of Motorola, Inc. JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 6 ECLinPS and ECLinPS Lite MPC993/D DL140 — Rev 3 ...

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