PM5316-BI PMC-Sierra Inc, PM5316-BI Datasheet
PM5316-BI
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... SPECTRA™ 4x155 SONET/SDH Payload Extractor/Aligner Issue No. 6: November 2005 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet PM5316 4 x 155 Mbit/s Data Sheet Released Released 1 ...
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Legal Information Copyright Copyright 2005 PMC-Sierra, Inc. All rights reserved. The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or ...
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Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP ...
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Revision History Issue No. Issue Date Issue 6 November 2005 Issue 5 September 2002 Issue 4 Mar 2001 Issue 3 Jan 2001 Issue 2 Sept 2000 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: ...
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Issue No. Issue Date Issue 1 June 2000 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Details of Change Added Section describing loopbacks ...
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Table of Contents Legal Information........................................................................................................................... 2 Copyright................................................................................................................................. 2 Disclaimer ............................................................................................................................... 2 Trademarks ............................................................................................................................. 2 Patents .................................................................................................................................... 2 Contacting PMC-Sierra.................................................................................................................. 2 Revision History............................................................................................................................. 4 Table of Contents........................................................................................................................... 6 List of Registers............................................................................................................................. 9 List of Figures .............................................................................................................................. 19 List of Tables................................................................................................................................ 21 ...
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Analog Miscellaneous Signals .................................................................................... 66 9.12 JTAG Test Access Port (TAP) Signals......................................................................... 66 9.13 Power and Ground ...................................................................................................... 67 10 Functional Description .......................................................................................................... 70 10.1 Receive Line Interface and CRSI................................................................................ 70 10.2 Receive Section Overhead Processor (RSOP) .......................................................... 71 ...
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Loop Back Modes ..................................................................................................... 409 13.9 Loop Back Operation ................................................................................................ 413 13.10 JTAG Support............................................................................................................ 414 13.11 Board Design Recommendations ............................................................................. 419 13.12 Analog Power Supply Filtering .................................................................................. 420 13.13 Power Supplies Sequencing ..................................................................................... 422 13.14 Interfacing to ECL or ...
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List of Registers Register 0000H: SPECTRA 4x155 Reset, Identity and Accumulation Trigger ......................... 115 Register 0001H: Master Clock Activity Monitor......................................................................... 116 Register 0002H: Master Clock Control...................................................................................... 117 Register 0003H: Master Interrupt Status................................................................................... 119 Register 0004H: Path Processing Slice Interrupt Status ...
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Register 0117H, 0217H, 0317H, 0417H: RSOP Section BIP (B1) Error Count #2 .............................................................................................................................. 154 Register 0118H, 0218H, 0318H, and 0418H: RLOP Control and Status.................................. 155 Registers 0119H, 0219H, 0319H, and 0419H: RLOP Interrupt Enable and Status ........................................................................................................................ 157 Registers 011AH, ...
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Registers 0150H, 0250H, 0350H, and 0450H: RASE SD Saturation Threshold ...................... 182 Registers 0151H, 0251H, 0351H, and 0451H: RASE SD Declaring Threshold ....................... 183 Registers 0152H, 0252H, 0352H, and 0452H: RASE SD Declaring Threshold ....................... 183 Registers 0153H, 0253H, 0353H, ...
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Register 1081H: SPECTRA 4x155 Add Bus STM-1 #1 AU-3 #1 Select................................... 218 Register 1082H: SPECTRA 4x155 Add Bus STM-1 #2 AU-3 #1 Select................................... 219 Register 1083H: SPECTRA 4x155 Add Bus STM-1 #3 AU-3 #1 Select................................... 220 Register 1084H: SPECTRA 4x155 ...
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Registers 111DH, 121DH, 131DH, 141DH, 151DH, 161DH, 171DH, 181DH, 191DH, 1A1DH, 1B1DH, and 1C1DH: RPPS RALM Output Control #2 .............................................................................................................................. 256 Registers 111EH, 121EH, 131EH, 141EH, 151EH, 161EH, 171EH, 181EH, 191EH, 1A1EH, 1B1EH, and 1C1EH: RPPS Reserved ........................................... 258 Registers ...
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Registers 1146H, 1246H, 1346H, 1446H, 1546H, 1646H, 1746H, 1846H, 1946H, 1A46H, 1B46H, and 1C46H: RPOP Pointer MSB........................................ 282 Registers 1147H, 1247H, 1347H, 1447H, 1547H, 1647H, 1747H, 1847H, 1947H, 1A47H, 1B47H, and 1C47H: RPOP Path Signal Label................................ 284 Registers 1148H, 1248H, ...
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Registers 1163H, 1263H, 1363H, 1463H, 1563H, 1663H, 1763H, 1863H, 1963H, 1A63H, 1B63H, and 1C63H: SPTB Indirect Data Register.......................... 307 Registers 1164H, 1264H, 1364H, 1464H, 1564H, 1664H, 1764H, 1864H, 1964H, 1A64H, 1B64H, and 1C64H: SPTB Expected Path Signal Label.......................................................................................................................... 308 Registers ...
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Registers 11B0H, 12B0H, 13B0H, 14B0H, 15B0H, 16B0H, 17B0H, 18B0H, 19B0H, 1AB0H, 1BB0H, and 1CB0H: SPECTRA 4x155 TPPS Auxiliary Path Interrupt Status................................................................................... 334 Registers 11C0H, 12C0H, 13C0H, 14C0H, 15C0H, 16C0H, 17C0H, 18C0H, 19C0H, 1AC0H, 1BC0H, and 1CC0H: TPOP Control .............................................. 335 ...
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Registers 11E1H, 12E1H, 13E1H, 14E1H, 15E1H, 16E1H, 17E1H, 18E1H, 19E1H, 1AE1H, 1BE1H, and 1CE1H: TPIP Alarm Interrupt Status (EXTD=0) .................................................................................................................. 356 Registers 11E2H, 12E2H, 13E2H, 14E2H, 15E2H, 16E2H, 17E2H, 18E2H, 19E2H, 1AE2H, 1BE2H, and 1CE2H: TPIP Pointer Interrupt Status ....................... ...
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Registers 11FCH, 12FCH, 13FCH, 14FCH, 15FCH, 16FCH, 17FCH, 18FCH, 19FCH, 1AFCH, 1BFCH, and 1CFCH: APGM Monitor Error Count #1.................... 384 Registers 11FDH, 12FDH, 13FDH, 14FDH, 15FDH, 16FDH, 17FDH, 18FDH, 19FDH, 1AFDH, 1BFDH, 1CFDH:APGM Monitor Error Count #2............................ 384 Register 2000H: ...
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List of Figures Figure 1 STS-3 (STM-0/AU-3) or STS-3c (STM-1/AU-4) Application with 19.44 MHz Byte TelecomBus Interface................................................................................. 30 Figure 2 STS-3 (STM-1/AU-3) or STS-3c (STM-1/AU-4) Application with 77.76 MHz Byte TelecomBus Interface................................................................................. 31 Figure 3 Block Diagram ............................................................................................................. 32 Figure ...
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Figure 34 Receive Path Alarm Port Timing ............................................................................. 435 Figure 35 Transmit Ring Control Port...................................................................................... 436 Figure 36 Transmit Alarm Port Timing .................................................................................... 437 Figure 37 STS-3 (STM-1/AU-3) 19.44 MHz Byte Drop Bus Timing ........................................ 438 Figure 38 STS-3c (STM-1/AU-4) ...
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List of Tables Table 1 Pointer Interpreter Event (Indications) Description ...................................................... 80 Table 2 Pointer Interpreter Transition Description .................................................................... 81 Table 3 Path Signal Label Match/Mismatch State Table. ......................................................... 85 Table 4 Pointer Generator Event (Indications) Description....................................................... 88 Table 5 ...
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Table 34 Receive Line Input Interface Timing......................................................................... 459 Table 35 Receive Line Overhead and Alarm Output Timing................................................... 459 Table 36 Receive Path Overhead and Alarm Port Output Timing .......................................... 460 Table 37 Receive Ring Control Port Output Timing ................................................................ 462 ...
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Features 1.1 General • Monolithic four channel SONET/SDH Payload Extractor/Aligner for use in STS-3 (STM- 1/AU-3) or STS-3c (STM-1/AU-4) interface applications, operating at serial interface speeds of 155.52 Mbit/s. • Provides integrated clock recovery and clock synthesis for direct ...
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Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors. • Extracts and serializes the order wire channels (E1, E2), the data communication channels (D1-D3, D4-D12) and the section user channel (F1) from ...
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Extracts a 64-byte or 16-byte path trace (J1) message using an internal register bank for the receive stream. Detects an unstable path trace message or mismatch with an expected message, and inserts Path RAI upon either of these conditions. ...
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Applications • SONET/SDH Add Drop Multiplexers • SONET/SDH Terminal Multiplexers • SONET/SDH Line Multiplexers • SONET/SDH Cross Connects • SONET/SDH Test Equipment • Switches and Hubs • Routers Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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References 1. American National Standard for Telecommunications - Digital Hierarchy - Optical Interface Rates and Formats Specification, ANSI T1.105-1991. 2. American National Standard for Telecommunications - Layer 1 In-Service Digital Transmission Performance Monitoring, T1X1.3/93-005R1, April 1993. 3. Committee T1 ...
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Document Conventions & Definitions The following conventions are used along this document: designated equivalent signals, either input our output. Each of these signals SIGNAL1-4: applies to the corresponding device channel. designate a differential signal. SIGNAL±: SIGNAL[N:0]: designate a bus ...
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SIPO Serial-to-parallel Converter SLLB System Side Line Loop back SPE Synchronized Payload Envelope SPTB SONET/SDH Path Trace Buffer SSTB SONET/SDH Section Trace Buffer TAP Test Access Port TLOP Transmit Line Overhead Processor TPOP Transmit Path Overhead Processor TPPS Transmit Path ...
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... Application Examples The PM5316 SPECTRA™ 4x155 device is designed for use in various SONET/SDH network elements including switches, terminal multiplexers, and Add/Drop multiplexers. In these applications, the line interface of the SPECTRA 4x155 typically interfaces directly with the electrical optical modules and the system side interface connects directly with a TelecomBus. ...
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Figure 2 STS-3 (STM-1/AU-3) or STS-3c (STM-1/AU-4) Application with 77.76 MHz Byte TelecomBus Interface Mbi ts Opt ica l Opti cal Tra nsc eiv Mbi ts Opt ...
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Block Diagram Figure 3 Block Diagram ATP[3:0] PECLV Clock Synthesis REFCLK+/- (CSPI) Channel Line Side Top #m Tx Transport m={1,2,3,4] Overhead Controller (TTOC Line Section O/H TXD+/-[4:1] I/F Processor (TSOP) Section Trace CP/CN[4:1] Buffer (SSTB) Clock and ...
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... Functional Description The PM5316 SPECTRA 4X155 SONET/SDH Payload Extractor/Aligner terminates the transport and path overhead of four STS-3 (STM-1/AU-3) and STS-3c (STM-1/AU-4) streams at 155 Mbit/s. The device implements significant receive and transmit functions for a SONET/SDH-compliant line interface. In the receive direction, the SPECTRA 4x155 receives SONET/SDH frames via bit serial interfaces, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path ...
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The SPECTRA 4x155 supports Time-Slot Interchange (TSI) on the Telecom Add and Drop buses. On the Drop side, the TSI views the receive stream as 12 independent time-division multiplexed columns of data (12 constituent STS-1 (STM-0/AU-3) or equivalent streams or ...
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Pin Diagrams The SPECTRA 4x155 is available in a 520-pin SBGA package having a body size and a ball pitch of 1.27 mm. Figure 4 Pin Diagram of SPECTRA 4x155 Proprietary and Confidential ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet QAVD_2 Released QAVS_2 36 ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Released 37 ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Released 38 ...
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Pin Description (SBGA 520) The SPECTRA 4x155 is available in a 520-pin SBGA package having a body size of 40 40.0 mm and a ball pitch of 1.27 mm. 9.1 Serial Line side Interface Signals Pin Name ...
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Pin Name Type PGMTCLK Output CP1 Analog CN1 CP2 CN2 CP3 CN3 CP4 CN4 PECLV Input 9.2 Section/Line/Path Status and Alarm Signals Pin Name Type SALM1 Output SALM2 SALM3 SALM4 LOF1 Output LOF2 LOF3 LOF4 Proprietary and Confidential to PMC-Sierra, ...
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Pin Name Type LOS1/ Output LOS2/ LOS3/ LOS4/ /RRCPFP1 /RRCPFP2 /RRCPFP3 /RRCPFP4 LRDI1/ Output LRDI2/ LRDI3/ LRDI4/ /RRCPCLK1 /RRCPCLK2 /RRCPCLK3 /RRCPCLK4 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ...
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Pin Name Type LAIS1/ Output LAIS2/ LAIS3/ LAIS4/ /RRCPDAT1 /RRCPDAT2 /RRCPDAT3 /RRCPDAT4 RLAIS1/ Input RLAIS2/ RLAIS3/ RLAIS4/ /TRCPCLK1 /TRCPCLK2 /TRCPCLK3 /TRCPCLK4 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ...
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Pin Name Type Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. The TRCPFP1-4 and TRCPDAT1-4 signals are sampled on the ...
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Pin Name Type TLRDI1/ Input TLRDI2/ TLRDI3/ TLRDI4/ /TRCPFP1 /TRCPFP2 /TRCPFP3 /TRCPFP4 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. ...
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Pin Name Type TLAIS1/ Input TLAIS2/ TLAIS3/ TLAIS4/ /TRCPDAT1 /TRCPDAT2 /TRCPDAT3 /TRCPDAT4 9.3 Receive Section/Line/Path Overhead Extraction Signals Pin Name Type RTOHCLK1 Output RTOHCLK2 RTOHCLK3 RTOHCLK4 RTOH1 Output RTOH2 RTOH3 RTOH4 Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Pin Name Type RTOHFP1 Output RTOHFP2 RTOHFP3 RTOHFP4 RPOHCLK Output RPOHFP Output RPOH Output RPOHEN Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data ...
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Pin Name Type RAD Output B3E Output RTCEN Input RTCOH Input RALM Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function ...
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Pin Name Type Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. corresponding stream. In Addition to these alarms, the LOS ...
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Pin Name Type 9.4 Transmit Section/Line/Path Overhead Insertion Signals Pin Name Type TTOHCLK1 Output TTOHCLK2 TTOHCLK3 TTOHCLK4 TTOH1 Input TTOH2 TTOH3 TTOH4 TTOHEN1 Input TTOHEN2 TTOHEN3 TTOHEN4 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document ...
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Pin Name Type TTOHFP1 Output TTOHFP2 TTOHFP3 TTOHFP4 TAD Input TAFP Input TACK Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin ...
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Pin Name Type 9.5 Receive Section/Line DCC Extraction Signals Pin Name Type RSLDCLK1 Tristate RSLDCLK2 Output RSLDCLK3 RSLDCLK4 RSLD1 Tristate RSLD2 Output RSLD3 RSLD4 9.6 Transmit Section/Line DCC Insertion Signals Pin Name Type TSLDCLK1 Tristate TSLDCLK2 Output TSLDCLK3 TSLDCLK4 Proprietary ...
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Pin Name Type TSLD1 Input TSLD2 TSLD3 TSLD4 9.7 Transmit Path AIS Insertion Signals Pin Name Pin Type DPAISCK Input DPAISFP Input DPAIS Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue ...
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Pin Name Pin Type TPAISCK Input TPAISFP Input TPAIS Input 9.8 Drop Bus Telecom Interface Signals Pin Name Pin Type DCK Input DFP Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue ...
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Pin Name Pin Type DD[0] Output DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8] Output DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA ...
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Pin Name Pin Type DD[16] Output DD[17] DD[18] DD[19] DD[20] DD[21] DD[22] DD[23] DD[24] Output DD[25] DD[26] DD[27] DD[28] DD[29] DD[30] DD[31] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA ...
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Pin Name Pin Type DPL[1] Output DPL[2] Output DPL[3] Output DPL[4] Output DC1J1V1[1] Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin ...
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Pin Name Pin Type DC1J1V1[2] Output DC1J1V1[3] Output DC1J1V1[4] Output DDP[1] Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. ...
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Pin Name Pin Type DDP[2] Output DDP[3] Output DDP[4] Output 9.9 Add Bus Telecom Interface Signals Pin Name Pin Type ACK Input AD[0] Input AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Pin Name Pin Type AD[8] Input AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] Input AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] Input AD[25] AD[26] AD[27] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document ...
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Pin Name Pin Type AD[28] AD[29] AD[30] AD[31] APL[1] Input APL[2] Input APL[3] Input APL[4] Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data ...
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Pin Name Pin Type AC1J1V1[1]/ Input AFP[1] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. overhead bytes. APL[4] is set ...
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Pin Name Pin Type AC1J1V1[2]/ Input AFP[2] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. provided on the Add data ...
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Pin Name Pin Type AC1J1V1[3]/ Input AFP[3] AC1J1V1[4]/ Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. identified. When using ...
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Pin Name Pin Type AFP[4] ADP[1] Input ADP[2] Input ADP[3] Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1990822, Issue 6 SPECTRA 4x155 ASSP Telecom Standard Product Data Sheet Pin Function No. bus ...
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Pin Name Pin Type ADP[4] Input 9.10 Microprocessor Interface Signals Pin Name Type MBEB Input CSB Schmidt TTL Input RDB/ Input E WRB/ Input RWB D[7] I/O D[6] D[5] D[4] D[3] D[2] D[1] Proprietary and Confidential to PMC-Sierra, Inc., and ...
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Pin Name Type D[0] A[13] Input A[12] Input A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB Schmidt TTL Input ALE Input INTB OD Output 9.11 Analog Miscellaneous Signals Pin Name Type ATP[0] Analog ATP[1] ATP[2] ...
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TDO Tristate Output TRSTB Schmidt TTL Input 9.13 Power and Ground Pin Name Pin Type Reserved1 Output Reserved2 Output Reserved3 Input Reserved4 Input Reserved5 Output VBIAS[0] Bias VBIAS[1] Voltage AVD Analog Power AVS Analog Ground Proprietary and Confidential to PMC-Sierra, ...
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Pin Name Pin Type VDD Digital Power VSS Digital Ground Notes on Pin Description: 1. All SPECTRA 4x155 inputs and bi-directional pins present minimum capacitive loading and operate at TTL logic levels except the SD and RXD± inputs, which operate ...
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Due to ESD protection structures in the pads, caution must be taken when powering the device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme ...
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Functional Description 10.1 Receive Line Interface and CRSI The Receive Line Interface and the Clock Recover/Serial-to-Parallel Converter (CRSI) blocks perform PECL conversion, clock and data recovery on the incoming 155.52 Mbit/s data stream, and serial-to-parallel conversion based on the ...
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Figure 5 SPECTRA 4x155 Typical Jitter Tolerance 100 10 Jitter (UI 10.1.2 Serial-to-Parallel Converter (SIPO) The Serial-to-Parallel Converter (SIPO) inside the CRSI converts the received bit serial SONET/SDH stream into a byte serial stream. The SIPO ...
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The RSOP may also force Line AIS. AIS-L is inserted in the receive data stream using input RLAIS or, optionally, automatically when LOS, LOF, or when section trace mismatch or unstable events occur. Line AIS may also be inserted automatically ...
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Descramble The Descramble Block of RSOP uses a frame-synchronous descrambler to process the receive stream. The generating polynomial and the sequence length is 127. Details of the de-scrambling operation are provided ...
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Section trace identifier data bytes from the receive stream are written into the capture page. The expected identifier message is downloaded by the microprocessor into the expected page. On receipt of a trace identifier byte written into the ...
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Line AIS Detect The Line AIS Block detects the presence of an alarm indication signal (LAIS) in the receive stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the ...
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Automatic Protection Switch (APS) Control The Automatic Protection Switch (APS) control block of RASE filters and captures the receive APS channel bytes (K1 and K2) allowing them to be read via the RASE APS K1 register and the RASE ...
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Receive Transport Overhead Controller (RTOC) The Receive Transport Overhead Controller block (RTOC) extracts the entire receive transport overhead on RTOH1-4, along with the nominal 5.184 MHz transport overhead clock, RTOHCLK1-4, and the transport overhead frame position signal, RTOHFP1-4, allowing ...
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Receive De-multiplexer (RX_DEMUX) The receive de-multiplexer (RX_DEMUX) block within each channel de-multiplexes the STS-3 (STM-1) stream into three STS-1(STM-1/AU3) streams or three equivalent STS-1(STM1/AU3) streams for an STS-3c(ATM1(AU4). In the case of an STS-3 (STM1/AU3) stream, the demultiplexed streams ...
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Note: The path overhead bytes are provided on RPOH at close to twice the rate in which they are received to facilitate the multiplexing of the extracted data from the various RPPSs single serial output. Output RPOHEN ...
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The transition between states will be consecutive events (indications). Refer to Figure 6. An example is when three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is ...
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Event (Indication) dec_ind inv_point new_point inc_req dec_req Notes 1. Active offset is defined as the accepted current phase of the SPE (VC) in the NORM_state and is undefined in the other states. 2. Enabled NDF is defined as the following ...
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Notes 1. The transitions from NORM_state to NORM_state do not represent state changes but imply offset changes new_point takes precedence over other events and if the IINVCNT bit is set resets the inv_point count. 3. All three ...
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Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point), discontinuous change of pointer alignment, and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF ...
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Path Overhead Extract Path overhead bytes are extracted from an STS-1 (STM-0/AU-3) or equivalent stream that is being processed by the RPOP. When processing a concatenated stream, only the RPOP in a master RPPS will provide valid path overhead bytes. ...
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The length of the path trace identifier message is selectable between 16-bytes and 64-bytes. When programmed for 16-byte messages, the SPTB synchronizes to the byte with the most significant bit set to high and places the byte at the first ...
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Receive TelecomBus Aligner (RTAL) The Receive TelecomBus Aligner (RTAL) block of RPPS takes the payload data from an STS-1 (STM-0/AU-3) or equivalent stream from the RPOP and inserts TelecomBus Drop bus. It aligns the frame of ...
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Pointer Generator The Pointer Generator generates the Drop bus pointer (H1, H2) as specified in the references. The pointer value is used to determine the location of the path overhead (the J1 byte) in the Drop bus STS-1 (STM-0/AU-3) stream. ...
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Figure 7 Pointer Generation State Diagram The events indicated in the state diagram are defined in Table 4. Table 4 Pointer Generator Event (Indications) Description Event (Indication) ES_lowerT ES_upperT FO_discont PI_AIS Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Event (Indication) PI_LOP PI_NORM Note 1. A frame offset discontinuity occurs if an incoming NDF enabled is received overflow/underflow occurred. The autonomous transitions indicated in the state diagram are defined in Table 5. Table 5 Pointer ...
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When processing a concatenated stream, the DPGM in a master RPPS co-ordinate the distributed PRBS generation by itself and its counterparts in the slave RPPSs. Each DPGM will generate one third ( the complete PRBS sequence for ...
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Path overhead bytes and fixed stuff columns in the receive concatenated stream will be collectively skipped over as described for the PRBS generator of the DPGM. To ensure that all payload bytes (all STS-1 (STM-0/AU-3) or equivalent streams ...
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Received path BIP errors (REI) and path RDIs for all the receive STS-1 (STM-0/AU-3) streams or STS-3c (STM-1/AU-4) streams from the RPPSs in a remote SPECTRA 4x155 are communicated to the corresponding TPPSs in the local SPECTRA 4x155 via the ...
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Pointer Interpreter The TPIP block allows the SPECTRA 4x155 to operate with TelecomBus-like back plane systems that do not indicate the J1 byte position. The TPIP block can be enabled using the DISJ1V1 bit in the SPECTRA 4x155 Path Configuration ...
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Transmit TelecomBus Aligner (TTAL) The Transmit TelecomBus Aligner (TTAL) block of TPPS takes the STS-1 (STM-0/AU-3) SPE (VC-3) or equivalent data stream from the Add bus and aligns it to the frame of the transmit stream. The alignment is ...
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A piece of tandem connection originating equipment should signal incoming signal failure by setting the IEC field and the payload bytes to all-ones. Likewise, the equipment should detect ISF by only examining the IEC field for all-ones. If the upstream ...
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Path RDI Insert Path RDI may be inserted via the TPOP block. The RDI codes to be inserted into the transmit stream may be supplied externally via the transmit Alarm Data Port (TAD) or may be automatically inserted via the ...
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The APS bytes K1/K2 received via the TAD port may be optionally inserted via the TTOC logic. The received K1/K2 on TAD match the transmitted K1/K2 that a mate SPECTRA transmitted. Individual data channels can be sourced from TSLD1-4. TTOHFP1-4 ...
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Figure 8 Unused and National Use Bytes 1 2 Section Line D10 The National overhead bytes are defined: • ...
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Line BIP Calculate The Line BIP Calculate Block of TLOP calculates the line BIP-24 error detection code (B2) based on the line overhead and SPE of the transmit stream. The line BIP-24 code is a bit interleaved parity calculation ...
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The BIP-8 calculation is based on the scrambled data of the complete STS-3 (STM-1) frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code ...
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Parallel-to-Serial Converter (PISO) The Parallel to Serial Converter (PISO) of SSTB converts the transmit byte serial stream to a bit serial stream. The transmit bit serial stream appears on the TXD1-4+/- PECL output. 10.17 Add/Drop Bus Time-Slot Interchange (TSI) ...
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Drop TSI On the Drop side, the Drop bus TSI logic grooms the four STS-3/3c (STM-1/AU-3/AU-4) receive streams provided by the 12 RPPSs into the corresponding column of a Drop bus stream. The Drop TSI also generates the STS-1 ...
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For the four STS-3/3c (STM-4/AU-3/AU-4) transmit streams, the Telecom bus interface accepts a byte stream from the single 77.76 MHz (STM-4) Telecom Add bus or four byte streams from the four 19.44 MHz (STM-1) byte Telecom Add buses. The byte ...
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Microprocessor Interface The Microprocessor Interface Block provides the logic required to interface the generic microprocessor bus with the normal mode and test mode registers within the SPECTRA 4x155. The normal mode registers are used during normal operation to configure ...
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REG # AddressA[13:0] 0109H 0 m 09H 010AH 0 m 0AH 010BH 0 m 0BH 010CH 0 m 0CH 0110H 0 m 10H 0111H 0 m 11H 0112H 12H-0 m 13H 0113H 0114H 0 m 14H 0115H 0 ...
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REG # AddressA[13:0] 0147H 0 m 47H 0148H 0 m 48H 0149H 0 m 49H 014AH 0 m 4AH 014BH 0 m 4BH 014CH 0 m 4CH 014DH 0 m 4DH 014EH 0 m 4EH 014FH 0 m 4FH 0150H ...
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REG # AddressA[13:0] 0500H- 0500H-051FH 051FH 0520H- 0520H-053FH 053FH 0540H - 0540H -055FH 055FH 0560H- 0560H-1000H 1000H 1001H 1001H 1002H 1002H 1003H 1003H 1004H 1004H 1005H 1005H 1006H 1006H 1007H 1007H 1008H 1008H 1009H 1009H 100AH 100AH 100BH 100BH 100CH ...
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REG # AddressA[13:0] 108DH- 108DH-10AFH 10AFH 10B0H 10B0H 10B1H 10B1H 10B2H 10B2H 10B3H 10B3H 10B4H 10B4H 10B5H 10B5H 10B6H 10B6H 10B7H 10B7H 10B8H- 10B8H-10FFH 10FFH 1100H 1 n 00H 1101H 1 n 01H 1102H 1 n 02H 1103H ...
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REG # AddressA[13:0] 1134H 1 n 34H 1135H 35H-1 n 3FH 113FH 1 n 40H 1140H 1 n 41H 1141H 1142H 1 n 42H 1143H 1 n 43H 1144H 1 n 44H 1145H 1 n 45H 1146H 1 ...
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REG # AddressA[13:0] 1168H 68H-1 n 6FH 116FH 1170H 1 n 70H 1 n 71H 1171H 1172H 1 n 72H 1 n 73H 1173H 1174H 74H-1177H 1177h 1178H 1 n 78H 1179H 1 n 79H 117AH ...
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REG # AddressA[13:0] 11C8H 1 n C8H 11C9H 1 n C9H 11CAH 1 n CAH 11CBH 1 n CBH 11CCH 1 n CCH 11CDH 1 n CDH 11CEH CEH-1 n CFH 11CFH 11D0 1 n D0H H 11D1H ...
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REG # AddressA[13:0] 11FBH 1 n FBH 11FCH 1 n FCH 11FDH 1 n FDH 11FEH FEH-1 n FFH 11FFH 1D00H 1D00H 1FFFH 1FFFH 2000H 2000H 2001H 2001H 2002H 2002H 2FFFH 2FFFH Notes 1. For all register accesses, ...
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Figure 9 Path Processing Slices and Order of Transmission STS S-1 # (ST M-1 #, STM-0/AU3 #) Slice #1 1,1 Slice #5 1,2 Slice #9 1,3 Slice #2 2,1 Slice #6 2,2 Slice #10 2,3 Slice #3 3,1 ...
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Normal Mode Register Description Normal mode registers are used to configure and monitor the operation of the SPECTRA 4x155. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[13]) is low. Notes on Normal Mode ...
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Register 0000H: SPECTRA 4x155 Reset, Identity and Accumulation Trigger Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register allows the revision ...
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Register 0001H: Master Clock Activity Monitor Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register provides activity monitoring on SPECTRA 4x155 ...
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Register 0002H: Master Clock Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register controls the various line side output clocks ...
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RCLKEN The RCLK enable (RCLKEN) bit controls the gating of the RCLK output. When RCLKEN is set low, the RCLK output is held low. When RCLKEN is set high, the RCLK output is allowed to operate normally. PGMRCHSEL[1:0] The PGMRCHSEL[1:0] ...
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Register 0003H: Master Interrupt Status Bit Type Bit 7 R/W Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R When the interrupt output INTB goes low, this register ...
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CHNL4I The CHNL4I bit is high when an interrupt request is active from the transport overhead processing blocks of Channel #4. The Section/Line Block Interrupt Status register, Auxiliary Section/Line Interrupt Status register, and the Auxiliary Signal Status/Interrupt Status register of ...
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Register 0004H: Path Processing Slice Interrupt Status #1 Bit Type Bit 7 R Bit 6 R Bit5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 0005H: Path Processing Slice Interrupt Status ...
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Index (STS-3, STS1) (STM-1, AU-3) 4 (4,1) RPPSI[12:1] The Receive Path Processing Slice Interrupts (RPPSI[12:1]) are high when an interrupt request is active from the index number receive slice. TPPSI[12:1] The Transmit Path Processing Slice Interrupts (TPPSI[12:1]) are high when ...
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Register 0007H: Path Reset Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RESET_PATH The RESET_PATH bit allows the path processing blocks of ...
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Register 000AH: FREE Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W FREE[7:0] The FREE[7:0] register bits do not perform any function. They ...
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Register 0010H: CSPI Control and Status Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R Bit 4 — Bit 3 R Bit 2 — Bit 1 R/W Bit 0 R/W This register controls the clock synthesis and reports ...
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Register 0011H: CSPI Reserved Bit Type Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Reserved The Reserved bits must be set low for proper ...
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Register 0100H, 0200H, 0300H, and 0400H: Channel Reset, Identity and Accumulation Trigger Bit Type Bit 7 R/W Bit 6 R Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 R Bit 0 R Writing to ...
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Register 0101H, 0201H, 0301H, and 0401H: Line Configuration #1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register is used to ...
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LOOPT The LOOPT bit selects the source of timing for the transmit section of the indexed channel. When LOOPT is a logic zero, the transmitter timing is derived from input REFCLK. When LOOPT is a logic one, the transmitter timing ...
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Register 0102H, 0202H, 0302H, and 0402H: Line Configuration #2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register is used to ...
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Register 0103H, 0203H, 0303H, and 0403H: Receive Line AIS Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register enables various ...
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LOFAIS The LOFAIS bit enables the insertion of path AIS in the Drop direction upon the declaration of LOF. If LOFAIS is a logic one, path AIS is inserted into the indexed channel SONET/SDH frame when LOF is declared. Path ...
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Register 0104H, 0204H, 0304H, and 0404H: Ring Control Bit Type Bit 7 R Bit 6 R Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W SLAIS The SLAIS bit controls the ...
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AUTOLREI The AUTOLREI bit enables the automatic insertion/indication of line REI events to the mate transmitter (local or remote). When AUTOLREI is a logic one and the local ring control port of the indexed channel is disabled, receive B2 errors ...
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Register 0105H, 0205H, 0305H, and 0405H: Transmit Line RDI Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register controls the ...
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LOSLRDI The LOSLRDI bit enables the insertion of line RDI in the transmit stream or the receive ring control port of the indexed channel upon the declaration of LOS. When LOSLRDI is a logic one, the detection of LOS results ...
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Register 0106H, 0206H, 0306H, and 0406H: Section Alarm Output Control #1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register and ...
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LOSSALM The LOSSALM bit allows the LOS alarm indication of the indexed channel to be ORed into the SALMm output. When the LOSSALM bit is set high, the corresponding alarm indication is ORed with other alarm indications of the indexed ...
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Register 0107H, 0207H, 0307H, and 0407H: Section Alarm Output Control #2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register and ...
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Register 0108H, 0208H, 0308H, and 0408H: Section/Line Block Interrupt Status Bit Type Bit 7 — Bit 6 — Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register allows the ...
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CRSII The CRSII bit is set high when one or more of the maskable interrupt sources in the CRSI’s of the indexed channel have been activated. This register bit remains high until the interrupt is acknowledged by reading the CRSI ...
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Register 0109H, 0209H, 0309H, and 0409H: Auxiliary Section/Line Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W The Auxiliary Section/Line Interrupt ...
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OOFE The OOF interrupt enable bit controls interrupt generation on output INTB by the corresponding interrupt status bit in the Auxiliary Section/Line Interrupt Status register of the indexed channel. RDOOLE The receive data out of lock (RDOOL) interrupt enable bit ...
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Register 010AH, 020AH, 030AH, and 040AH: Auxiliary Section/Line Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R The Auxiliary Section/Line Interrupt ...
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Register 010BH, 020BH, 030BH, and 040BH: Auxiliary Signal Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W The Auxiliary Signal Interrupt Enable ...
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Register 010CH, 020CH, 030CH, and 040CH: Auxiliary Signal Status/Interrupt Status Bit Type Bit 7 R/W Bit 6 R/W Bit5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register replicates the receive ...
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Registers 0110H, 0210H, 0310H, and 0410H: CRSI Configuration and Interrupt Status Bit Type Bit 7 R/W Bit 6 R Bit5 R Bit 4 R Bit 3 R Bit 2 R/W Bit 1 R/W Bit 0 R/W This register controls the ...
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RROOLV The receive reference out of lock status indicates the clock recovery PLL is unable to lock to the receive reference (REFCLK). RROOLV should be polled after a power up reset to determine when the CRU PLL is operational. When ...
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Registers 0111H, 0211H, 0311H, and 0411H: CRSI Reserved Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 \R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Reserved The reserved bits must be ...
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Registers 0114H, 0214H, 0314H, and 0414H: RSOP Control and Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W OOFE The OOFE ...
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FOOF The FOOF bit is used to force the RSOP of the indexed channel OOF. When a logic one is written to the FOOF bit location, the RSOP is forced OOF at the next frame boundary, for only one frame. ...
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Registers 0115H, 0215H, 0315H, and 0415H: RSOP Status and Interrupt Bit Type Bit 7 — Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R OOFV The OOFV bit ...
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LOSI The LOSI bit is set high when LOS is declared or removed on the indexed channel. This bit is cleared when this register is read. A clear-on-write version of this register bit may be found in the Auxiliary Section/Line ...
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Registers 0116H, 0216H, 0316H, 0416H: RSOP Section BIP (B1) Error Count #1 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 0117H, ...
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Register 0118H, 0218H, 0318H, and 0418H: RLOP Control and Status Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R Bit 0 R LRDIV The LRDIV bit ...
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BLKBIPO The BLKBIPO (Block BIP Out) bit controls the indication of line BIP (B2) errors reported to the TLOP and receive ring control port blocks of the indexed channel for insertion as REI. When BLKBIPO is logic one, one BIP ...
Page 157
Registers 0119H, 0219H, 0319H, and 0419H: RLOP Interrupt Enable and Status Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R Bit 2 R Bit 1 R Bit 0 R LRDII The LRDII ...
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BIPEE The BIPEE bit is an interrupt enable for the line BIP-24 errors. When BIPEE is a logic one, a line interrupt is generated when a line BIP-24 error (B2) is detected on the indexed channel. LREIE The LREIE is ...
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Registers 011AH, 021AH, 031AH, 041AH: RLOP Line BIP (B2) Error Count #1 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Registers 011BH, ...
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Registers 011DH, 021DH, 031DH, and 041DH: RLOP REI Error Count #1 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Registers 011EH, 021EH, ...
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Registers 0120H, 0220H, 0320H, and 0420H: SSTB Section Trace Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LEN16 The section trace ...
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RTIME The receive section trace identifier (mode 1) mismatch interrupt enable bit (RTIME) controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state from match to mismatch and vice versa ...
Page 163
Registers 0121H, 0221H, 0321H, and 0421H: SSTB Section Trace Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register reports the ...
Page 164
In Mode 2, RTIUV is set low during the stable state that is declared after having received the same 16-byte trace message three consecutive times on the indexed channel (stable trace byte for forty-eight consecutive frames). The stable byte is ...
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Registers 0122H, 0222H, 0322H, and 0422H: SSTB Section Trace Indirect Address Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register supplies ...
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Registers 0123H, 0223H, 0323H, and 0423H: SSTB Section Trace Indirect Data Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register contains ...
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Registers 0124H, 0224H, 0324H, and 0424H: SSTB Reserved Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Reserved The Reserved bits must be ...
Page 168
Registers 0125H, 0225H, 0325H, and 0425H: SSTB Reserved Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R Bit 2 R Bit 1 R Bit 0 R Reserved The Reserved bits must be ...
Page 169
Registers 0126H, 0226H, 0326H, and 0426H: SSTB Section Trace Operation Bit Type Bit 7 R Bit 6 R/W Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 — Bit 0 — RWB The access control ...
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Registers 0130H, 0230H, 0330H, and 0430H: RTOC Overhead Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W The RTOC Control Register is ...
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Registers 0131H, 0231H, 0331H, and 0431H: RTOC AIS Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W The RTOC AIS Control Register ...
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Registers 0140H, 0240H, 0340H, 0440H: RASE Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W SDBERE The SDBERE bit is the ...
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Registers 0141H, 0241H, 0341H, 0441H: RASE Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PSBFV The PSBFV bit indicates the ...
Page 174
SFBERI The SFBERI bit is set high when the signal failure threshold crossing alarm is declared or removed on the indexed channel. This bit is cleared when the RASE Interrupt Status register is read. A clear-on-write version of this register ...
Page 175
Registers 0142H, 0242H, 0342H, 0442H: RASE Configuration/Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W SDCMODE The SDCMODE alarm bit selects the ...
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SFCMODE The SFCMODE alarm bit selects the RASE window size to use for clearing the SF alarm. When SFCMODE is a logic zero the RASE clears the SF alarm using the same window size used for declaration. When SFCMODE is ...
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Registers 0143H, 0243H, 0343H, and 0443H: RASE SF Accumulation Period Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 0144H, 0244H, 0344H, ...
Page 178
Registers 0146H, 0246H, 0346H, and 0446H: RASE SF Saturation Threshold Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 0147H, 0247H, 0347H, ...
Page 179
Registers 0148H, 0248H, 0348H, and 0448H: RASE SF Declaring Threshold Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 0149H, 0249H, 0349H, ...
Page 180
Registers 014AH, 024AH, 034AH, and 044AH: RASE SF Clearing Threshold Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 014BH, 024BH, 034BH, ...
Page 181
Registers 014CH, 024CH, 034CH, and 044CH: RASE SD Accumulation Period Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 014DH, 024DH, 034DH, ...
Page 182
Registers 014FH, 024FH, 034FH, and 044FH: RASE SD Saturation Threshold Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 0150H, 0250H, 0350H, ...
Page 183
Registers 0151H, 0251H, 0351H, and 0451H: RASE SD Declaring Threshold Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 0152H, 0252H, 0352H, ...
Page 184
Registers 0153H, 0253H, 0353H, and 0453H: RASE SD Clearing Threshold Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Registers 0154H, 0254H, 0354H, ...
Page 185
Registers 0155H, 0255H, 0355H, 0455H: RASE Receive K1 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R K1[7:0] The K1[7:0] bits contain the ...
Page 186
Registers 0156H, 0256H, 0356H, 0456H: RASE Receive K2 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R K2[7:0] The K2[7:0] bits contain the ...
Page 187
Registers 0157H, 0257H, 0357H, 0457H: RASE Receive Z1/S1 Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Z1/S1[3:0] The lower nibble of the ...
Page 188
Registers 0180H, 0280H, 0380H, and 0480H: TSOP Control Bit Type Bit 7 — Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LAIS The LAIS bit controls the ...
Page 189
Registers 0181H, 0281H, 0381H, and 0481H: TSOP Diagnostic Bit Type Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 R/W Bit 1 R/W Bit 0 R/W DFP The DFP bit controls the ...
Page 190
Registers 0184H, 0284H, 0384H, and 0484H: TLOP Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LRDI The LRDI bit controls the ...
Page 191
Registers 0185H, 0285H, 0385H, and 0485H: TLOP Diagnostic Bit Type Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 — Bit 0 R/W DB2 The DB2 bit controls the ...
Page 192
Registers 0186H, 0286H, 0386H, and 0486H: TLOP Transmit K1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W K1[7:0] The K1[7:0] bits contain ...
Page 193
Registers 0187H, 0287H, 0387H, and 0487H: TLOP Transmit K2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W K2[7:0] The K2[7:0] bits contain ...
Page 194
Registers 0188H, 0288H, 0388H, and 0488H: TTOC Transmit Overhead Output Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TSLD_SEL The transmit ...
Page 195
Registers 0189H, 0289H, 0389H, and 0489H: TTOC Transmit Overhead Byte Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W NAT_V The NAT_V ...
Page 196
UNUSED_EN The UNUSED_EN bit enables overwriting the unused transport overhead bytes of the indexed channel with an all-ones or all-zeros pattern. When UNUSED_EN is set high, the unused transport overhead bytes are overwritten with an all-ones pattern or all-zeros pattern ...
Page 197
TAPS_SEL The transmit APS select (TAPS_SEL) bit selects the source of the transmit APS (K1/K2) bytes of the indexed channel. When TAPS_SEL is low, the TTOHENm is used as source for the APS bytes. When TAPS_SEL is high, the APS ...
Page 198
Registers 018AH, 028AH, 038AH, and 048AH: TTOC Transmit Z0 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Z0[7:0] Z0[7:0] contains the value ...
Page 199
Registers 018BH, 028BH, 038BH, and 048BH: TTOC Transmit S1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W S1[7:0] The value written into ...
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Register 1001H: Drop Bus STM-1 #1 AU-3 #1 Select Bit Type Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This is a configuration register ...