CY7C373I-100AC Cypress Semiconductor Corporation., CY7C373I-100AC Datasheet
CY7C373I-100AC
Specifications of CY7C373I-100AC
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CY7C373I-100AC Summary of contents
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... UltraLogic™ 64-Macrocell Flash CPLD • Available in 84-pin PLCC and 100-pin TQFP packages • Pin compatible with the CY7C374i Functional Description The CY7C373i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the F 370i™ family of high-density, high-speed CPLDs. Like ...
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... TQFP Top View 100 FOR CY7C373i GND I/O /SDI I/O 48 CLK / ...
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... TM ALL NEW DESIGNS Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C373i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming ...
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... CC OUT MHz GND Min 0. Min 2. Max Max CCINT FOR CY7C373i Ambient V CC Temperature V CCINT 0qC to +70qC 5V r 0.25V 40qC to +85qC 5V r 0.5V Min. Typ. [3] 2.4 [3, 4] [3, 4] [3] [5] 2.0 [5] –0.5 –10 –50 [4] 0 –70 – ...
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... Output Waveform–Measurement Level x 1. 0.5V 2.6V 0. 1.5V 0. the V X 0.5V (d) Test Waveforms Max. EN measured with 35-pF AC Test Load. FOR CY7C373i Min. Max 100-Pin TQFP 84-Lead PLCC 8 8 Max. 100 ALL INPUT PULSES 3.0V 90% 10% GND < (c) Unit pF pF Unit nH Unit ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... Min. Max. 8 125 + t ), 1/( [7] 10 [7] 12 [1] 16 [7] 10 [7] 12 [1] 16 500 FOR CY7C373i 7C373i–83 7C373i–66 7C373i–100 7C373iL-83 7C373iL–66 Min. Max. Min. Max. Min 83.3 66.6 50 ...
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... INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ALL NEW DESIGNS PDL t ICS PDL t WH CY7C373i SCS t ICO t WL Page ...
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... OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ALL NEW DESIGNS t ICOL t ICS CY7C373i t PDLL Page ...
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... CY7C373i–100AC CY7C373i–100JC CY7C373i–100AI CY7C373i–100JI 83 CY7C373i–83AC CY7C373i–83JC CY7C373i–83AI CY7C373i–83JI CY7C373iL–83JC 66 CY7C373i–66AC CY7C373i–66JC CY7C373i–66AI CY7C373i–66JI CY7C373iL–66JC Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ALL NEW DESIGNS t ER Package Package ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000 TM FOR ALL NEW DESIGNS 84-Lead Plastic Leaded Chip Carrier J83 370, F 370i, ISR, UltraLogic, Warp Professional, and Warp Enterprise LASH LASH CY7C373i 51-85048-*B 51-85006-*A Page ...
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... Document History Page Document Title: CY7C373i UltraLogic™ 64-Macrocell Flash CPLD Document Number: 38-03030 REV. ECN NO. Issue Date ** 106375 09/17/01 *A 213375 See ECN Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ALL NEW DESIGNS Orig. of Change SZV Change from Spec number: 38-00495 to 38-03030 FSG Added note to title page: “ ...