2242CKTC

Manufacturer Part Number2242CKTC
ManufacturerFairchild Semiconductor
2242CKTC datasheet
 
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
Page 4/16:

Pin Descriptions

Download datasheet (91Kb)Embed
PrevNext
PRODUCT SPECIFICATION

Pin Descriptions

Pin Number
Pin Name
PLCC
MQFP
Dedicated Timing Controls
CLK
42
36
Clock . The chip operates from a single-phase master clock, to whose rising
edges all timing parameters are referenced. All internal registers are strobed on
every rising edge of CLK, although the output register is strobed on alternate
rising edges during decimation. In all modes, the frequency applied to CLK is the
higher of the input and output data sampling rates. During interpolation, the chip
reads its input bus on alternate rising edges of CLK.
SYNC
43
37
Synchronization . During interpolation, the chip accepts input data on alternate
rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is
HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will
accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either
held LOW or fed a square wave of half the CLK frequency, the part will continue
to accept data on odd-numbered CLK edges and to stuff zeroes on even-
numbered edges. Similarly, during decimation, the output data change only on
alternate clock cycles. If the user operates SYNC as above, each even-
numbered rising edge of CLK will trigger a change in the output. In all other
modes, the state of SYNC doesn’t affect operation of the chip.
Dedicated Data Input Port
SI
40,
34,
Input Data . A 12-bit two’s complement or unsigned input word is registered by
11-0
37-30,
31-24,
the rising edges of CLK. SI
27-25
21-19
Dedicated Data Output Port
SO
4-11,
42-44,
Output Data MSBs . When OE is LOW, the 12 most significant bits of the filter’s
15-0
14-21
1-5,
output emerge here, following each rising edge of CLK. The format may be two’s
8-15
complement, unsigned, or inverted offset binary. Bits SO
input bits SI
underflows in the output data.
Dual Function Data Output/Control Input Pins
SO
Output Data . These pins serve as data outputs when RND
3-2
RND
SO
Output Data 2
1
either RND
SO
Output Data LSB . This pin is a data output if and only if all RND bits are LOW.
0
Otherwise, it augments the data I/O format controls.
Dedicated Static Controls (Set state before first desired data input.)
INT, DEC
44, 1
38, 39
Interpolate and Decimate. Jointly with SO
overall operating mode, as discussed earlier in Table 1
TCO
2
40
Output format control. When TCO is HIGH, the output data are in two’s
complement format. When TCO is LOW, they are inverted offset binary, unless
SO
RND
22-24
16-18
Round and output tristate. Selects output rounding position and active bus
2-0
width 8-16 bits. All outputs at and below the rounding bit position are tristated,
allowing the 4 LSBs to become control inputs.
Active, Asynchronous Control
OE
3
41
Output enable. LOW activates output bus from SO
as chosen by RND
as are all drivers when OE is HIGH.
4
Pin Function Description
is the LSB.
0
, respectively. An on-chip limiter prevents overflows and
11-0
is HIGH, they become additional filter mode controls (Table 1).
2
nd
LSB. This pin is a data output when RND
or RND
is HIGH, it becomes an additional rounding control.
2
1
is HIGH and RND is nonzero, in which case they are unsigned.
0
. All drivers at and below the rounding point are disabled,
2-0
TMC2242C
correspond to
15-4
is LOW. When
2
are LOW. When
2-1
1
2
, these bits select the chip’s
3-2
down to the effective LSB,
15