MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
512K x 9 Bit Separate I/O
Synchronous Fast Static RAM
512K words of 9 bits. It features separate TTL input and output buffers, which
drive 3.3 V output levels, and incorporates input and output registers on–board
with high speed SRAM. It also features transparent–write and data pass–through
capabilities.
external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data
output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are
registered on the rising edge of clock (K).
nous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
Ball Grid Array) package.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA FAST SRAM
REV 3
12/23/97
The MCM67Q909 is a 4M–bit static random access memory, organized as
The synchronous design allows for precise cycle control with the use of an
The control pins (E, W, G) function differently in comparison to most synchro-
The pass–through function is always enabled. E high disables the write to the
The MCM67Q909 is available in an 86–bump surface mount PBGA (Plastic
Motorola, Inc. 1997
Single 5 V
Fast Cycle Time: 12 ns Max
Single Clock Operation
TTL Input and Output Levels (Outputs LVTTL Compatible)
Address, Data Input, E, W, and G Registers On–Chip
83 MHz Maximum Clock Cycle Time
Self–Timed Write
Separate Data Input and Output Pins
Transparent–Write and Pass–Through
High Output Drive Capability: 50 pF/Output at Rated Access Time
Boundary Scan Implementation
PBGA Package for High Speed Operation
5% Power Supply
A
B
E
F
G
H
K
C
D
J
V CC
V SS
V SS Q7
A16
D7
D5
D3
Q1
1
V SS
A13
A12
A14
Q3
A15
D1
Q5
A0 – A18
E
W
G
D0 – D8
Q0 – Q8
K
SCK
SE
SDI
SDO
V CC
V SS
NC
E
2
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. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
V SS
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
V SS
V SS
V SS
A10
A11
MCM67Q909
A17
A18 V SS
PIN ASSIGNMENT
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
G
3
W
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
V SS V SS V SS V SS
V SS
SCK
V CC
V SS V SS V SS V SS
V SS V SS V SS V SS
V SS V SS V SS V SS
V SS
TOP VIEW
86–BUMP
K
4
PIN NAMES
V SS
V CC
V SS V SS V SS
V SS
SDI
A9
5
SDO
V SS
A6
SE
A8
6
Order this document
+ 5 V Power Supply
86 BUMP PBGA
CASE 896A–02
Scan Data Output
by MCM67Q909/D
Scan Clock Input
V SS
Scan Data Input
A2
A7
A5
A4
No Connection
7
Output Enable
MCM67Q909
Address Input
Data Outputs
Not to Scale
Write Enable
Scan Enable
Chip Enable
Data Inputs
Clock Input
V SS
V SS
Q8
Q6
D2
D0
A0
D4
A1
A3
8
Ground
V CC
V SS
V SS
D8
D6
Q4
Q2
Q0
9
1