ACS8527 Semtech Corporation, ACS8527 Datasheet

no-image

ACS8527

Manufacturer Part Number
ACS8527
Description
Manufacturer
Semtech Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ACS8527
Manufacturer:
PERI
Quantity:
50
Part Number:
ACS8527
Manufacturer:
SEMTECH
Quantity:
300
The ACS8527 is a highly integrated, single-chip, MUX with
PLL solution for protection switching between two SECs
(SDH/SONET Equipment Clocks) from Master and Slave
SETS (Synchronous Equipment Timing Source) clock
cards, for line cards in a PDH, SONET or SDH Network
Element. The ACS8527 has fast activity monitors on the
inputs and will raise a flag on a pin if there is a loss of
activity on the currently selected input. The protection
switching between the input reference clock sources is
controlled by an external pin.
The ACS8527 has two SEC reference clock input ports,
configured for expected frequency by setting hardware
pins.
The ACS8527 can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from a
backplane into a 155.52 MHz clock for local line cards.
The ACS8527 generates two independent SEC clock
outputs, one on a LVDS port and one on a TTL/CMOS port,
at spot frequencies configured by hardware pins. The spot
frequencies range from 1.544 MHz up to 155.52 MHz.
The ACS8527 also provides an 8 kHz Frame Sync output
and 2 kHz Multi-Frame Sync output.
Figure 1 Block Diagram of the ACS8527 MUXPLL
Revision 4.01/June 2006 © Semtech Corp.
Description
ADVANCED COMMUNICATIONS
Block Diagram
ADVANCED COMMUNICATIONS
2 x SEC TTL inputs
SEC Inputs:
Input Frequencies
8kHz
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
SONSDHB
IP_FREQ
SRCSW
SEC1
SEC2
TRST
TMS
TDO
TCK
TDI
1149.1
SEC Port
Selector
IEEE
JTAG
Input
DPLL
Generator
TCXO or
Clock
Chip
XO
FINAL
FINAL
Page 1
Line Card Protection Switch for PDH, SONET
Features
APLL
Line card protection switch - partners Semtech SETS
devices for Stratum 3E/3/4E/4 PDH, SONET or SDH
applications
High performance DPLL/APLL solution
Output jitter compliant to STM-1
Two independent SEC inputs ports (TTL)
Four independent output ports:
I/O frequencies configurable via hardware pins:
Digital Holdover mode on input failure
“Loss of activity” on selected input flagged on
dedicated pin
Source switch under external hardware control
7O Hz (acquisition) /35 Hz (locked) DPLL bandwidth
Output clock phase continuity to GR-1244-CORE
Single 3.3 V operation, 5 V I/O compatible
IEEE 1149.1 JTAG Boundary Scan is supported
Operating temperature (ambient) of -40 to +85°C
Available in LQFP 64 package
Lead (Pb)-free version available (ACS8527T). RoHS
and WEE compliant
Two clock ports: one LVDS, one TTL
Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync
TTL I/O ports: spot frequencies 1.544 MHz to
77.76 MHz
LVDS output port: spot frequencies 19.44 MHz to
155.52 MHz
OP_FREQ1
OP_FREQ2
Frequency
Selection
Output
Port
LOS_ALARM
Output Frequencies/MHz
01 Output:
19.44
25.92
34.368 (E3)
38.88
44.736 (DS3)
51.84
77.76
155.52
SEC Outputs:
01 (LVDS)
02 (TTL)
Sync Outputs:
MFrSync 2 kHz (TTL)
FrSync 8 kHz (TTL)
ACS8527 MUXPLL
F8527D_001BLOCKDIA_01
02 Output:
1.544
2.048
3.088
19.44
25.92
34.368 (E3)
38.88
44.736 (DS3)
51.84
77.76
or SDH Systems
DATASHEET
www.semtech.com
[13]

Related parts for ACS8527

ACS8527 Summary of contents

Page 1

... LVDS port and one on a TTL/CMOS port, at spot frequencies configured by hardware pins. The spot frequencies range from 1.544 MHz up to 155.52 MHz. The ACS8527 also provides an 8 kHz Frame Sync output and 2 kHz Multi-Frame Sync output. Block Diagram ...

Page 2

... Maximum Ratings ........................................................................................................................................................................... 11 Operating Conditions ...................................................................................................................................................................... 11 DC Characteristics .......................................................................................................................................................................... 11 Jitter Performance .......................................................................................................................................................................... 13 Input/Output Timing ....................................................................................................................................................................... 15 Package Information .............................................................................................................................................................................. 16 Thermal Conditions......................................................................................................................................................................... 17 Application Information .......................................................................................................................................................................... 18 References .............................................................................................................................................................................................. 19 Abbreviations .......................................................................................................................................................................................... 19 Notes ....................................................................................................................................................................................................... 20 Trademark Acknowledgements ............................................................................................................................................................. 20 Revision Status/History ......................................................................................................................................................................... 21 Ordering Information .............................................................................................................................................................................. 22 Disclaimers...................................................................................................................................................................................... 22 Contacts........................................................................................................................................................................................... 22 Revision 4.01/June 2006 © Semtech Corp. Table of Contents FINAL Page 2 ACS8527 MUXPLL DATASHEET Page www.semtech.com ...

Page 3

... ADVANCED COMMUNICATIONS Pin Diagram Figure 2 ACS8527 Pin Diagram 1 AGND1 2 IC1 3 AGND2 4 VA1+ 5 LOS_ALARM 6 REFCLK 7 DGND1 8 VD1+ 9 VD2+ 10 DGND2 1 11 DGND3 12 VD3+ 13 SRCSW 14 VA2+ 15 AGND3 16 IC2 Revision 4.01/June 2006 © Semtech Corp. ACS8527 MUXPLL FINAL ACS8527 MUXPLL Page 3 DATASHEET 48 PORB 47 IC9 46 O1_FREQ1 ...

Page 4

... Supply Ground: Digital ground for logic. - Supply Ground: Digital ground for differential output pins 19 and 20. - Supply Ground: Analog grounds TTL input with pull-up resistor, TTL = TTL input with pull-down resistor. D Type - Internally Connected: Leave to float. - Not Connected: Leave to float Page 4 ACS8527 MUXPLL DATASHEET Description Description www.semtech.com ...

Page 5

... JTAG Input: Serial test data Input. Sampled on rising edge of TCK not used. D TTL/CMOS Output Reference: Programmable, default 19.44 MHz. U TTL Output O1 Frequency Select: Frequency select for output O1. TTL SONET or SDH frequency select: Sets the device for SONET or SDH frequencies D on power-up/reset. Page 5 ACS8527 MUXPLL DATASHEET Description www.semtech.com ...

Page 6

... Line Cards in a SONET or SDH Network Element. The ACS8527 has fast activity monitors on the SEC clock inputs. The ACS8527 is a standalone part where all input and output frequencies are set by external control using the IP_FREQ, OP_FREQ and SONSDHB pins. The SRCSW pin is used to select one of the two SEC inputs to lock to ...

Page 7

... Application Schematic” on page 18. SEC Selection - SRCSW pin After the ACS8527 has been initialized (see previous “Initialization” section), then the value of SRCSW pin directly selects either SEC1 (SRCSW High) or SEC2 (SRCSW Low). The frequency tolerance of SEC1 and SEC2 is ± ...

Page 8

... ADVANCED COMMUNICATIONS DPLL Acquisition Bandwidth The ACS8527 DPLL has a preset acquisition bandwidth of 70 Hz. DPLL Input Tracking (Locked) Bandwidth The ACS8527 DPPL has a preset tracking bandwidth of 35 Hz. This bandwidth setting corresponds to the -3 dB jitter attenuation point on the ACS8527’s jitter transfer characteristic. ...

Page 9

... Local Oscillator Clock The Master system clock on the ACS8527 should be provided by an external clock oscillator of frequency 12.800 MHz. Wander on the local oscillator clock will not have a significant effect on the output clock whilst in Locked mode. Prior to initial lock or in Digital Holdover mode, wander on the crystal is more significant ...

Page 10

... ADVANCED COMMUNICATIONS Electrical Specifications JTAG The JTAG connections on the ACS8527 allow a full boundary scan to be made. The JTAG implementation is [4] fully compliant to IEEE 1149.1 , with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support INTEST ...

Page 11

... OUT T - -50 STOR Symbol Minimum Typical V 3 3.0 3.3/5.0 DD5V T - TOT Symbol Minimum Typical Page 11 ACS8527 MUXPLL DATASHEET Maximum Units 3.6 V 5 +150 C Maximum Units 3.3 3.6 5 +85 110 200 mA 360 720 mW Maximum Units - - - 0.8 µ www.semtech.com V V ...

Page 12

... 12 Symbol Minimum Typical 2 Symbol Minimum Typical V - OHLVDS V 0.885 OLLVDS V 250 ODLVDS Page 12 ACS8527 MUXPLL DATASHEET Maximum Units - - kΩ µΑ - 120 Maximum Units - - kΩ - 47.5 kΩ µA - 120 Maximum Units - 0.4 V ...

Page 13

... Hz - 1.3 MHz 65 kHz - 1.3 MHz 100 kHz 100 kHz 100 kHz Page 13 ACS8527 MUXPLL DATASHEET Typical Maximum Units - 25 - 1.275 Fully Programmable Output Frequencies F8522D_025LVDS_02 Jitter Spec ACS8527 Jitter UI UI (TYP) 0.1 p-p 0.073 p-p 0.05 p-p 0.012 p-p 0.1 p-p 0.069 p-p 0.05 p-p 0.011 p-p 0.5 p-p 0.083 p-p 0.075 p-p 0.073p-p 0.5 p-p 0.012 p-p 0.2 p-p 0.012 p-p 0.05 p-p ...

Page 14

... GR-1244-CORE for 1.544 MHz Note...This table is only for comparing the ACS8527 output jitter performance against values and quoted in various specifications for given conditions. It should not be used to infer compliance to any other aspects of these specifications. Revision 4.01/June 2006 © Semtech Corp. ...

Page 15

... DS1 (1.544 MHz) E1 (2.048 MHz) +4.7 ± 1.5 ns DS3 (44.736 MHz) +4.6 ± 1 (34.368 MHz) 19.44 MHz +3.0 ± 1.5 ns 25.92 MHz +5.3 ± 1.5 ns 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz Page 15 ACS8527 MUXPLL DATASHEET Min/Max Phase Alignment (FrSync Alignment switched on) -1.2 ± 0.5 ns -1.2 ± 1.25 ns -1.2 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns -3.75 ± 1.25 ns F8527D_021IP_OPTiming_04 www ...

Page 16

... ADVANCED COMMUNICATIONS Package Information Figure 6 LQFP Package Revision 4.01/June 2006 © Semtech Corp. ACS8527 MUXPLL FINAL Page 16 DATASHEET www.semtech.com ...

Page 17

... All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 7 Typical 64-Pin LQFP Package Landing Pattern Revision 4.01/June 2006 © Semtech Corp. ACS8527 MUXPLL FINAL Page 17 DATASHEET ...

Page 18

... DGND3 14 VA2+ 15 AGND3 IC2 10R 100nF AGND VDD BSH205 FrSync MFrSync O1P O1N DGND DGND2 Page 18 ACS8527 MUXPLL VDD3 VDD2 VDDA AGND DGND2 DGND3 DGND C14 VDD 100nF PORB C13 1nF 48 PORB 47 IC9 DGND 46 VDD O1_FREQ1 45 O1_FREQ0 44 NC1 ...

Page 19

... Oscillator UI Unit Interval WEEE Waste Electrical and Electronic Equipment (directive) XO Crystal Oscillator Revision 4.01/June 2006 © Semtech Corp. ACS8527 MUXPLL FINAL References [1] AT & T 62411 (12/1990) ACCUNET ® T1.5 Service description and Interface Specification [2] ETSI ETS 300 462-3, (01/1997) Transmission and Multiplexing (TM); Generic requirements for synchronization networks ...

Page 20

... AT & T. C-MAC is a registered trademark of C-MAC MicroTechnology - a division of Solectron Corporation. ICT Flexacom is a registered trademark of ICT Electronics. Telcordia is a registered trademark of Telcordia Technologies. Revision 4.01/June 2006 © Semtech Corp. ACS8527 MUXPLL FINAL Notes Page 20 DATASHEET www.semtech.com ...

Page 21

... This is a FINAL release (Revision 4.01) of the ACS8527 datasheet. Changes made for this document revision are given in Table 16, together with a summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions ...

Page 22

... ACS8527 MUXPLL Line Card Protection Switch for PDH, SONET or SDH Systems ACS8527T Lead (Pb)-free package version of ACS8527; RoHS and WEEE compliant. Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. ...

Related keywords