CS4237B-JQ Cirrus Logic, Inc., CS4237B-JQ Datasheet

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CS4237B-JQ

Manufacturer Part Number
CS4237B-JQ
Description
Manufacturer
Cirrus Logic, Inc.
Datasheet

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Part Number:
CS4237B-JQ
Manufacturer:
CRYSTAL
Quantity:
246
Advanced Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
http://www.cirrus.com
CrystalClear
DACK<A:C>
DRQ<A:C>
SA<12:15>
IOCHRDY
IRQ<A:F>
SA<11:0>
(CDROM)
(Modem)
Integrated SRS
Compatible with Sound Blaster
Pro
Advanced MPC3-Compliant Input and Output Mixer
Enhanced Stereo Full Duplex Operation
Dual Type-F DMA Support
Industry Leading Delta-Sigma Data Converters
Fully Plug-and-Play ISA Compatible
3.3 V or 5 V ISA Bus Operation
Programmable Power Management
Hardware Master Volume Control
Enhanced Digital Gameport
CS9236 Wavetable Digital Audio Interface
MPU-401 MIDI Interface
Consumer IEC-958 Digital Output (S/PDIF)
CS4236/CS4232/CS4231 Register Compatible
SD<7:0>
AEN
IOW
IOR
TM
, and Windows Sound System
XTALI
OSCILLATOR
CD-ROM, Modem, or
Upper Address Bits
INTERFACE
CODEC
Decode
PLUG
PLAY
AND
BUS
Logic
REG
ISA
XTALO
I/F
®
Config
DMA
IRQ
IO
VREF REFFLT
SERIAL
SHIFT
3D Sound Technology
VREF
JOYSTICK
JOYSTICK
DIGITAL/
ANALOG
LOGIC
Advanced Audio System with 3D Sound
LINEAR
A-LAW
ADPCM
-LAW
LINEAR
A-LAW
ADPCM
-LAW
TM
Synthesizer
, Sound Blaster
FM
SERIAL PORT
WAVETABLE
TM
CS9236
SERIAL
PORT
This document contains information for a new product. Cirrus
Logic, Inc. reserves the right to modify this product without notice.
Attenuation
Loopback
Monitor
DSP SERIAL
DIGITAL
SERIAL
MIXER
PORT
DSP
PORT
L/RFILT
Copyright
S/PDIF
General Description
The CS4237B is a single chip multimedia audio system
that provides compatibility with the Microsoft Windows
Sound System standard and will run software written to
the Sound Blaster and Sound Blaster Pro interfaces.
The CS4237B is fully compliant with Microsoft’s PC’ 97
and WHQL audio requirements. The product includes
an internal FM synthesizer and Plug-and-Play external
interfaces for Wavetable, CD-ROM, and modem de-
vices. In addition, the CS4237B includes hardware
master volume control pins as well as extensive power
management and SRS 3D sound technology.
ORDERING INFORMATION:
GAIN
(All Rights Reserved)
CS4237B-KQ
CS4237B-JQ
INPUT MIXER
MPU-401
Cirrus Logic, Inc. 1997
FIFOS
UART
MIDI
with
OUTPUT MIXER
SCS/
UP
Synth. Interface
Volume Control
or Hardware
DOWN
SINT/
GAIN
100 pin TQFP, 14x14x1.4mm
100 pin TQFP, 14x14x1.4mm
CS4237B
MUTE
Registers
SBPRO
WSS
GAIN
Peripherals
EEPROM
Interface
BRESET
ATTN.
GAIN
GAIN
GAIN
GAIN
&
DS213PP4
SEP ’97
L/RLINE
L/RAUX1
L/RAUX2
CMAUX2
L/RMIC
MIN
MOUT
L/ROUT
XIOW
XIOR
XD<7:0>
XA<2:0>
1

Related parts for CS4237B-JQ

CS4237B-JQ Summary of contents

Page 1

... WHQL audio requirements. The product includes an internal FM synthesizer and Plug-and-Play external interfaces for Wavetable, CD-ROM, and modem de- vices. In addition, the CS4237B includes hardware master volume control pins as well as extensive power management and SRS 3D sound technology. ORDERING INFORMATION: CS4237B-JQ CS4237B-KQ L/RFILT INPUT MIXER GAIN Loopback Monitor ...

Page 2

... Sound Blaster and Sound Blaster Pro are registered trademarks of Creative Labs. Adlib is a registered trademark of Adlib Corporation. The word SRS and the SRS Symbol The CS4237B incorporates the SRS (Sound Retrieval System) under license from SRS Labs, Inc. 2 TABLE OF CONTENTS WSS CODEC SOFTWARE DESCRIPTION .......79 Calibration ...

Page 3

... Notes: 1. This specification is guaranteed by characterization, no production testing. 2. MGE = 1 (see WSS Indirect Reg I0, I1). *Parameter definitions are given at the end of this data sheet. Specifications are subject to change without notice. DS213PP4 °C; VA, VD1, VDF1-VDF4 = +5V A CS4237B-JQ Symbol Min (Note 1) 16 (Note 1) - Line Inputs ...

Page 4

... Total Operating Total Power Down Power Supply Rejection 1 kHz Notes 100 pF load current only. If dynamic loading exists, then the voltage reference output must be buffered or the performance of ADCs and DACs will be degraded. 4 (Continued) CS4237B-JQ Symbol Min (Note 1) 16 (Note 1) - All Outputs ...

Page 5

... When VD1 is powered from 3.3 Volts, all ISA bus input pins, except DRQA, must also be 3.3 Volts. DRQA is internally powered from the VDF supply and must have a 5 Volt interface. To use DRQA in a 3.3 Volt application, a level translator is needed. DS213PP4 CS4237B-JQ Min LINE, AUX1, AUX2 - ...

Page 6

... Mono ADPCM format ADCs DACs (T = 25°C ; VA, VDF1-VDF4 = 5V, VD1 = 5V/3V; A Symbol Digital Inputs V IH XTALI -24 - 4.0 mA (Digital Inputs) (High-Z Digital Outputs) CS4237B Min Typ Max Units 0 - 0.40xFs -1 0.1 0.40xFs - 0.60xFs 0.60xFs - - 10/Fs ...

Page 7

... VA, VD1, VDF1-VDF4 = +5V; outputs loaded with 30pF A Symbol HD:STA t LSCL t HSCL t SU:STA t HD:DAT t SU:DAT (Note SU:STO HSCL t LSCL HD:STA t HD:DAT PROM 2-Wire Interface Timing CS4237B Min Max 0 3.5 4.0 - 4.7 - 4 250 - - 1 - 300 4 SU:DAT t SU:STO Units ...

Page 8

... DKHDa t DKHDb (Note 1) t RESDRV (Note INIT (Note 1, 10) t EEPROM (Notes 1, 11) (Notes 1, 11) (Notes 1, 11) (Note 1) Fs (Note 1) t PD1 (Note 1) t PD2 (Note (Note CS4237B Min Max Units ...

Page 9

... DSP Serial Port Timing t t DKSUa DRHD t STW t RDDV 8-Bit Mono DMA Read/Capture Cycle t RESDRV t t INIT EEPROM EEPROM read Reset Timing t h1 MSB, Left MSB, Left t DKHDb t DHD1 Codec responds to ISA activity CS4237B 9 ...

Page 10

... SD<7:0> DKSUb DRHD t STW 8-Bit Mono DMA Write/Playback Cycle t BWDN LEFT/LOW BYTE 8-Bit Stereo or 16-Bit Mono DMA Cycle t BWDN LEFT/LOW LEFT/HIGH BYTE BYTE 16-Bit Stereo or ADPCM DMA Cycle CS4237B t DKHDa t t DHD2 WDSU RIGHT/HIGH BYTE RIGHT/LOW RIGHT/HIGH BYTE BYTE DS213PP4 ...

Page 11

... DRQ<> t SUDK1 DACK<> IOR SD<7:0> SA<> AEN DRQ<> t SUDK1 DACK<> IOW SD<7:0> SA<> AEN DS213PP4 t SUDK2 t t RDDV DHD1 t ADSU I/O Read Cycle t SUDK2 t STW t t WDSU DHD2 t ADSU I/O Write Cycle CS4237B t ADHD t ADHD 11 ...

Page 12

... CDROMs with I/O locations and sup- ports both the base address and the alternate base address, an interrupt, and a DMA channel. Al- though this logical device is listed as a CDROM, any external device that fits within the resources listed above may be substituted. CS4237B DS213PP4 ...

Page 13

... SD<7:0> lines while the host asserts the IOR strobe. Write cycles require the host to assert data on the SD<7:0> lines and strobe the IOW signal. Data is latched on the ris- ing edge of the IOW strobe. CS4237B Logical Device 5 Logical Device 4 Modem: CDROM: ...

Page 14

... The DMA request signal can be asserted at any time. Once asserted, the DMA request will re- main asserted until a complete DMA cycle occurs. A complete DMA cycle consists of one or more bytes depending on which device inter- nal to the part is generating the request. CS4237B DS213PP4 ...

Page 15

... Data port (020Bh - 03FFh). The read data port is relocated automatically by PnP software when a conflict occurs. The configuration sequence is as follows: 1. Host sends a software key which places all PnP cards in the sleep state (or Plug-and- Play mode). 2. The Crystal part is isolated from the system using an isolation sequence. CS4237B 15 ...

Page 16

... ASCII. (See the PnP Spec for more information) 42h - Oem ID. A unique Oem ID must be ob- tained from Crystal for each unique Crystal product used. 37h - Crystal product ID for the CS4237B FFh, FFh, FFh, FFh - Serial number. This can be modified by each OEM to uniquely identify their card. ??h - Checksum. ...

Page 17

... Appendix A. Loading Firmware Patch Data An external E up sequence that stores Hardware Configuration and PnP data, and firmware patch data. The part contains RAM and ROM to run the core proces- CS4237B PROM section for more information 2 2 PROM interface and E 2 ...

Page 18

... CS4237B Sub optimal Sub optimal Choice 1 Choice 2 ANSI ID = WSS/SB 534-FFCh 4 11, 12, 15 (SB share (SB share) ---- 388-3F8h 4/8 ---- 220-300h 16/32 ANSI ID = GAME ANSI ID = CTRL ANSI ID = MPU 330-3E0h 2/8 ---- DS213PP4 ...

Page 19

... CTRLbase+5. The part will not par- ticipate in any future PnP cycles. The Crystal Key can also be disabled by writing a 56h to CTRLbase+5. xxh is logical device number: 0-5 high byte , low byte high byte , low byte high byte , low byte (33h, 00h deactivates a device) CS4237B 19 ...

Page 20

... CDROM address decode, ACDbase. See the CDROM Interface section for more details on ACDbase 000 - ACDCS low for 1 byte 001 - ACDCS low for 2 bytes 011 - ACDCS low for 4 bytes 111 - ACDCS low for 8 bytes xxx - all others, RESERVED CS4237B CM2 CM1 CM0 DS213PP4 ...

Page 21

... IRQ A/B Selection: Lower nibble = A, Upper nibble = B. IRQ C/D Selection: Lower nibble = C, Upper nibble = D. IRQ E/F Selection: Lower nibble = E, Upper nibble = F. DMA A/B Selection: Lower nibble = A, Upper nibble = B. 2 PROM and are not used in the Hostload mode. Table 2. Hardware Configuration Data CS4237B 2 PROM exists. 2 PROM 2 PROM ...

Page 22

... D6 MM2 MM1 MM0 IHCD IHS ACDB7D SDD VCEN IHM CKD PKD IHS IHCD CS4237B PKD CKD IHM VCEN SDD Alternate CDROM, data Bit 7 Disable. When set, SD7 is held in a high impedance state when reading from ACDbase+1 (only this one address). ...

Page 23

... FM must be provided on the external LINE analog inputs CB5 CB4 CB3 CB2 Code Base Byte. Determines the code 2 base located in the E PROM. If not correct, the Firmware code after the PnP resource data is not loaded. 0x0B - CS4237B 0x43 - CS4236 CS4237B D1 D0 CB1 CB0 23 ...

Page 24

... Serial Identifier as being a user de- fined serial number. The E change the user section of the identifier, store default resource data for PnP, Hardware Con- figuration data specific to the Crystal part, and firmware patches to upgrade the core processor functionality. CS4237B 2 PROM loads. 2 PROM is used to DS213PP4 ...

Page 25

... XD0 because open-drain output. Use the guidelines in the Bank Part Read Start Address Address Acknowledge Figure 3. EEPROM Format CS4237B 2 PROM would be 388 bytes. The 2 PROM supported is 2k bytes. 2 PROM exists accessed by 2 PROM serial interface. When the 2 2 PROM ...

Page 26

... When MODE 2 is selected, the bit IA4 in the Index Address register (R0) will be decoded as a valid index pointer providing 16 additional registers and increased functionality over the CS4248. To reverse the procedure, set the CMS1,0 bits to 00 and the part will resume operation in CS4237B DS213PP4 ...

Page 27

... WSS Codec and the bus. The WSS Codec is responsible for asserting a request sig- nal whenever the Codec’s internal buffers need updating. The bus responds with an acknowledge signal and strobes data to and from the Codec, 8 bits at a time. The WSS Codec keeps the request CS4237B 27 ...

Page 28

... DMA request occurs on DMA channel select 0 for the WSS Codec. (In MODEs 2 and 3, the capture data format is al- ways set in register I28.) If both playback and capture are enabled, the default will be playback. SDC does not have any affect when using PIO accesses. CS4237B DS213PP4 ...

Page 29

... Extended Register Access (X regs) I24 Alternate Feature Status I25 Compatibility ID I26 Mono Input & Output Control I27 Reserved I28 Capture Data Format I29 Reserved I30 Capture Upper Base Count I31 Capture Lower Base Count Table 4. WSS Codec Indirect Registers CS4237B Register Name 29 ...

Page 30

... DIV4 DIV3 XA2 XA1 XA0 MOM MBY - - - - FMT0 C/L S CUB6 CUB5 CUB4 CLB6 CLB5 CLB4 CS4237B IA3 IA2 IA1 ID3 ID2 ID1 PU/L PL/R PRDY CD3/PD3 CD2/PD2 CD1/PD1 LAG3 LAG2 LAG1 RAG3 RAG2 RAG1 LX1G3 LX1G2 LX1G1 RX1G3 RX1G2 ...

Page 31

... Linear, 16-bit two’s complement, Little Endian 1 1 A-Law, 8-bit companded 0 1 ADPCM, 4-bit, IMA compatible 1 0 Linear, 16-bit two’s complement, Big Endian Table 11. WSS Codec Data Format CS4237B Level 12.0 dB 10.5 dB 9.0 dB 7.5 dB 6.0 dB 4.5 dB 3.0 dB 1.5 dB 0.0 dB -1.5 dB -3.0 dB -4 ...

Page 32

... KHz 8 50.40 KHz - - 21 50.40 KHz 22 48.10 KHz 23 46.01 KHz 24 44.10 KHz 25 42.36 KHz 26 40.70 KHz 27 39.20 KHz 28 37.80 KHz - - 255 4.150 KHz 16 X 255 CS4237B 353 529 617 1058 1764 2117 2558 - - - 353 529 617 1058 1764 2117 2558 ...

Page 33

... During initialization and software power down of the WSS Codec, this register can NOT be written and is always read 10000000 (80h) Status Register (WSSbase+2, R2, Read Only CU/L CL/R INT PRDY CS4237B ID5 ID4 ID3 ID2 ID1 Indexed Data register: These bits are the indirect register referenced by the Indexed Address register (R0) ...

Page 34

... Writes to this register sends data to the Playback Data register. Reads from this register will receive data from the Capture Data register. During initialization and software power down of the WSS Codec, this register CANNOT be written and is always read 10000000 (80h) CS4237B DS213PP4 ...

Page 35

... Default = 000x0000 D7 D6 LSS1 LSS0 LMGE LAG3-LAG0 res LMGE LSS1-LSS0 PD2 PD1 PD0 CS4237B res LAG3 LAG2 LAG1 Left ADC Gain. The least significant bit represents +1.5 dB, with 0000 = 0 dB. See Table 7. Reserved. Must write 0. Could read ...

Page 36

... RX1BM RX1IM RX1OM RAUX1 (Line In) CS4237B the gain stage, is muted. In MODEs 1 & 2, this bit is not avail- able and internally forced on (muted). Left Auxiliary #1 Mute. When set to 1, the left Auxiliary #1 input, LAUX1, to the output mixer through the gain stage, is muted. ...

Page 37

... The total range -94.5 dB. See Table 6. Reserved. Must write 0. Could read Left PC Wave Mute. When set, the left PCM input to the digital mixer summer will be muted. CS4237B To Output Mixer To Input Mixer D1 D0 LDG1 ...

Page 38

... S CFS1 CFS0 C2SL CS4237B See Table below. Clock Frequency Divide Select: These bits select the audio sample fre- quency for both capture and playback. The actual audio sample frequency depends on which clock base (C2SL) is selected. Note that these bits can be disabled by setting SRE in I22 or IFSE in X11 ...

Page 39

... D1 D0 SDC CEN PEN PPIO CPIO CS4237B Capture Enabled. This bit enables the capture of data. The WSS Codec will generate a DRQ and respond to DACK signal when CEN is enabled and CPIO=0. If CPIO=1, CEN en- ables PIO capture mode. CEN may be set and reset without setting the MCE bit ...

Page 40

... Error Status and Initialization (I11, Read Only) Default = 00000000 D7 D6 COR PUR ORL1-ORL0 ORR1-ORR0 DRS CS4237B 00 - 12kHz < Fs 24kHz > 24kHz 12kHz 11 - reserved on the XCTL1,0 pins of the part. NOTE: These pins are multiplexed with other functions; therefore, they may not be available on a particular design ...

Page 41

... LBE res LBA5-LBA0 ID2 ID1 ID0 Playback Upper Base (I14) Default = 00000000 D7 D6 PUB7 PUB6 PUB7-PUB0 CS4237B 00 - MODE Reserved 10 - MODE MODE LBA3 LBA2 LBA1 LBA0 res Loopback Enable: When set to 1, the ADC data is digitally mixed with data sent to the DACs ...

Page 42

... ADC. This filter forces the ADC offset disabled 1 - enabled Crystal Enable. Provided for back- wards compatibility with the CS4231A. This bit does nothing on the this part. Reserved. Must write 0. Could read CS4237B D1 D0 HPF DS213PP4 ...

Page 43

... RLBM RLG4 RLG3 RLG2 RR6 RR5 RR4 RR3 RR2 Right LINE Volume. This register is used to control the RLINE analog in- put volume to the mixers. The least significant bit represents 1.5 dB, with 01000 = 0 dB. See Table 10. CS4237B D1 D0 RLG1 RLG0 RR1 RR0 43 ...

Page 44

... This bit can be disabled by setting IFSE in X11 24.576 MHz base 1 - 16.9344 MHz base Clock Divider. These bits select the audio sample frequency for both cap- ture and playback. These bits can be overridden by IFSE in X11 (2*XT)/(M*N) CS4237B D1 D0 TU1 TU0 D1 D0 DIV0 CS2 ...

Page 45

... Playback Interrupt: Indicates an interrupt is pending from the play- back DMA count registers. Capture Interrupt: Indicates an interrupt is pending from the capture DMA count registers. Timer Interrupt: Indicates an interrupt is pending from the timer registers CS4237B ...

Page 46

... This register is fixed to indicate code compatibility with the CS4236. X25 or C1 should be used to further differentiate between parts that are compatible with the CS4236. All Chips: 00011 - CS4236, CS4237B 00010 - CS4232/CS4232A 00000 - CS4231/CS4231A V2-V0 Version number. As enhancements are made to the part, the version ...

Page 47

... CUB7-CUB0 Capture Lower Base (I31) Default = 00000000 D7 D6 CLB7 CLB6 CLB7-CLB0 CS4237B sample frequency must be the same and is set in I8. MCE (R0) or CMCE (I16) must be set to modify this regis- ter. See Changing Audio Data Formats section for more details ...

Page 48

... Left Master Digital Audio Volume X15 Right Master Digital Audio Volume X16 Left Wavetable Serial Port Volume X17 Right Wavetable Serial Port Volume X18-X24 Reserved X25 Chip Version and ID Table 17. WSS Extended Registers CS4237B Register Name XA4 res ACF DS213PP4 ...

Page 49

... SRAD6 SRAD5 SRAD4 SRDA6 SRDA5 SRDA4 LDMG6 LDMG5 LDMG4 RDMG6 RDMG5 RDMG4 - LWG5 LWG4 - RWG5 RWG4 V1 V0 CID4 Table 18. Extended Register Bit Summary CS4237B IA3 IA2 IA1 ID3 ID2 ID1 XRAE XA4 - LLAG3 LLAG2 LLAG1 RLAG3 RLAG2 RLAG1 LMG3 ...

Page 50

DSP SERIAL PORT DSP Audio Data Serial Port 16-bit SRC Loopback Atten. Atten. X8L I13L & (R) X9R X10 Stereo Enable Mute X8L X10R Loopback enable I13 X9R Digital Mixer Mute I6L 16 bit DSP I7R Mute X6L Atten. I6L ...

Page 51

... RLINE, from the volume control to the input mixer is muted. Right LINE Alternate Output Mute. When set to 1, the Right Line Input, RLINE, from the volume control to the output mixer is muted. RLAOM RLAG4-G0 RLAIM +12 to -34.5 dB RLABM CS4237B Output Mixer To Input Mixer 51 ...

Page 52

... FM and Wavetable Serial Port volume. Internal FM enable. When set to 1, the internal FM synthesis engine is enabled. Setting this bit also changes I6/7 from the master digital audio volume to the ISA bus wave volume control. X14/15 becomes the CS4237B To Output Mixer To Input Mixer D1 D0 res ...

Page 53

... LSPM res LSPA5 LSPA4 LSPA3 LSPA2 LSPA1 LSPA0 LSPA4-LSPA0 Left DSP Serial Port Attenuation. res CS4237B Reserved. Must write 0. Could read Left FM mute. When set to 1, the left internal FM input to the digital mixer is muted. LFMA5-A0 To Digital Mixer ...

Page 54

... SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0 SRAD7-SRAD0 Sample Rate frequency select for CS4237B Stereo LoopBack Enable. When set to 1, control over the Left and Right loopback volume is separated. RLBA5-RLBA0 (X10) control the Right channel, and LBA5-LBA0 (I13) control the Left channel ...

Page 55

... From Digital Mixer Summer Note: This bit is controlled by register (X11) To Input Mixer LDMIM To Output Mixer LDMOM CS4237B ation. The least significant bit represents 1.5 dB, with 000000 = 0 dB. See Table 12. Right Digital Master Output Mixer Mute. When set, the Right DAC output is muted to the Right output mixer ...

Page 56

... Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to C1 and replaces the ID register in I25. 00000 - CS4237B, Revision B 01000 - CS4237B Version Number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip ...

Page 57

... Mixer Register Address Mixer Data Port Reset FM Status Port FM Register port FM Data Port Read Data Port Command/Write Data Write Buffer Status (Bit 7) Data Available Status (Bit 7) CS4237B Type Read Write Write Only Read Write Write Only Write Only Read/Write Write Only ...

Page 58

... RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Table 20. SBPro Compatible Mixer Interface LINE OUT VOICE VOLUME RIGHT X MIC MIXING INPUT SELECT X X VSTC MASTER VOLUME RIGHT FM VOLUME RIGHT CD VOLUME RIGHT LINE VOLUME RIGHT CS4237B DS213PP4 ...

Page 59

... Mixer Index 28H, Default = 01H This register provides 8 steps of CD volume control each for the right and left channels. Line-In Volume Register, Mixer Index 2EH, Default = 01H This register provides 8 steps of line-in volume control each for the right and left channels. CS4237B 59 ...

Page 60

... Must not write any value to this register. May read any value res res res res res Must not write any value to this register. May read any value. series resistor to the appro- CS4237B D1 D0 res res D1 D0 res res pul- DS213PP4 ...

Page 61

... PM1,0 and PDP always reflects the value written, not whether the three devices are pow- ered up or not. CS4237B Power Down Mixer. When set, the analog mixer is powered down and all mixer control registers (in WSSbase space) are reset to de- fault values ...

Page 62

... PROM. 2 PROM. EEN ISH* ICH* * Note: These bits can be initialized through the CS4237B 10 - Codec Input mux is mixed into output mixer. A/D input is from line outputs. This facilitates the Mic mixed to output, and the output recorded by the ADCs reserved. Figure 6. MODE 2 Mixer Addition Interrupt polarity - External Synthe- sizer ...

Page 63

... CD5 CD4 CD3 CD2 Control Indirect Data register. This register provides access to the indi- rect registers C0-C8, where CTRLbase+3 selects the actual reg- ister. See the Control Indirect Register section for more details. CS4237B D1 D0 CA1 CA0 D1 D0 CD1 CD0 63 ...

Page 64

... CR1 CR0 CWSS ICTRL res IMPU IWSS ISB ICTRL CWSS RE2 RE1 RE0 CS4237B ISB IWSS IMPU res Reserved. Could read MPU-401 Interrupt status interrupt pending interrupt is pending Windows Sound System Interrupt status interrupt pending interrupt is pending Sound Blaster Interrupt status ...

Page 65

... Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to the WSS X25 register. 01000 - CS4237B V2-V0 Version number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip ...

Page 66

... SPE bit in WSS I16. For more information on the consumer digital audio transmis- sion format see Crystal’s Application Note 22 titled Overview of Digital Audio Interface Data Structures . Center (CTR3-CTR0) 0.0 dB -1.5 dB -3 -12 -18.0 dB -19.5 dB -21.0 dB -22.5 dB CS4237B D1 D0 res res DS213PP4 ...

Page 67

... Broadcast 0111xxx - Broadcast 100xxxx - Laser-Optical Channel Status bits 25, 24. Sample frequency 44.1 kHz Sample Frequency. This is the only Fs supported res res res res res Reserved. Must write 0. Could read CS4237B D1 D0 CS11 CS10 D1 D0 res res 67 ...

Page 68

... SRS is not required in the recording process. This means a listener’s entire audio library can be enhanced by SRS by simply playing it through the CS4237B Crystal chip. Like stereo, any two-speaker stereo system is adequate. CS4237B DS213PP4 ...

Page 69

... SPC3-0, in or- der to increase apparent image width. SRS Space Control The SRS Space adjustment, SPC3-0 in C2, con- trols the amount of processed difference signal, (L-R)p, that is added to the final left and right digital signals going to the DACs. The difference CS4237B 69 ...

Page 70

... Once Space is set, the Center control should be adjusted to provide a pleasant balance between the ambient sounds and the centered sounds. CS4237B Stereo To 16-bit Analog - ...

Page 71

... L+R and L-R signal levels ("Center" and "Space") are not re- quired and are internally fixed. Consumer IEC-958 Digital Output The CS4237B supports the industry standard IEC-958 consumer digital interface. Sometimes this standard is referred to S/PDIF which refers to an older version of this standard. This output ...

Page 72

... CS4 CS3 CS2 D0-D5 are the 6 LSBs of the last command written to this port. Transmit Buffer Status Flag Transmit buffer not full 1 - Transmit buffer full Receive Buffer Status Flag 0 - Data in Receive buffer 1 - Receive buffer empty CS4237B D1 D0 CS1 CS0 D1 D0 CS1 CS0 DS213PP4 ...

Page 73

... IFM bit in the Hardware Configuration data, byte 8 (Global Configuration Byte) must be set. This bit is also available in WSS register X4. Volume control for the internal FM synthesizer is supported through X6 and X7 in the WSS ex- tended register space. The volume range -94.4 dB with 000000 equal to 0 dB. After CS4237B 73 ...

Page 74

... DOWN which is controlled through the VCEN bit. See the Volume Control Interface section for more details. Note that ACDCS takes precedence over XCTL1/SINT. Also DOWN, when VCEN is set, takes precedence over all other functions. CS4237B DS213PP4 ...

Page 75

... CDbase or ACDbase addresses. This bit allows external data buffers to be used for a CDROM that bypasses the XD<7:0> bus and connects directly to the ISA bus. Note that SDD affects any peripheral port device which in- cludes the external FM and modem interfaces. CS4237B 75 ...

Page 76

... This format has 64 SCLKs per frame, with FSYNC high transitions at the start of the left data word and low transi- tions at the start of the right data word. Both the left and right data words are followed by 16 ze- ros. CS4237B DS213PP4 ...

Page 77

... Clocks Right Data Figure 11. 32-bit Mode (SF1,0 = 10) ... 7 zeros INT CEN PEN OVR 32 Bits INT = Interrupt Bit CEN = Capture Enable PEN = Playback Enable OVR = Left Overrange or Right Overrange ... ... 0 16 Clocks Right Data 32 No-Clock bit periods 0 ... CS4237B 13 zeros Left Data 77 ...

Page 78

... PCM data summed into the digital mixer which is then summed into the analog output mixer. ... DAC 16 Clocks ... DAC 16 Clocks ADC 16 Clocks Figure 12. ADC/DAC Mode (SF1,0 = 11) CS4237B ... ... 15 0 ... ... DAC 16 Clocks Right Data DS213PP4 ...

Page 79

... This mode is also useful when the codec is operating full-duplex and an ADC data format change is desired. This is the only calibration mode that does not affect the DACs (i.e. mute the DACs). The No Calibration mode takes zero sample periods. CS4237B 79 ...

Page 80

... WSS Codec can be removed from MCE. A second method of changing the sample fre- quency is to disable the sample frequency bits in I8 (lower four bits) by setting SRE in I22. When this bit is set, OSM1 and OSM0 in I10, along CS4237B DS213PP4 ...

Page 81

... This format uses the value 0 (00h) to represent maxi- mum negative analog amplitude, 128 for center scale, and 255 (FFh) to represent maximum positive analog amplitude. The 16-bit signed and 8-bit unsigned transfer functions are shown in Figure 22. CS4237B 81 ...

Page 82

... MONO sample 3 sample 2 sample 2 RIGHT 32-bit Word Time sample 2 sample 1 MONO 32-bit Word Time sample 1 sample 1 LEFT 32-bit Word Time sample 2 sample 1 MONO 32-bit Word Time sample 1 sample 1 LEFT CS4237B DS213PP4 ...

Page 83

... MONO MONO MONO sample 2 sample 2 sample 1 LEFT RIGHT LEFT 32-bit Word Time sample 2 sample 1 sample 1 MONO 32-bit Word Time sample 1 sample 1 sample 1 LEFT CS4237B Time sample 1 0 Time sample ...

Page 84

... FIFO. Then the ADPCM’s block accumulator and step size will be frozen. The software must continue +FS 0 -FS A-Law: 2Ah 15h u-Law: 00h 3Fh Figure 23. Companded Transfer Functions CS4237B 55h/D5h 95h AAh 7Fh/FFh BFh 80h DIGITAL CODE DS213PP4 ...

Page 85

... When the playback Current Count register rolls under, the Playback Interrupt bit, PI, (I24) is set causing the INT bit (R2 set. The interrupt is cleared by a write of any value to the Status register (R2), or writing a "0" to the Playback Interrupt bit, PI (I24). CS4237B 85 ...

Page 86

... Count register (DMA playback, DMA capture, or Timer) sets the INT bit. This bit remains set until cleared by a write of ANY value to Status regis- ter (R2 clearing the appropriate bit or bits (PI, CI, TI) in the Alternate Feature Status regis- ter (I24). CS4237B DS213PP4 ...

Page 87

... Holding either of these buttons in the low state causes the volume to to continue changing. The mute function is supported using three for- mats. These formats are selected using the VCF1 and VCF0 bits in the Hardware Configuration data, Global Config. byte. CS4237B 87 ...

Page 88

... Codec register I10 are output directly to the ap- propriate pin when enabled. Pin XCTL0/XA2 becomes an output for XCTL0 whenever the resource data for the CDROM or Synthesizer specifies a logical device address Up Down Mute GND VCF1 Figure 25. Volume Control Formats CS4237B Up Down Mute GND VCF1 DS213PP4 ...

Page 89

... MCS and MINT respectively. Once this switch occurs, the only way to revert to the CDROM DMA pins is to reset the part or re- move power. The XCTL1/SINT/ACDCS/DOWN pin state is first determined by VCEN. If VCEN is set this pin is forced to the DOWN volume control pin. CS4237B 89 ...

Page 90

... Line Inputs must be connected to the AUX1 ana- log inputs. Since some analog inputs can be as large the circuit shown in Figure 26 can be RMS used to attenuate the analog input which is the maximum voltage allowed for the line-level inputs. CS4237B 6 6.8 k 6.8 k 6.8 k Figure 26 ...

Page 91

... At power-up, the MIN line is connected directly to the MOUT pin (with attenuation) allowing the initial beeps, heard when the computer is initializing, to pass through. CS4237B MC33078 or MC33178 0 ...

Page 92

... ISA bus pins as well as the internal digital interface pins. DGND1 is ground for the data bus and should electrically connected to the digital ground 8 plane which will minimize the effects of the bus 7 1 MC34119 or LM4861 CS4237B DS213PP4 ...

Page 93

... XD7-0 and all chip select and address pins. VDF1 through VDF4 provide power to internal digital sections of the codec and should be qui- eter than VD1. This can be achieved by using a Digital Digital Ground Noise Ground Figure 31. Suggested Motherboard Layout Analog Crystal Ground Part 1 Power Connector CS4237B 93 ...

Page 94

... Analog Ground 1 Digital Ground Figure 32. Suggested Add-In Card Layout PIN 80 AGND PIN PIN 81 SGND3 Analog Digital = vias through to power/ground plane PIN 45 VD1 CS4237B Crystal Part PIN 79 REFFLT .1 F PIN 71 TEST PIN 66 SGND2 .1 F PIN 65 VDF2 PIN 54 VDF4 .1 F PIN 53 ...

Page 95

... Input Frequency ( x Fs) Figure 35. ADC Passband Ripple DS213PP4 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.0 0 -10 -20 - -80 -90 -100 0.30 0.35 0.40 0.45 0. CS4237B 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency ( x Fs) Figure 34. ADC Filter Response Input Frequency ( x Fs) Figure 36. ADC Transition Band 0.8 0.9 1 ...

Page 96

... Input Frequency ( x Fs) Figure 39. DAC Transition Band 96 0.2 0.1 0.0 -0.1 -0 -0.4 -0.5 -0.6 -0.7 -0.8 0.6 0.7 0.8 0.9 1.0 0.00 2.0 1.5 1.0 0 -1.5 -2.0 0. 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Input Frequency ( x Fs) Figure 38. DAC Passband Ripple 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Input Frequency ( x Fs) Figure 40. Deviation from Linear Phase CS4237B 0.40 0.45 0.50 0.40 0.45 0.50 DS213PP4 ...

Page 97

... XCTL1*/SINT/ACDCS/DOWN 17 VDF1 SGND1 18 (INT15*) IRQF 19 (INT12*) IRQE 20 (INT11*) IRQD 21 (INT9*) IRQC 22 (INT7*) IRQB 23 (INT5*) IRQA Defaults - See individual pin descriptions for more details DS213PP4 (TOP VIEW) CS4237B 75 LAUX1 74 RAUX1 73 LOUT 72 71 TEST 70 JAB1 69 JBB1*/FSYNC 68 JACX 67 JBCX*/SDOUT 66 SGND2 65 ...

Page 98

... The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3. The defaults can be changed by modifying the Hardware Resource data. Note that DRQA Volt-only pin. When the ISA bus is run at 3.3 Volts, DRQA can either be used with the proper level translator, or DRQA can be left unconnected and not used. 98 CS4237B DS213PP4 ...

Page 99

... RMBST bit. LAUX1 - Left Auxiliary #1 Input Nominally 1 V max analog input for the Left AUX1 channel, centered around VREF. A RMS programmable gain block provides volume control and is located in I2. Typically used for an external Left line-level input. DS213PP4 2 PROM. CS4237B 99 ...

Page 100

... MOMR in X5 mutes the right channel. 100 max analog input, centered around VREF, that goes through a max analog output, centered around VREF. This output is a RMS CS4237B max centered around RMS max centered around RMS DS213PP4 ...

Page 101

... CS9236 Single-Chip Wavetable Music Synthesizer and uses pins XD7-XD5. This serial port is enabled via the WTEN bit. Both SPS and WTEN are located in either C8 in the Control logical device, or the Global Configuration byte in the E Hardware Configuration data. DS213PP4 2 PROM data or PnP commands. CS4237B 2 PROM 101 ...

Page 102

... PROM Data Pin, Bi-directional, Open Drain,4mA sink 2 PROM is used to set the Plug and Play resource data. 2 PROM access is enabled, via EEN in 2 PROM. resistor must be tied between this pin CS4237B 2 2 PROM. When an E PROM is 2 PROM device and DS213PP4 ...

Page 103

... When the serial port is enabled, SPE = 1 in I16, this pin is the serial clock output. The DSP serial port SCLK pin can be switched to XD1 via the SPS bit. This would facilitate using the DSP serial port and the second joystick simultaneously. DS213PP4 CS4237B resistor to the joystick connector pin 11. resistor to the joystick connector pin 13. pullup ...

Page 104

... DMCLK bit the Control logical device space. DMCLK provides a partial software power-down mode for the CS9236. 104 2 PROM Hardware Configuration data, or C8. The to minimize power-down currents and allow for stuffing options. to minimize power-down currents and allow for stuffing CS4237B DS213PP4 ...

Page 105

... Alternately, this pin can be used to output an active low Modem chip select, MCS. The pin is switched to the modem chip select when the LD5 base address, COMbase, is first programmed to non-zero through the PnP data or a hostload. DS213PP4 resistor must be tied between XIOR and SGND. 2 PROM data or PnP commands. This CS4237B 105 ...

Page 106

... The falling edge also latches the state of XIOR and XIOW to determine the functionality of dual mode pins. This signal is typically connected to the ISA bus signal RESDRV. RESDRV must be asserted whenever the part is powered up to initialize the internal registers to a known state. This pin, when high, also drives the BRESET pin low. 106 CS4237B DS213PP4 ...

Page 107

... These pins should be filtered, using a ferrite bead, from VD1. SGND1, SGND2, SGND3, SGND4 - Substrate Ground Substrate ground reference for the codec . These pins are connected to the substrate of the die. Optimum layout is achieved by placing SGND1/2/3/4 on the digital ground plane with the DGND pin as shown in Figure 33. DS213PP4 CS4237B 107 ...

Page 108

... For the DACs, the difference in output voltages for each channel with a full scale digital input. Units in dB. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input code. 108 CS4237B DS213PP4 ...

Page 109

... Ejector pin marks in molding are present on every package. A Description MIN Lead Count Overall Height Stand Off 0.00 b Lead Width 0.14 c Lead Thickness 0.077 Terminal Dimension 15.70 Package Body Terminal Dimension 15.70 Package Body Lead Pitch 0.40 Foot Length 0.30 T Lead Angle 0.0° CS4237B NOM MAX 100 1.66 0.20 0.26 0.127 0.177 16.00 16.30 14.0 16.00 16.30 14.0 0.50 0.60 0.50 0.70 12.0° 109 ...

Page 110

... DB 0B9H DB 0FCH DB 010H DB 003H ; PnP Resource Header - PnP ID for CS4237B IC, OEM 00EH, 063H, 042H, 037H, 0FFH,0FFH,0FFH,0FFH,030H DB 00AH, 010H, 001H DB 082H, 009H, 000H, ’CMB4237B’, 000H ; ANSI ID ; LOGICAL DEVICE 0 (Windows Sound System & SBPro) DB 015H, 00EH, 063H, 000H, 000H, 000H ; EISA ID: CSC0000 DB 082H, 007H, 000H, ’ ...

Page 111

... End of DF for Logical Device Best Choice ; DF Acceptable Choice 1 ; End of DF for Logical Device Best Choice ; IRQ: 9 Interrupt Select Acceptable Choice 1 ; IRQ: 9,11,12,15 Interrupt Select Suboptimal Choice 1 ; End of DF for Logical Device 3 ; End of Resource Data, Checksum CS4237B 111 ...

Page 112

... This part is designed to be hardware and software backwards compatible with the CS4236 and will drop into an existing CS4236 socket without any hardware modifications. Properly written code for the CS4236 will run on the this Codec. However, the CS4237B has enhancements over the CS4236 that provide extra functionality. ...

Page 113

... Volt ISA bus support is added. This includes all ISA pins except DRQA (which still runs at 5 Volts). When the VD1 pin is powered from a 3.3 Volt supply, the ISA bus connected to it must also run at 3.3 Volts. DS213PP4 2 PROM this byte must be changed to 0x0B. This provides backwards CS4237B 2 PROM. When firmware code 2 PROM. 113 ...

Page 114

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