MC68HC908AZ60 Freescale Semiconductor, Inc, MC68HC908AZ60 Datasheet
MC68HC908AZ60
Available stocks
Related parts for MC68HC908AZ60
MC68HC908AZ60 Summary of contents
Page 1
...
Page 2
...
Page 3
... Motorola, Inc., 1999 MOTOROLA List of Sections MC68HC908AZ60 — Rev 2.0 1 ...
Page 4
... MC68HC908AZ60 — Rev 2.0 2 List of Sections MOTOROLA ...
Page 5
... FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . 41 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . . 43 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FLASH-2 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Future FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MOTOROLA Table of Contents MC68HC908AZ60 — Rev 2.0 3 ...
Page 6
... Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 System Integration Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Module (SIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . .109 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Program Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 MC68HC908AZ60 — Rev 2.0 4 Table of Contents MOTOROLA ...
Page 7
... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Computer Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Operating Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Properly Module Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 (COP) I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 184 MOTOROLA Table of Contents Table of Contents MC68HC908AZ60 — Rev 2.0 5 ...
Page 8
... Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . .239 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 MC68HC908AZ60 — Rev 2.0 6 Table of Contents MOTOROLA ...
Page 9
... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 (MSCAN08) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 MOTOROLA Table of Contents Table of Contents MC68HC908AZ60 — Rev 2.0 7 ...
Page 10
... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447 Appendix A: Future EEPROM Timebase Divider Control Registers . . . . . . . . . . . . . . . .449 EEPROM Registers EEDIVH and EEDIVL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 EEDIV Non-volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 MC68HC908AZ60 — Rev 2.0 8 Table of Contents MOTOROLA ...
Page 11
... Glossary Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . . 466 Revision History Major Changes Between Revision 2.0 and Revision 1 469 MOTOROLA Table of Contents Table of Contents MC68HC908AZ60 — Rev 2.0 9 ...
Page 12
... MC68HC908AZ60 — Rev 2.0 10 Table of Contents MOTOROLA ...
Page 13
... CAN Receive Pin (CANRx Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MC Order Numbers The MC68HC908AZ60 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 ...
Page 14
... This part is designed to emulate the MC68HC08AZxx automotive family. In AZxx mode the MC68HC908AZ60 offers extra features which are not available on the MC68HC08AZ32 device the user’s responsibility to ensure compatibility between the features used on the MC68HC908AZ60 and those which are available on the device which will ultimately be used in the application ...
Page 15
... Index Register and Stack Pointer Memory-to-Memory Data Transfers Fast 8 8 Multiply Instruction Fast 16/8 Divide Instruction Binary-Coded Decimal (BCD) Instructions Optimization for Controller Applications C Language Support shows the structure of the MC68HC908AZ60. General Description General Description MCU Block Diagram MC68HC908AZ60 — Rev 2.0 13 ...
Page 16
... IRQ IRQ MODULE POWER-ON RESET MODULE POWER V DDA V SSA Figure 1. MCU Block Diagram for the MC68HC908AZ60 (64-Pin QFP) V REFH ANALOG-TO-DIGITAL MODULE BREAK MODULE LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE TIMER A 6 CHANNEL INTERFACE MODULE TIMER B INTERFACE MODULE ...
Page 17
... CANTx 10 PTF5/TBCH1 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 2. MC68HC908AZ60 (64-Pin QFP) NOTE: The following pin descriptions are just a quick reference. For a more detailed representation, see 5-gen MOTOROLA shows the MC68HC908AZ60 pin assignments. I/O Ports General Description General Description Pin Assignments PTH0/KBD3 48 PTD3/ATD11 ...
Page 18
... Serial Peripheral Interface Module (SPI) NOTE: V must be grounded for proper MCU operation. SS The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See MC68HC908AZ60 — Rev 2.0 16 are the power supply and ground pins. The MCU operates SS MCU ...
Page 19
... The analog sections consist of a clock generator Clock Generator Module (CGM) on page 305. General Description General Description Pin Assignments on page 105 for more information. on page 191. on page 127. on page 127. on page 127 on page 421 and I/O Ports MC68HC908AZ60 — Rev 2.0 I ...
Page 20
... See page 381 and Port 2-bit special-function port that shares all of its pins with the keyboard interrupt module (KBD). See page 381 and MC68HC908AZ60 — Rev 2 page 305. Timer Interface Module A (TIMA-6) Analog-to-Digital Converter (ADC-15) on page 305 ...
Page 21
... Dual State No Dual State Input Hi-Z No Dual State Yes Input Hi-Z Open Drain Dual State Yes Input Hi-Z Open Drain Dual State Yes Input Hi-Z Open Drain Dual State Yes Input Hi-Z Dual State Yes Input Hi-Z Dual State Yes Input Hi-Z Dual State Yes Input Hi-Z MC68HC908AZ60 — Rev 2.0 19 ...
Page 22
... DDAREF A /V VSS REFL V REFH OSC1 OSC2 CGMXFC IRQ RST CANRx CANTx MC68HC908AZ60 — Rev 2.0 20 Driver Function Type General-Purpose I/O Dual State SCI Transmit Data General-Purpose I/O Dual State General-Purpose Dual State I/O/Timer B Channel General-Purpose I/O Dual State Timer A Channel 5 General-Purpose I/O Dual State ...
Page 23
... General Description General Description Pin Assignments Clock Source CGMXCLK or Bus Clock CGMXCLK or CGMOUT CGMXCLK Bus Clock RC OSC or Bus Clock Bus Clock/SPSCK CGMXCLK Bus Clock or PTD4/TBCLK Bus Clock CGMOUT and CGMXCLK Bus Clock Bus Clock Bus Clock OSC1 and OSC2 MC68HC908AZ60 — Rev 2.0 21 ...
Page 24
... This section contains instructions for ordering the MC68HC908AZ60. MC68HC908AZ60CFU MC68HC908AZ60VFU MC68HC908AZ60MFU MC68HC908AZ60 — Rev 2.0 22 Table 3. MC Order Numbers MC Order Number General Description Operating Temperature Range – – 105 C –40 ° 125 °C 12-gen MOTOROLA ...
Page 25
... Bytes of EEPROM with Protect Option 52 Bytes of User-Defined Vectors 224 Bytes of Monitor ROM Reserved — Accessing a reserved location can have unpredictable effects on MCU operation. Unimplemented — Accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled. Memory Map MC68HC908AZ60 — Rev 2.0 23 ...
Page 26
... MC68HC908AZ60 — Rev 2.0 24 Figure 1. Memory Map $0000 I/O REGISTERS (64 BYTES) $003F $0040 I/O REGISTERS, 16 BYTES $004F $0050 RAM-1, 1024 BYTES $044F $0450 FLASH-2, 176 BYTES $04FF $0500 CAN CONTROL AND MESSAGE BUFFERS, 128 BYTES $057F $0580 FLASH-2, 128 BYTES $05FF $0600 EEPROM-2, 512 BYTES ...
Page 27
... Memory Map Memory Map Introduction $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 $FE17 $FE18 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 $FEFF $FF00 $FF7F $FF80 $FF81 $FF82 $FFCB MC68HC908AZ60 — Rev 2.0 25 ...
Page 28
... Table 1 MC68HC908AZ60 — Rev 2.0 26 Figure 1. Memory Map (Continued) $FFCC VECTORS (52BYTES) $FFFF $FE00 (SIM break status register, SBSR) $FE01 (SIM reset status register, SRSR) $FE03 (SIM break flag control register, SBFCR) $FE09 (configuration write-once register, CONFIG-2) ...
Page 29
... PTG1 PTH1 DDRE4 DDRE3 DDRE2 DDRE1 DDRF4 DDRF3 DDRF2 DDRF1 0 0 DDRG2 DDRG1 DDRH1 CPOL CPHA SPWOM SPE MC68HC908AZ60 — Rev 2.0 Bit 0 PTA0 PTB0 PTC0 PTD0 DDRA0 DDRB0 DDRC0 DDRD0 PTE0 PTF0 PTG0 PTH0 DDRE0 DDRF0 DDRG0 DDRH0 SPTIE 27 ...
Page 30
... Configuration Write-Once $001F Register (CONFIG-1) Timer A Status and Control $0020 Register (TASC) Keyboard Interrupt Enable Register $0021 (KBIE) Figure 2. Control, Status, and Data Registers (Sheet MC68HC908AZ60 — Rev 2.0 28 Bit Unimplemented Read: SPRF OVRF ERRIE Write: Read: ...
Page 31
... MS3A ELS3B ELS3A TOV3 MS4A ELS4B ELS4A TOV4 MC68HC908AZ60 — Rev 2.0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX Bit 8 Bit 0 CH3MAX Bit 8 Bit 0 CH4MAX Bit 8 29 ...
Page 32
... Timer B CH1 Status and Control Register (TBSC1) $0048 Timer B CH1 Register High $0049 (TBCH1H) Timer B CH1 Register Low $004A (TBCH1L) Figure 2. Control, Status, and Data Registers (Sheet MC68HC908AZ60 — Rev 2.0 30 Bit Read: Bit Write: Read: CH5F ...
Page 33
... BLK0 HVEN VERF ERASE EEPRTCT EEBP3 EEBP2 EEBP1 0 EERAS1 EERAS0 EELAT MC68HC908AZ60 — Rev 2.0 I/O Section Bit 0 PPS0 Bit 8 Bit 0 Bit 8 Bit AZxx PGM Bit 8 Bit PGM EEBP0 EEPGM R 31 ...
Page 34
... FLASH Block Protect Register $FF80 (FLBPR1) FLASH Block Protect Register $FF81 (FLBPR2) $FFFF COP Control Register (COPCTL) Figure 2. Control, Status, and Data Registers (Sheet MC68HC908AZ60 — Rev 2.0 32 Bit Read: EERA CON2 CON1 EEPRTCT EEBP3 Write: Read: EERA ...
Page 35
... TIMB CH1 Vector (Low) $FFEA TIMB CH0 Vector (High) $FFEB TIMB CH0 Vector (Low) $FFEC TIMA Overflow Vector (High) $FFED TIMA Overflow Vector (Low) $FFEE TIMA CH3 Vector (High) $FFEF TIMA CH3 Vector (Low) Memory Map Memory Map I/O Section MC68HC908AZ60 — Rev 2.0 33 ...
Page 36
... MC68HC908AZ60 — Rev 2.0 34 Table 1. Vector Addresses (Continued) Address $FFF0 TIMA CH2 Vector (High) $FFF1 TIMA CH2 Vector (Low) $FFF2 TIMA CH1 Vector (High) $FFF3 TIMA CH1 Vector (Low) $FFF4 TIMA CH0 Vector (High) $FFF5 TIMA CH0 Vector (Low) $FFF6 PIT Vector (High) ...
Page 37
... RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. 1-ram MOTOROLA MC68HC908AZ60 — Rev 2.0 RAM 35 ...
Page 38
... During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908AZ60 — Rev 2.0 36 RAM 2-ram MOTOROLA ...
Page 39
... Design is underway to introduce an improved Flash memory module. The new module will offer improved write erase cycling and faster programming times. However Flash program and erase algorithms will 3-flash-1 MOTOROLA FLASH-1 Memory MC68HC908AZ60 — Rev 2.0 37 ...
Page 40
... The 8 program cycle maximum per row aligns with the architecture’s 8 pages of storage per MC68HC908AZ60 — Rev 2.0 38 $8000–$FDFF $FF80–FF81 (Block Protect Registers) $FE0B FLASH Control Register $FFCC– ...
Page 41
... Bit FDIV1 FDIV0 BLK1 BLK0 Figure 1. FLASH-1 Control Register (FLCR1) FLASH-1 Memory FLASH-1 Memory FLASH-1 Control Register HVEN MARGIN ERASE FLASH on page 41. MC68HC908AZ60 — Rev 2.0 Bit 0 PGM 0 39 ...
Page 42
... ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. MC68HC908AZ60 — Rev 2.0 40 FLASH Erase Operation FLASH Erase Operation 1 = High voltage enabled to array and charge pump on ...
Page 43
... FLASH-1 control register. See 1 for FDIV settings. FLASH-1 Memory FLASH-1 Memory FLASH Charge Pump Frequency Control Table 1 shows Bus Clock Frequency 1 2 MHz 10 MHz 10 MHz 10 MHz 10% Table 2 for block sizes. See MC68HC908AZ60 — Rev 2.0 Table 41 ...
Page 44
... In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. For instance, with BLK0 = BLK1 = 0, writing to any Flash address in the range $8000 to $FFFF will enable the full-array erase. MC68HC908AZ60 — Rev 2.0 42 register: address $FF80. See and FLASH-1 Block Protect Register information ...
Page 45
... Wait for time, t 9-flash-1 MOTOROLA Memory Characteristics operation and enables the latching of address and data for programming. requires eight separate write operations. . PROG . HVTV . VTP . HVD FLASH-1 Memory FLASH-1 Memory FLASH Program/Margin Read Operation on page 445, has a detailed MC68HC908AZ60 — Rev 2.0 43 ...
Page 46
... In order to ensure proper FLASH read operation after completion of the smart programming algorithm, a series of 500 dummy FLASH reads must be performed of any address before accurate data is read from the FLASH. MC68HC908AZ60 — Rev 2.0 44 separate read operations which are each stretched by eight cycles. FLASH Erase Operation FLASH-1 Memory on page 41) ...
Page 47
... Clear HVEN Bit Wait t HVTV Set MARGIN Bit Wait t VTP Clear PGM Bit Wait t HVD Margin Read Page of Data N Margin Read Data Equal To Write Data? Y Clear MARGIN Bit Clear Interrupt Mask: CLI Instr. (see note above) Programming Operation Complete MC68HC908AZ60 — Rev 2.0 45 ...
Page 48
... IRQ pin. The presence of V entry in to monitor mode out of reset. Therefore, the ability to change the block protect register is voltage dependent and can occur in either user or monitor modes. MC68HC908AZ60 — Rev 2 page 47. The block protect register HI FLASH-1 Memory ...
Page 49
... Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program FLASH-1 Memory FLASH-1 Memory FLASH-1 Block Protect Register BPR3 BPR2 BPR1 MC68HC908AZ60 — Rev 2.0 Bit 0 BPR0 0 47 ...
Page 50
... The block protect register is implemented as a byte within the FLASH-1 memory. Each bit, when programmed, protects a range of addresses in the FLASH-2 array. Address: Read: Write: Reset: MC68HC908AZ60 — Rev 2 Address range protected from erase or program 0 = Address range open to erase or program $FF81 Bit 7 6 ...
Page 51
... Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program FLASH-1 Memory FLASH-1 Memory FLASH-2 Block Protect Register on the HI MC68HC908AZ60 — Rev 2.0 49 ...
Page 52
... Exit from stop must now be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. MC68HC908AZ60 — Rev 2.0 50 FLASH-1 Memory 16-flash-1 ...
Page 53
... Design is underway to introduce an improved Flash memory module. The new module will offer improved write erase cycling and faster programming times. However Flash program and erase algorithms will 1-flash-2 MOTOROLA FLASH-2 Memory MC68HC908AZ60 — Rev 2.0 51 ...
Page 54
... The 8 program cycle maximum per row aligns with the architecture’s 8 pages of storage per row. The margin read step of the smart programming algorithm is used to insure programmed bits are programmed to sufficient margin for data MC68HC908AZ60 — Rev 2.0 52 $0450–$04FF $0580–$05FF $0E00– ...
Page 55
... Bit FDIV1 FDIV0 BLK1 BLK0 Figure 1. FLASH-2 Control Register (FLCR2) FLASH-2 Memory FLASH-2 Memory FLASH Control Register HVEN MARGIN ERASE FLASH on page 55. FLASH on page 55. MC68HC908AZ60 — Rev 2.0 Bit 0 PGM 0 53 ...
Page 56
... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be set at the same time. MC68HC908AZ60 — Rev 2.0 54 FLASH Erase Operation FLASH Erase Operation 1 = High voltage enabled to array and charge pump on ...
Page 57
... ERASE FLASH-2 Memory FLASH-2 Memory FLASH Charge Pump Frequency Control Table 1 Bus Clock Frequency 1 2 MHz 10 MHz 10 MHz 10 MHz 10% Table 2 for block sizes. See FLASH Block Protection on page MC68HC908AZ60 — Rev 2.0 shows Table 1 55 ...
Page 58
... In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. For instance, with BLK0 = BLK1 = 0, writing to any Flash address in the range $0450-$05FF or $0E00-$7FFF will enable the full-array erase. MC68HC908AZ60 — Rev 2 for the high voltages to dissipate. KILL , the memory can be accessed in read mode again ...
Page 59
... Wait for time, t 7-flash-2 MOTOROLA Memory Characteristics operation and enables the latching of address and data for programming. requires eight separate write operations. . PROG . HVTV . VTP . HVD FLASH-2 Memory FLASH-2 Memory FLASH Program/Margin Read Operation on page 445 has a detailed MC68HC908AZ60 — Rev 2.0 57 ...
Page 60
... In order to ensure proper FLASH read operation after completion of the smart programming algorithm, a series of 500 dummy FLASH reads must be performed of any address before accurate data is read from the FLASH. MC68HC908AZ60 — Rev 2.0 58 separate read operations which are each stretched by eight cycles. FLASH Erase Operation FLASH-2 Memory on page 55) ...
Page 61
... Clear HVEN Bit Wait t HVTV Set MARGIN Bit Wait t VTP Clear PGM Bit Wait t HVD Margin Read Page of Data N Margin Read Data Equal To Write Data? Y Clear MARGIN Bit Clear Interrupt Mask: CLI Instr. (see note above) Programming Operation Complete MC68HC908AZ60 — Rev 2.0 59 ...
Page 62
... The block protect register for FLASH-2 is physically implemented as a byte within the FLASH-1 memory. Please refer to the FLASH-1 memory section, register. Each bit, when programmed, protects a range of addresses in the FLASH-2 array. MC68HC908AZ60 — Rev 2 page 60. The block protect register FLASH-2 Block Protect Register FLASH-2 Memory ...
Page 63
... Exit from stop must now be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. 11-flash-2 MOTOROLA FLASH-2 Memory FLASH-2 Memory Low-Power Modes MC68HC908AZ60 — Rev 2.0 61 ...
Page 64
... MC68HC908AZ60 — Rev 2.0 62 FLASH-2 Memory 12-flash-2 MOTOROLA ...
Page 65
... Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Functional Description EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MC68HC908AZ60 EEPROM Protection EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 EEPROM Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Wait Mode Stop Mode This section describes the electrically erasable programmable read-only memory (EEPROM). The 1024 bytes available on the MC68HC908AZ60 are physically located in two 512byte arrays ...
Page 66
... This new silicon will not allow multiple writes before erase. EEPROM bytes must be erased before reprogramming. EEPROM features include: • • • • • MC68HC908AZ60 — Rev. 2.0 64 for preliminary details. Byte, Block, or Bulk Erasable Nonvolatile Block Protection Option Nonvolatile MCU Configuration Bits On-Chip Charge Pump for Programming/Erasing Security Option ...
Page 67
... Clear EEPGM bit. 6. Wait for a time Clear EELAT bits. (See note D.) 8. Repeat steps for more EEPROM programming. 3-eeprom-1 MOTOROLA note A and B program the byte. EEPGM , for the programming voltage to fall. EEFPV EEPROM-1 EEPROM-1 Functional Description MC68HC908AZ60 — Rev. 2.0 65 ...
Page 68
... NOTES: MC68HC908AZ60 — Rev. 2 EERAS1 and EERAS0 must be cleared for programming. Otherwise, the part will be in erase mode. b. Setting EELAT bit configures the address and data buses to latch data for programming the array. Only data with valid EEPROM address will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data ...
Page 69
... If EELAT is set, other writes to the EECR1 will only be allowed after a valid EEPROM write. b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase EEPROM-1 EEPROM-1 Functional Description /t . EEBULK. MC68HC908AZ60 — Rev. 2.0 67 ...
Page 70
... EENVR1 register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR1 register and then reading the EENVR1 register. MC68HC908AZ60 — Rev. 2.0 68 mode cannot be modified. If EEPGM is set, the onboard charge pump generates the erase voltage and applies it to the user EEPROM array ...
Page 71
... The new array configuration will take affect after a system reset or a read of the EENVR1. The MC68HC908AZ60 has a special protection option which prevents program/erase access to memory locations $08F0 to $08FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR to 0 ...
Page 72
... EEOFF — EEPROM Power Down This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. NOTE: The EEPROM requires a recovery time, t the EEOFF bit. MC68HC908AZ60 — Rev. 2.0 70 $FE1D Bit ...
Page 73
... X = don’t care 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation 1 = EEPROM programming/erasing power switched EEPROM programming/erasing power switched off EEPROM-1 EEPROM-1 Functional Description EERAS0 MODE 0 Byte Program 1 Byte Erase 0 Block Erase 1 Bulk Erase X No Erase/Program MC68HC908AZ60 — Rev. 2.0 71 ...
Page 74
... This one-time programmable bit can be used to protect 16 bytes ($8F0–$8FF) from being erased or programmed. EEBP3–EEBP0 — EEPROM Block Protection Bits These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP[3:0] from EENVR1 to EEACR1. MC68HC908AZ60 — Rev. 2.0 72 $FE1C Bit ...
Page 75
... EERA CON2 CON1 EEPRTCT = Unimplemented Figure 3. EEPROM-1 Array Control Register (EEACR1 EEPROM protection disabled 0 = EEPROM protection enabled 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected EEPROM-1 Functional Description EEBP3 EEBP2 EEBP1 EENVR MC68HC908AZ60 — Rev. 2.0 EEPROM-1 Figure Bit 0 EEBP0 73 ...
Page 76
... Program/erase time will need to be extended if program/erase is interrupted by entering stop mode. The module requires a recovery time, t stop mode. Attempts to access the array during the recovery time will result in unpredictable behavior. MC68HC908AZ60 — Rev. 2 stabilize after leaving EESTOP EEPROM-1 ...
Page 77
... Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Functional Description EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MC68HC908AZ60 EEPROM Protection EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 EEPROM Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Wait Mode Stop Mode This section describes the electrically erasable programmable read-only memory (EEPROM). The 1024 bytes available on the MC68HC908AZ60 are physically located in two 512byte arrays ...
Page 78
... This new silicon will not allow multiple writes before erase. EEPROM bytes must be erased before reprogramming. EEPROM features include: • • • • • MC68HC908AZ60 — Rev 2.0 76 for preliminary details. Byte, Block, or Bulk Erasable Nonvolatile Block Protection Option Nonvolatile MCU Configuration Bits On-Chip Charge Pump for Programming/Erasing Security Option ...
Page 79
... Clear EEPGM bit. 6. Wait for a time Clear EELAT bits. (See note D.) 8. Repeat steps for more EEPROM programming. 3-eeprom-2 MOTOROLA note A and B program the byte. EEPGM , for the programming voltage to fall. EEFPV EEPROM-2 EEPROM-2 Functional Description MC68HC908AZ60 — Rev 2.0 77 ...
Page 80
... NOTES: MC68HC908AZ60 — Rev 2 EERAS1 and EERAS0 must be cleared for programming. Otherwise, the part will be in erase mode. b. Setting EELAT bit configures the address and data buses to latch data for programming the array. Only data with valid EEPROM address will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data ...
Page 81
... If EELAT is set, other writes to the EECR2 will only be allowed after a valid EEPROM write. b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase EEPROM-2 EEPROM-2 Functional Description /t . EEBULK. MC68HC908AZ60 — Rev 2.0 79 ...
Page 82
... EENVR2 register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR2 register and then reading the EENVR2 register. MC68HC908AZ60 — Rev 2.0 80 mode cannot be modified. If EEPGM is set, the onboard charge pump generates the erase voltage and applies it to the user EEPROM array ...
Page 83
... The new array configuration will take affect after a system reset or a read of the EENVR2. The MC68HC908AZ60 has a special protection option which prevents program/erase access to memory locations $08F0 to $08FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR to 0 ...
Page 84
... EEOFF — EEPROM Power Down This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. NOTE: The EEPROM requires a recovery time, t the EEOFF bit. MC68HC908AZ60 — Rev 2.0 82 $FE19 Bit ...
Page 85
... X = don’t care 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation 1 = EEPROM programming/erasing power switched EEPROM programming/erasing power switched off EEPROM-2 EEPROM-2 Functional Description EERAS0 MODE 0 Byte Program 1 Byte Erase 0 Block Erase 1 Bulk Erase X No Erase/Program MC68HC908AZ60 — Rev 2.0 83 ...
Page 86
... This one-time programmable bit can be used to protect 16 bytes ($8F0–$8FF) from being erased or programmed. EEBP3–EEBP0 — EEPROM Block Protection Bits These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP[3:0] from EENVR2 to EEACR2. MC68HC908AZ60 — Rev 2.0 84 $FE18 Bit ...
Page 87
... EERA CON2 CON1 EEPRTCT = Unimplemented Figure 3. EEPROM-2 Array Control Register (EEACR2 EEPROM protection disabled 0 = EEPROM protection enabled 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected EEPROM-2 Functional Description EEBP3 EEBP2 EEBP1 EENVR MC68HC908AZ60 — Rev 2.0 EEPROM-2 Figure Bit 0 EEBP0 85 ...
Page 88
... Program/erase time will need to be extended if program/erase is interrupted by entering stop mode. The module requires a recovery time, t stop mode. Attempts to access the array during the recovery time will result in unpredictable behavior. MC68HC908AZ60 — Rev 2 stabilize after leaving EESTOP EEPROM-2 ...
Page 89
... This section describes the central processor unit (CPU8). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 1-cpu MOTOROLA Central Processor Unit (CPU) MC68HC908AZ60 — Rev 2.0 87 ...
Page 90
... MC68HC908AZ60 — Rev 2.0 88 Full upward, object-code compatibility with M68HC05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 8.4MHz CPU internal bus frequency 64K byte program/data memory space ...
Page 91
... Central Processor Unit (CPU) CPU registers 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 0 CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG MC68HC908AZ60 — Rev 2.0 Bit 0 89 ...
Page 92
... In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: SP Write: Reset: MC68HC908AZ60 — Rev 2.0 90 Bit ...
Page 93
... Figure 5. Program counter (PC) Bit Indeterminate Figure 6. Condition code register (CCR) Central Processor Unit (CPU) Central Processor Unit (CPU) CPU registers MC68HC908AZ60 — Rev 2.0 Bit Bit ...
Page 94
... A return from interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (CLI). MC68HC908AZ60 — Rev 2 Overflow overflow ...
Page 95
... Some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 7-cpu MOTOROLA 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result 1 = Carry out of bit carry out of bit 7 Central Processor Unit (CPU) Central Processor Unit (CPU) CPU registers MC68HC908AZ60 — Rev 2.0 93 ...
Page 96
... After exiting STOP mode, the CPU clock begins running after the oscillator stabilization delay. MC68HC908AZ60 — Rev 2.0 94 clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from WAIT mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. ...
Page 97
... A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. 9-cpu MOTOROLA Break Module Central Processor Unit (CPU) Central Processor Unit (CPU) CPU during break interrupts on page 161. The program MC68HC908AZ60 — Rev 2.0 95 ...
Page 98
... ASL ,X ASL opr ,SP ASR opr ASRA ASRX Arithmetic Shift Right ASR opr ,X ASR opr ,X ASR opr ,SP BCC rel Branch if Carry Bit Clear MC68HC908AZ60 — Rev 2.0 96 provides a summary of the M68HC08 instruction set. Table 1. Instruction Set Summary Description A (A) + (M) + (C) A (A) + (M) « SP (SP) + (16 M) « ...
Page 99
... REL 91 rr – – – – – – REL 2C rr – – – – – – REL 2B rr – – – – – – REL 2D rr MC68HC908AZ60 — Rev 2 ...
Page 100
... CBEQ X+ ,rel CBEQ opr, SP ,rel CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX CLRH Clear CLR opr ,X CLR ,X CLR opr ,SP MC68HC908AZ60 — Rev 2.0 98 Description PC (PC rel ? ( (PC rel ? ( (PC rel PC (PC rel ? (Mn (PC ...
Page 101
... INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff MC68HC908AZ60 — Rev 2 ...
Page 102
... LSL ,X LSL opr ,SP LSR opr LSRA LSR X Logical Shift Right LSR opr ,X LSR ,X LSR opr ,SP MOV opr,opr MOV opr, X+ Move MOV # opr,opr MOV X+ ,opr MUL Unsigned multiply MC68HC908AZ60 — Rev 2.0 100 Description ...
Page 103
... DIR 36 dd INH 46 INH 56 – – IX1 SP1 9E66 ff – – – – – – INH 9C INH 80 – – – – – – INH 81 MC68HC908AZ60 — Rev 2 ...
Page 104
... SUB opr SUB opr ,X Subtract SUB opr ,X SUB ,X SUB opr ,SP SUB opr ,SP SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A MC68HC908AZ60 — Rev 2.0 102 Description A (A) – (M) – ( (A) (M (H: Stop Oscillator ...
Page 105
... INH 4D INH 5D 0 – – – IX1 SP1 9E6D ff – – – – – – INH 95 – – – – – – INH 9F – – – – – – INH 94 MC68HC908AZ60 — Rev 2 103 ...
Page 106
... MC68HC908AZ60 — Rev 2.0 104 Central Processor Unit (CPU) 18-cpu MOTOROLA ...
Page 107
... SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 125 1-sim MOTOROLA Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . 113 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . 114 System Integration Module (SIM) MC68HC908AZ60 — Rev 2.0 105 ...
Page 108
... SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: • • • • MC68HC908AZ60 — Rev 2.0 106 Figure Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control ...
Page 109
... CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE MC68HC908AZ60 — Rev 2.0 107 ...
Page 110
... Register Name SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) Table 2 Signal Name CGMXCLK CGMVCLK MC68HC908AZ60 — Rev 2.0 108 Bit POR PIN COP BCFE Reserved Figure 2. SIM I/O Register Summary Table 1 ...
Page 111
... CGMOUT = B BCS PTC3 CGM Figure 3. CGM Clock Signals System Integration Module (SIM) System Integration Module (SIM) SIM Bus Clock Control and Generation Figure 3. This clock can come on page 127). on page 127). SIM COUNTER BUS CLOCK 2 GENERATORS SIM MC68HC908AZ60 — Rev 2.0 109 ...
Page 112
... Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR MC68HC908AZ60 — Rev 2.0 110 Power-on reset module (POR) ...
Page 113
... POR/LVI All others VECT H Figure 4. External Reset Timing Figure System Integration Module (SIM) System Integration Module (SIM) Reset and System Initialization Table 3 for details. Figure 4163 (4096 + ( VECT L Figure 6). Note that for LVI or POR Figure 5. MC68HC908AZ60 — Rev 2.0 111 ...
Page 114
... CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: • • • • • • MC68HC908AZ60 — Rev 2.0 112 RST PULLED LOW BY MCU 32 CYCLES IAB Figure 5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST ...
Page 115
... SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. 9-sim MOTOROLA 4096 32 32 CYCLES CYCLES Figure 7. POR Recovery Computer Operating Properly Module (COP) System Integration Module (SIM) System Integration Module (SIM) Reset and System Initialization $FFFE $FFFF on page 179. MC68HC908AZ60 — Rev 2.0 113 ...
Page 116
... LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST pin will be held low until the SIM counts 4096 CGMXCLK cycles after V DD CPU is released from reset to allow the reset vector sequence to occur. See MC68HC908AZ60 — Rev 2.0 114 voltage falls to the V voltage. The LVI bit in the SIM reset LVII DD rises above V ...
Page 117
... The SIM counter is free-running after all reset states. See Active Resets from Internal Sources internal reset recovery sequences. 11-sim MOTOROLA on page 111 for counter control and System Integration Module (SIM) System Integration Module (SIM) SIM Counter Stop Mode on page MC68HC908AZ60 — Rev 2.0 115 ...
Page 118
... I bit is cleared), see 9. MODULE I N TERRUPT I BIT IAB DUMMY SP IDB DUMMY PC – 1[7:0] R/W MC68HC908AZ60 — Rev 2.0 116 Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts Figure 8 shows interrupt entry timing. SP – – – – ...
Page 119
... STACK CPU REGISTERS. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO YES RTI UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 9. Interrupt Processing System Integration Module (SIM) System Integration Module (SIM) Program Exception Control SET I BIT. MC68HC908AZ60 — Rev 2.0 117 ...
Page 120
... Families the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908AZ60 — Rev 2.0 118 SP – – – ...
Page 121
... RTI . Figure 11 Interrupt Recognition Example Break Module on page 161. The SIM puts the CPU into the System Integration Module (SIM) System Integration Module (SIM) Program Exception Control BACKGROUND ROUTINE INT1 INTERRUPT SERVICE ROUTINE INT2 INTERRUPT SERVICE ROUTINE MC68HC908AZ60 — Rev 2.0 119 ...
Page 122
... Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break wait bit, BW, in the SIM break MC68HC908AZ60 — Rev 2.0 120 Figure 12 shows the timing for wait mode entry. ...
Page 123
... Figure 13. Wait Recovery from Interrupt or Break 32 Cycles IAB $6E0B IDB $A6 $A6 $A6 RST Figure 14. Wait Recovery from Internal Reset System Integration Module (SIM) System Integration Module (SIM) Low-Power Modes SAME SAME SAME SAME $00FF $00FE $00FD $00FC $0B $6E 32 Cycles RST VCT H RST VCT L MC68HC908AZ60 — Rev 2.0 121 ...
Page 124
... The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery then used to time the recovery period. CPUSTOP NOTE: Previous data can be operand data or the STOP opcode, depending on the last MC68HC908AZ60 — Rev 2.0 122 Figure 15 shows stop mode entry timing. IAB ...
Page 125
... Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt System Integration Module (SIM) System Integration Module (SIM) SIM Registers SP SP – – – See Note 0 NOTE: Writing a logic 0 clears BW MC68HC908AZ60 — Rev 2.0 Bit 0 R 123 ...
Page 126
... A power-on reset sets the POR bit and clears all other bits in the register. Address: Read: Write: POR: POR — Power-On Reset Bit MC68HC908AZ60 — Rev 2.0 124 ; See if wait mode or stop mode was exited ; by break RETURNLO is not zero, ...
Page 127
... Reserved Figure 19. SIM Break Flag Control Register (SBFCR Status bits clearable during break 0 = Status bits not clearable during break System Integration Module (SIM) System Integration Module (SIM) SIM Registers MC68HC908AZ60 — Rev 2.0 Bit 0 R 125 ...
Page 128
... MC68HC908AZ60 — Rev 2.0 126 System Integration Module (SIM) 22-sim MOTOROLA ...
Page 129
... CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . 149 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 149 1-cgm MOTOROLA Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Acquisition and Tracking Modes 133 Manual and Automatic PLL Bandwidth Modes 133 Programming the PLL 135 Special Programming Exceptions 137 Clock Generator Module (CGM) MC68HC908AZ60 — Rev 2.0 127 ...
Page 130
... Features of the CGM include: • • • • • MC68HC908AZ60 — Rev 2.0 128 Phase-Locked Loop with Output Frequency in Integer Multiples of the Crystal Reference Programmable Hardware Voltage-Controlled Oscillator (VCO) for Low-Jitter Operation Automatic Bandwidth Control Mode for Low-Jitter Operation ...
Page 131
... CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks are derived from CGMOUT. shows the structure of the CGM. Clock Generator Module (CGM) Clock Generator Module (CGM) Functional Description MC68HC908AZ60 — Rev 2.0 129 ...
Page 132
... OSC1 CGMRDV CGMRCLK V DDA PHASE DETECTOR LOCK DETECTOR LOCK CGMVDV MC68HC908AZ60 — Rev 2.0 130 CLOCK SELECT CIRCUIT BCS CGMXFC V SS VRS7–VRS4 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG BANDWIDTH INTERRUPT CONTROL CONTROL AUTO ACQ PLLIE PLLF MUL7–MUL4 CGMVCLK FREQUENCY DIVIDER Figure 1 ...
Page 133
... Modulo VCO frequency divider Phase detector Loop filter Lock detector Clock Generator Module (CGM) Clock Generator Module (CGM) Functional Description VRS7 VRS6 VRS5 PPG $001E MC68HC908AZ60 — Rev 2.0 Bit VRS4 0 131 ...
Page 134
... The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f condition based on this comparison. MC68HC908AZ60 — Rev 2.0 132 is equal to the nominal center-of-range VRS , (4.9152 MHz) times a linear factor L or (L)f ...
Page 135
... ACQ bit is set. PLL Bandwidth Control Register Base Clock Selector Circuit Clock Generator Module (CGM) Clock Generator Module (CGM) Functional Description on page 143. on page 137. The PLL is on page 143. If PLL on page 137. If the VCO is selected as Interrupts on page 147. MC68HC908AZ60 — Rev 2.0 133 ...
Page 136
... The following conditions apply when in manual mode: • • • • • MC68HC908AZ60 — Rev 2.0 134 The ACQ bit (See PLL Bandwidth Control Register read-only indicator of the mode of the filter. See Modes on page 133. The ACQ bit is set when the VCO frequency is within a certain ...
Page 137
... N f VCLK Example VCLK f . BUSDES Clock Generator Module (CGM) Clock Generator Module (CGM) Functional Description Definition . BUSDES . VCLKDES f BUSDES 8 MHz = 32 MHz , equal to the crystal frequency, RCLK f RCLK = 8 . VCLK RCLK 4 MHz = 32 MHz , and compare f BUS BUS MC68HC908AZ60 — Rev 2.0 with 135 ...
Page 138
... Using the value 4.9152 MHz for f 8. Calculate the VCO center-of-range frequency, f NOTE: For proper operation, Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9. Program the PLL registers accordingly: MC68HC908AZ60 — Rev 2.0 136 f VCLK f = ------------- ...
Page 139
... A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See page 137. Figure Clock Generator Module (CGM) Clock Generator Module (CGM) Functional Description Programming the PLL Base Clock Selector Circuit 3. Figure 3 shows only the logical MC68HC908AZ60 — Rev 2.0 on page on 137 ...
Page 140
... Figure 3 • • Routing should be done with great care to minimize signal cross talk and noise. (See information and more information on the filter capacitor’s value and its effects on PLL performance). MC68HC908AZ60 — Rev 2.0 138 Crystal Fixed capacitor Tuning capacitor, C ...
Page 141
... CGMXFC pin as possible with minimum routing distances and no routing of other signals across the C 13-cgm MOTOROLA CGMXCLK * Figure 3. CGM External Connections should be placed as close to the F connection. F Clock Generator Module (CGM) Clock Generator Module (CGM) I/O Signals BYP MC68HC908AZ60 — Rev 2.0 139 ...
Page 142
... CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. CGMINT is the CPU interrupt signal generated by the PLL lock detector. MC68HC908AZ60 — Rev 2.0 140 is a power pin used by the analog portions of the PLL. Connect the pin to the same voltage potential as the V ...
Page 143
... PLLIE PLLON Unimplemented Figure 4. PLL Control Register (PCTL PLL CPU interrupt requests enabled 0 = PLL CPU interrupt requests disabled Clock Generator Module (CGM) Clock Generator Module (CGM) CGM Registers BCS MC68HC908AZ60 — Rev 2.0 Bit 141 ...
Page 144
... VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off MC68HC908AZ60 — Rev 2.0 142 1 = Change in lock condition change in lock condition ...
Page 145
... In manual operation, forces the PLL into acquisition or tracking mode $001D Bit LOCK AUTO ACQ XLD Unimplemented Figure 5. PLL Bandwidth Control Register (PBWC) Clock Generator Module (CGM) Clock Generator Module (CGM) CGM Registers on page 137 MC68HC908AZ60 — Rev 2.0 Bit 143 ...
Page 146
... XLD — Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. MC68HC908AZ60 — Rev 2.0 144 1 = Automatic bandwidth control 0 = Manual bandwidth control 1 = VCO frequency correct or locked ...
Page 147
... MUL5 MUL4 Figure 6. PLL Programming Register (PPG) on page 135). A value the multiplier Clock Generator Module (CGM) Clock Generator Module (CGM) CGM Registers Bit 0 VRS7 VRS6 VRS5 VRS4 Circuits on page 131 and MC68HC908AZ60 — Rev 2.0 145 ...
Page 148
... VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908AZ60 — Rev 2.0 146 Table 3. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 ...
Page 149
... PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 21-cgm MOTOROLA Clock Generator Module (CGM) Clock Generator Module (CGM) Interrupts MC68HC908AZ60 — Rev 2.0 147 ...
Page 150
... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. MC68HC908AZ60 — Rev 2.0 148 Clock Generator Module (CGM) Break Module ...
Page 151
... Acquisition time is based on an initial frequency error, Clock Generator Module (CGM) Clock Generator Module (CGM) Acquisition/Lock Time Specifications . trk MC68HC908AZ60 — Rev 2.0 149 ...
Page 152
... The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor MC68HC908AZ60 — Rev 2.0 150 (f – not more than 100% ...
Page 153
... fact , (see Electrical Specifications fact , choose the voltage potential at which the DDA Clock Generator Module (CGM) Clock Generator Module (CGM) Acquisition/Lock Time Specifications on page 151. . The DDA on page 150, V DDA ------------ - f rdv on page MC68HC908AZ60 — Rev 2.0 151 ...
Page 154
... In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See Automatic PLL Bandwidth Modes clock cycles, n tracking mode entry tolerance, MC68HC908AZ60 — Rev 2.0 152 Correct selection of filter capacitor, C Capacitor on page 151). Room temperature operation ...
Page 155
... Clock Generator Module (CGM) Clock Generator Module (CGM) Acquisition/Lock Time Specifications , is required to ascertain that the TRK . Therefore, the Lock /f , and the ACQ RDV /f TRK RDV Base Clock Selector Circuit Parametric Influences on MC68HC908AZ60 — Rev 2.0 . Also, on 153 ...
Page 156
... MC68HC908AZ60 — Rev 2.0 154 Clock Generator Module (CGM) MOTOROLA ...
Page 157
... MOTOROLA Resets caused by the LVI module Power to the LVI module LVI enabled during stop mode Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) Computer operating properly module (COP) Stop instruction enable/disable. Configuration Register (CONFIG-1) MC68HC908AZ60 — Rev 2.0 155 ...
Page 158
... LVISTOP bit must logic 1. Take note that by enabling the LVI in stop mode, the stop I LVIRST — LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module. (See Low-Voltage Inhibit (LVI) MC68HC908AZ60 — Rev 2.0 156 falls to a voltage, LVI DD TRIPF ...
Page 159
... STOP instruction enabled 0 = STOP instruction treated as illegal opcode 1 = COP module disabled 0 = COP module enabled Configuration Register (CONFIG-1) Configuration Register (CONFIG-1) Functional Description Low-Voltage Inhibit (LVI) on page 179 – 2 CGMXCLK cycles 18 4 – 2 CGMXCLK cycles on page 179). MC68HC908AZ60 — Rev 2.0 on 157 ...
Page 160
... MC68HC908AZ60 — Rev 2.0 158 Configuration Register (CONFIG-1) 4-config-1 MOTOROLA ...
Page 161
... MOTOROLA Configures either the MC68HC08AZxx emulator or the MC68HC08ASxx emulator Disables the CAN module $FE09 Bit MSCAND Figure 1. Configuration Register (CONFIG-2) Configuration Register (CONFIG- Bit AZxx MC68HC908AZ60 — Rev 2.0 159 ...
Page 162
... AZxx — AZxx Emulator Enable Bit AZxx enables the MC68HC08AZxx emulator configuration. This bit will be 0 out of reset. NOTE: AZxx bit is reset by a POWER-ON-RESET only. MC68HC908AZ60 — Rev 2.0 160 on page 331 MSCAN module disabled 0 = MSCAN Module enabled 1 = MC68HC08AZxx emulator enabled ...
Page 163
... The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. • • • • 1-brk MOTOROLA Accessible I/O Registers during Break Interrupts CPU-Generated Break Interrupts Software-Generated Break Interrupts COP Disabling during Break Interrupts Break Module MC68HC908AZ60 — Rev 2.0 161 ...
Page 164
... CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. MC68HC908AZ60 — Rev 2.0 162 A CPU-generated address (the address in the program counter) matches the contents of the break address registers. ...
Page 165
... Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) Break Module Break Module Functional Description BRKL BSCR $FE0D $FE0E MC68HC908AZ60 — Rev 2.0 Bit 0 Bit 8 0 Bit 163 ...
Page 166
... If so, the user can modify the return address on the stack by subtracting one from it. (See on page 123). The break module is inactive in stop mode. The STOP instruction does not affect break module register states. MC68HC908AZ60 — Rev 2.0 164 SIM Break Status Register Break Module is present on the ...
Page 167
... Figure 3. Break Status and Control Register (BSCR Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match 1 = (When read) Break address match 0 = (When read) No break address match Break Module Break Module Break Module Registers MC68HC908AZ60 — Rev 2.0 Bit 165 ...
Page 168
... The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Register: Address: Read: Write: Reset: Read: Write: Reset: MC68HC908AZ60 — Rev 2.0 166 BRKH BRKL $FE0C $FE0D Bit Bit 15 14 ...
Page 169
... Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. 1-mon MOTOROLA Monitor ROM (MON) MC68HC908AZ60 — Rev 2.0 167 ...
Page 170
... All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. MC68HC908AZ60 — Rev 2.0 168 Normal User-Mode Pin Functionality One Pin Dedicated to Serial Communication between Monitor ...
Page 171
... Functional Description V DD 68HC08 10 k RST 0 IRQ V DDA V /V DDA CGMXFC 0.1 F OSC1 4.9152 MHz OSC2 V SSA 0 PTA0 5 PTC3 PTC0 A (SEE PTC1 B NOTE.) MC68HC908AZ60 — Rev 2.0 DDAREF 169 ...
Page 172
... CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. MC68HC908AZ60 — Rev 2.0 170 shows the pin conditions for entering monitor mode. Table 1. Mode Selection ...
Page 173
... SIM PP 5.0 Volt DC Electrical Characteris- Figure 2 and Figure NEXT START STOP BIT 6 BIT 7 BIT BIT NEXT START STOP BIT 6 BIT 7 BIT BIT STOP NEXT BIT 6 BIT 7 BIT START BIT MC68HC908AZ60 — Rev 2.0 SWI Vector Low $FFFD $FEFD 3.) 171 ...
Page 174
... When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT MC68HC908AZ60 — Rev 2.0 172 Figure 4, the monitor ROM immediately echoes each READ ADDR. HIGH ADDR. HIGH Figure 4 ...
Page 175
... READ, read memory WRITE, write memory IREAD, indexed read IWRITE, indexed write READSP, read stack pointer RUN, run user program READ ADDR. HIGH ADDR. HIGH Monitor ROM (MON) Monitor ROM (MON) Functional Description ADDR. LOW ADDR. LOW DATA RESULT MC68HC908AZ60 — Rev 2.0 173 ...
Page 176
... Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR ECHO MC68HC908AZ60 — Rev 2.0 174 ADDR. HIGH ADDR. HIGH ADDR. LOW IREAD IREAD DATA Monitor ROM (MON) ADDR. LOW DATA ...
Page 177
... Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR ECHO 9-mon MOTOROLA IWRITE IWRITE ECHO READSP READSP SP HIGH Monitor ROM (MON) Monitor ROM (MON) Functional Description DATA DATA SP LOW RESULT MC68HC908AZ60 — Rev 2.0 175 ...
Page 178
... This supports designs which use the MSCAN module, which is generally clocked from a 4MHz, 8MHz or 16MHz crystal. The table below outlines the available baud rates for a range of crystals and how they can match baud rate. MC68HC908AZ60 — Rev 2.0 176 SENT TO MONITOR RUN ...
Page 179
... Monitor ROM (MON) Monitor ROM (MON) Functional Description Error % PTC3=1 PTC3=0 PTC3=1 28.8 0.64 0.63 900 0.64 0.64 1800 0.64 0.64 3600 0.64 0.64 3840 1.08 1.08 4430 0.49 0.50 7200 0.64 0.64 14400 0.64 0.64 MC68HC908AZ60 — Rev 2.0 177 ...
Page 180
... After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bytes. MC68HC908AZ60 — Rev 2.0 178 4096 + 32 CGMXCLK CYCLES 24 CGMXCLK CYCLES 256 CGMXCLK CYCLES (ONE BIT TIME) ...
Page 181
... COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 184 The COP module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter. 1-cop MOTOROLA Computer Operating Properly Module (COP) MC68HC908AZ60 — Rev 2.0 179 ...
Page 182
... Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. MC68HC908AZ60 — Rev 2.0 180 . During the break state Computer Operating Properly Module (COP) ...
Page 183
... COPCTL WRITE COPD FROM CONFIG-1 RESET CLEAR COP COPCTL WRITE COPL FROM CONFIG-1 Figure 1. COP Block Diagram Computer Operating Properly Module (COP) Computer Operating Properly Module (COP) Figure 6-BIT COP COUNTER COUNTER MC68HC908AZ60 — Rev 2.0 I/O Signals 1. RESET RESET STATUS REGISTER 181 ...
Page 184
... The COPL signal reflects the state of the COP rate select bit. (COPL) in the configuration register. (See page 155). MC68HC908AZ60 — Rev 2.0 182 on page 183), clears the COP counter and clears Configuration Register (CONFIG-1) Configuration Register (CONFIG-1) ...
Page 185
... Low Byte of Reset Vector Clear COP Counter Unaffected by Reset Figure 2. COP Control Register (COPCTL) pin or on the RST pin. PP Computer Operating Properly Module (COP) Computer Operating Properly Module (COP) COP Control Register present on the Hi MC68HC908AZ60 — Rev 2.0 Bit 0 183 ...
Page 186
... The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. The COP is disabled during a break interrupt when V RST pin. MC68HC908AZ60 — Rev 2.0 184 Computer Operating Properly Module (COP) is present on the Hi ...
Page 187
... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Functional Description 186 Polled LVI Operation 188 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 LVI Interrupts 189 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Wait Mode 190 Stop Mode 190 1-lvi MOTOROLA Low-Voltage Inhibit (LVI) MC68HC908AZ60 — Rev 2.0 185 ...
Page 188
... CPU cycles. NOTE: Note that short V responsibility to ensure a clean V voltage range if normal microcontroller operation guaranteed. MC68HC908AZ60 — Rev 2.0 186 pin and can force a reset when the V DD Programmable LVI Reset Programmable Power Consumption ...
Page 189
... Stop Mode Filter Bypass ANLGTRIP LVISTOP FROM CONFIG-1 Figure 1. LVI Module Block Diagram Low-Voltage Inhibit (LVI) Low-Voltage Inhibit (LVI) Functional Description Configuration Register DD for only one TRIPR Forced Reset Operation FROM CONFIG-1 LVIRST LVIOUT MC68HC908AZ60 — Rev 2.0 rises LVI RESET 187 ...
Page 190
... LVIRST bits must be at logic 1 to enable the LVI module and to enable LVI resets. The V supply noise. In order for the LVI module to reset the MCU,V remain at or below the LVI cycles. V MCU out of reset. MC68HC908AZ60 — Rev 2.0 188 Bit Unimplemented Figure 2. LVI I/O Register Summary by polling the LVIOUT bit ...
Page 191
... LVI TRIPF voltage falls below the DD Table LVIOUT For Number of CGMXCLK Cycles: Any Between 32 and CGMXCLK Cycles Any Previous Value MC68HC908AZ60 — Rev 2.0 level . Bit 1). Reset 189 ...
Page 192
... Note that the LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application V intended that users operate the microcontroller at lower than specified operating voltage V MC68HC908AZ60 — Rev 2.0 190 voltage collapsing completely to an unsafe level not DD . ...
Page 193
... This section describes the nonmaskable external interrupt (IRQ) input. Features include: • • • • 1-irq MOTOROLA Dedicated External Interrupt Pin (IRQ/V Hysteresis Buffer Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity Automatic Interrupt Acknowledge External Interrupt Module (IRQ MC68HC908AZ60 — Rev 2.0 191 ...
Page 194
... ACK1 VECTOR FETCH DECODER IRQ/V PP MC68HC908AZ60 — Rev 2.0 192 Figure 1 shows the structure of the IRQ module. pin are latched into the IRQ latch Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. Software clear — ...
Page 195
... Bit Read Write Reserved Vector fetch or software clear Return of the interrupt pin to logic 1 External Interrupt Module (IRQ) External Interrupt Module (IRQ) Functional Description IRQF1 0 IMASK1 MODE1 R R ACK1 pin. PP Figure 2 MC68HC908AZ60 — Rev 2.0 Bit 0 ). 193 ...
Page 196
... MC68HC908AZ60 — Rev 2.0 194 FROM RESET YES I BIT SET? NO YES INTERRUPT? NO STACK CPU REGISTERS. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 2. IRQ Interrupt Flowchart External Interrupt Module (IRQ) SET I BIT. ...
Page 197
... A reset will clear the latch and the PP External Interrupt Module (IRQ) External Interrupt Module (IRQ) pin is both falling-edge sensitive PP PP pin. A falling PP pin is falling-edge sensitive only. PP MC68HC908AZ60 — Rev 2.0 IRQ Pin pin and pin PP pin to PP 195 ...
Page 198
... To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect on the IRQ latch. MC68HC908AZ60 — Rev 2.0 196 SIM Break Flag Control Register External Interrupt Module (IRQ) pin ...
Page 199
... IRQ interrupt not pending 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled External Interrupt Module (IRQ) External Interrupt Module (IRQ) IRQ Status and Control Register interrupt pin IRQF1 0 IMASK1 R R ACK1 MC68HC908AZ60 — Rev 2.0 Bit 0 MODE1 0 197 ...
Page 200
... MODE1 — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ/V pin. Reset clears MODE1. MC68HC908AZ60 — Rev 2.0 198 1 = IRQ/V interrupt requests on falling edges and low levels IRQ/V interrupt requests on falling edges only PP External Interrupt Module (IRQ) ...