LAN83C183-JD Standard Microsystems, LAN83C183-JD Datasheet
LAN83C183-JD
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LAN83C183-JD Summary of contents
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... The LAN83C183 is ideal as a media interface for 100BASE-TX/10BASE-T adapter cards, PC Cards, motherboards, mobile applications, repeaters, switching hubs, and external PHYs. The LAN83C183 operates from a single 3.3V supply. All inputs and outputs are 5V-tolerant and can directly interface to other 5V devices. SMSC DS – LAN83C183 ...
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... CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – LAN83C183 ORDERING INFORMATION Order Number: LAN83C183-JD 64-Pin TQFP Package 2 Rev. 12/14/2000 ...
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... FULL/HALF DUPLEX MODE 1.5.1 1.5.2 1.5.3 1.6 REPEATER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.7 10/100 MBITS/S SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.7.1 1.7.2 1.7.3 1.8 JABBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SMSC DS – LAN83C183 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Oscillator and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Decoder Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Twisted-Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Twisted-Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FX Transmitter and Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Clock and Data Recovery Link Integrity and AutoNegotiation . . . . . . . . . . . . . . . . . . . . . . . . . 31 Link Indication ...
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... ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2.1 5.2.2 5.3 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.1 SMSC DS – LAN83C183 100 Mbits/s JAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 Mbits/s JAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Control Register (Register Status Register (Register PHY ID 1 Register (Register PHY ID 2 Register (Register AutoNegotiation Advertisement Register (Register AutoNegotiation Remote End Capability Register (Register Configuration 1 Register (Register 16) ...
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... PINOUTS AND PACKAGE DRAWINGS 107 5.5.1 5.5.2 5.6 MECHANICAL DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SMSC DS – LAN83C183 Transmit Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Receive Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Collision and JAM Timing Characteristics . . . . . . . . . . . . . . . . . . . 97 Link Pulse Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100 Jabber Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MI Serial Port Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . 105 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LAN83C183 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5 Rev. 12/14/2000 ...
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... SMSC DS – LAN83C183 6 Rev. 12/14/2000 ...
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... Figures 1.1 LAN83C183 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 100BASE-TX/FX and 10BASE-T Frame Format . . . . . . . . . . . . . . . . . . . . . 13 1.3 MII Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 TP Output Voltage Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 TP Input Voltage Template (10 Mbits/ 1.6 Link Pulse Output Voltage Template (10 Mbits/ 1.7 NLP vs FLP Link Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8 SOI Output Voltage Template - 10 Mbits 2.1 Device Logic Diagram 4.1 MI Serial Port Frame Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4 ...
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... SMSC DS – LAN83C183 8 Rev. 12/14/2000 ...
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... Transmit Timing 5.10 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.11 Collision and Jam Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.12 Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.13 Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.14 LED Driver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.15 MI Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.16 LAN83C183 Pin List (by Signal Category 107 5.17 LAN83C183 Pin List (by Pin Number 110 SMSC DS – LAN83C183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9 Rev. 12/14/2000 ...
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... SMSC DS – LAN83C183 10 Rev. 12/14/2000 ...
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... Section 1.11, “Powerdown” Section 1.12, “Receive Polarity Correction” 1.1 OVERVIEW This section gives a brief overview of the device functional operation. The LAN83C183 is a complete 10/100 Mbits/s Ethernet Media Interface IC. A block diagram is shown in 1.1.1 Channel Operation The PHY operates in the 100BASE-TX or 100BASE-FX modes at 100 Mbits/ the 10BASE-T mode at 10 Mbits/s ...
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... Figure 1.1 LAN83C183 Device Block Diagram OSCIN Oscillator RESETn RX_EN/JAMn 4B5B RPTR Encoder TX_CLK TXD[3:0] Manchester TX_EN Encoder TX_ER/TXD4 COL Controller Collision Interface (MII RX_CLK or RXD[3:0] FBI) CRS RX_DV RX_ER/RXD4 MDC Serial 4B5B MDIO Port Decoder MDINTn/MDA4n (MI) PLED[3:0]n MDA[3:0]n LED Drivers PLED[5:4]n ...
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... Gap PREAMBLE IDLE SSD PREAMBLE DA, SA, LN, LLC DATA, FCS = IDLE SSD PREAMBLE DA, SA, LN, LLC DATA, FCS = IDLE PREAMBLE DA, SA, LN, LLC DATA, FCS = SMSC DS – LAN83C183 Ethernet MAC Frame SFD 100BASE-TX Data Symbols SFD ...] IDLE = [ SSD = [ ...
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... NRZ format. The 4B5B decoder and descrambler then decodes and unscrambles the NRZ data, respectively, and sends it out of the Controller Interface SMSC DS – LAN83C183 Figure 1.3 MII Frame Format a. MII Frame Format ...
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... The data rate is 10 Mbits/s instead of 100 Mbits/s, The twisted-pair symbol data is two-level Manchester instead of ternary MLT-3. The transmitter generates link pulses during the idle period The transmitter detects the jabber condition The receiver detects link pulses and implements the AutoNegotiation algorithm SMSC DS – LAN83C183 Table 1.2. Bit Value 1 ...
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... The device has an MII interface to an external Ethernet Media Access Controller (MAC). MII (100 Mbits/s) – 802.3 and shown in outlined in IEEE 802.3. The LAN83C183 can directly connect, without any external logic, to any Ethernet controller or other device that also complies with the IEEE 802.3 MII specifications. SMSC DS – LAN83C183 shows the main blocks, along with their associated signals ...
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... When this signal is asserted, the device substitutes an error nibble in place of the normal data nibble that was clocked in on TXD[3:0]. The error nibble is defined to be the /H/ symbol, which is defined in IEEE 802.3 and shown in SMSC DS – LAN83C183 Figure 1.3. When all data on TXD[3:0] has been latched into the ...
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... CRS and RX_DV are asserted on the falling edge of RX_CLK. The assertion of RX_DV indicates that valid data is clocked out on RXD[3:0] on the falling edge of the RX_CLK. The RXD[3:0] data has the same frame structure as the TXD[3:0] data and is specified in IEEE 802.3 and shown in SMSC DS – LAN83C183 Table 1.3 4B/5B Symbol Mapping Description 5B Code ...
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... SELECTION OF MII OR FBI FBI Selection – bypassed. Bypassing the encoder/decoder passes the 5B symbols between the receiver/transmitter directly to the FBI without any alterations or substitutions. To SMSC DS – LAN83C183 MII 10 Mbits/s operation is identical to 100 Mbits/s operation except: Figure 1.3. When the end of packet is detected, CRS and RX_DV ...
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... COL If the MI address lines, MDA[4:0]n, are pulled HIGH during reset or powerup, the LAN83C183 powers up and resets with the MII and FBI disabled. Otherwise, the LAN83C183 powers up and resets with the MII and FBI enabled. In addition, when the R/J_CFG bit in the MI serial port Configuration 1 register is LOW, the RX_EN/JAMn pin is configured for RX_EN operation ...
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... Delimiter (ESD) (/T/R/ symbols) to the end of each packet, as defined in IEEE 802.3 and shown in (idle period), with a continuous stream of idle symbols, as shown in 1.2.3.2 MANCHESTER ENCODER (10 MBITS/S) The Manchester Encoder shown in combines clock and non-return to zero inverted (NRZI) data such that the first half of SMSC DS – LAN83C183 Table 1.4 4B/5B Symbol Mapping Description 5B Code Data 0 11110 ...
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... Configuration 1 register bypasses the 4B5B decoder. When this bit is set, 5B code words are passed directly to the controller interface from the descrambler without any of the alterations described in SMSC DS – LAN83C183 Section 1.2.3.1, “4B5B Encoder (100 Mbits/s),” subsection entitled “FBI Selection” Section 1.2.4, “Decoder,” page ...
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... DESCRAMBLER BYPASS Setting the Bypass Encoder/Decoder bit (BYP_SCR) in the MI serial port Configuration 1 register bypasses the descrambler. When this bit is set, 5B data bypasses the descrambler and goes directly from the 100BASE-T receiver to the 4B5B decoder. SMSC DS – LAN83C183 on page 1-19. Figure 1.1 is used in 100BASE-TX operation. The 23 Rev ...
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... During the idle period, no output signals are transmitted on the TP outputs except for link pulses. SMSC DS – LAN83C183 and Table 1.5. The waveshaper replaces and eliminates external filters on ...
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... SMSC DS – LAN83C183 Figure 1.4 TP Output Voltage Template ...
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... Table 1.6 Transmit Level Adjust TLVL[3:0] Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SMSC DS – LAN83C183 Time (ns) Internal MAU 111 110 100 110 90 Table 1.6. The adjustment range is approximately -14% Gain 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 0.98 ...
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... DC component of the input waveform that the external transformers have removed. The comparators convert the equalized signal back to digital levels and qualify the data with the squelch circuit. The MLT3 decoder takes the three-level SMSC DS – LAN83C183 shielded twisted-pair cable can drive other digital inputs. See DD for more detailed information on the LED outputs ...
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... In the unsquelch state, the receive threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. When the receiver is in the unsquelch state, the input signal is considered valid. SMSC DS – LAN83C183 Figure 1.5 The TP inputs are biased by internal resistors Short Bit Slope 0 ...
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... FXO+/- pins. The output driver is a differential current source that is able to drive a 100 drive an external fiber optic transceiver. The FX transmitter meets all the requirements defined in IEEE 802.3. SMSC DS – LAN83C183 or can drive another digital input. See DD for more detailed information on the LED outputs. ...
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... SD/FXDISn buffer trip level with the SD_THR pin allows this trip level to be referenced to an external supply, which facilitates connection to an external fiber optic transceiver. If the device connected to a 3.3V external fiber optic transceiver, SD_THR must be tied to GND. SMSC DS – LAN83C183 Gain 1.30 1.15 ...
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... Mbits/s and Half or Full Duplex operation. The different standard link integrity algorithms for 10 and 100 Mbits/s modes are described in following subsections. SMSC DS – LAN83C183 1.3V, which can be accomplished with an external resistor divider. 31 Figure 1 ...
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... The AutoNegotiation algorithm is the same algorithm defined in IEEE 802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast link pulses (FLPs), to pass bits of signaling data back and forth between the LAN83C183 and a remote device. The transmit FLP pulses meet the template specified in IEEE 802.3 and SMSC DS – ...
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... The remote device does the same, and the capabilities read back from the remote device are stored in the MI serial port AutoNegotiation Remote End Capability register. The LAN83C183 negotiation algorithm then matches its capabilities to the remote device’s capabilities and determines the device configuration according to the priority resolution algorithm defined in IEEE 802 ...
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... LED from either V Both the PLED3n and PLED0n outputs can also drive another digital input. Refer to Section 1.2.14, “LED Drivers,” page 1-36 PLED[3:0]n pins and their default values. SMSC DS – LAN83C183 for a description on how to program the 34 Table 1 ...
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... LOW for 100 ms every time a collision occurs. The PLED2n output is open drain with a pullup resistor and can drive an LED from V See Section 1.2.14, “LED Drivers,” page 1-36 LED output pins to indicate various conditions. SMSC DS – LAN83C183 or can drive another digital input. DD for more details on how to program the 35 ...
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... When the PLED[5:0]n pins are programmed for their normal functions (PLED_[1:0] = 0b11), the pin output states indicate four specific types of events. The LED Normal SMSC DS – LAN83C183 . The PLED[1:0]n outputs have both pullup and pulldown driver transistors Section 1.2.14.2, “LED Normal Function Select Table 1 ...
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... XMT ACT 1 0b00 RCV ACT XMT ACT 1. The LAN83C183 powers up with the LED_DEF[1:0] bits set to the default value of 0b00. The default Normal Functions for PLED[5:0]n are Receive Activity, Transmit Activity, Link 100, Activity, Full Duplex, and Link 10, respectively. Symbol RCV ACT ...
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... Because the idle period in 10 Mbits/s mode is defined to be when there is no valid data on the TP inputs, the start of packet for 10 Mbits/s mode is detected when the TP squelch circuit detects valid data. When the start of packet is detected, CRS is asserted as described in 1.2.8.4, “Squelch (10 Mbits/s),” page 1-29 SMSC DS – LAN83C183 Table 1.4 and Figure 1.2. ...
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... The TP transmitter generates the transmit SOI pulse and inserts it at the end of the data packet after TX_EN has been deasserted. The transmit waveshaper shapes the transmitted SOI output pulse at the TP output to meet the pulse template requirements specified in IEEE 802.3 Clause 14 and shown in SMSC DS – LAN83C183 Table 1.4 Figure 1.2. ...
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... The TP receiver senses missing data transitions in order to detect the receive SOI pulse. Once the SOI pulse is detected, data reception is ended and the CRS and RX_DV pins are deasserted. SMSC DS – LAN83C183 Figure 1.8 SOI Output Voltage Template - 10 Mbits/s 4 3.1 V 0.5 V/ns ...
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... When diagnostic loopback is enabled, the TXD[3:0] data is looped back onto RXD[3:0], TX_EN is looped back onto CRS, RX_DV operates normally, the TP receive and transmit paths are disabled, the transmit link pulses are SMSC DS – LAN83C183 Section 1.2.11, “Link Integrity and or GND and can also drive a digital input. ...
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... REPEATER MODE The LAN83C183 uses the standard MII as the physical interface for MII-based repeater cores. The LAN83C183 has one predefined repeater mode. To enable this mode, assert the RPTR pin. When this repeater mode is enabled with the RPTR pin: TX_EN to CRS loopback is disabled ...
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... This section describes automatic JAM operation for both 100 and 10 Mbits/s operation. 1.9.1 100 Mbits/s JAM The LAN83C183 has an automatic JAM feature that causes the device to automatically transmit a JAM packet if receive activity is detected. If automatic JAM is enabled, the following JAM packet is transmitted on TPO± when the RX_EN/JAMn ...
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... V operation 50 ms after the reset sequence is initiated. 1.11 POWERDOWN To powerdown the LAN83C183, set the Powerdown bit (PDN) in the MI serial port Control register. In powerdown mode, the TP outputs are in a high-impedance state, all functions are disabled except the MI serial port, and the power consumption is reduced to a minimum ...
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... TX_ER/TXD4 Interface (MII) TXD[3:0] RX_CLK RX_EN/JAMn RXD[3:0] RX_DV RX_ER/RXD4 MDC Management MDIO Interface MDINTn/MDA4n SMSC DS – LAN83C183 is a logic diagram for the device. Figure 2.1 Device Logic Diagram LAN83C183 10/100 Mbit/s Ethernet Physical Layer Device (PHY) CRS 45 PLED5n PLED4n PLED3n/MDA3n PLED2n/MDA2n LEDs/ ...
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... SD/FXDISn SD_THR TPO+/FXI- TPO-/FXI+ TPI+/FXO- TPI-/FXO+ SMSC DS – LAN83C183 Transmit Current Set An external resistor connected between the REXT pin and GND sets the output current for the TP and FX transmit outputs. FX Signal Detect Input/FX Interface Disable When this pin is not tied to GND, the FX interface is enabled and this pin becomes an ECL signal detect input ...
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... RX_DV RX_EN/JAMn Receive Enable Input RXER/RXD4 TX_CLK TXD[3:0] SMSC DS – LAN83C183 Carrier Sense Output The CRS output is asserted HIGH when valid data is detected on the receive TP inputs. CRS is clocked out on the falling edge of RX_CLK. Clock Oscillator Input There must be either a 25 MHz crystal between this pin and GND MHz clock applied to this pin ...
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... MDC MDINTn/MDA4n MDIO 2.4 MISCELLANEOUS SIGNALS ANEG SMSC DS – LAN83C183 Transmit Enable Input TX_EN must be asserted HIGH to indicate that data on TXD and TX_ER is valid. TX_ER is clocked in on the rising edge of TX_CLK and OSCIN. The TXER pin, when asserted, causes a special pattern to be trans- mitted on the twisted-pair outputs in place of normal data, and it is clocked in on the rising edge of TX_CLK when TX_EN is asserted ...
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... COL DPLX NC RESETn RPTR SPEED SMSC DS – LAN83C183 Collision Output COL is asserted HIGH when a collision between transmit and receive data is detected. Full/Half Duplex Select Input When the ANEG pin is LOW, the DPLX pin selects Half/Full Duplex operation. DUPLX Pin Meaning HIGH ...
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... LEDS PLED5n PLED4n PLED3n/MDA3n PLED2n/MDA2n SMSC DS – LAN83C183 Receive LED Output Pullup O.D. The function of this pin Receive Activity Detect output. The pin can drive an LED from V DD PLED5n Pin Function HIGH No receive activity LOW Receive packet occurred (held LOW for 100 ms) Transmit LED Output Pullup O ...
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... POWER SUPPLY GND V DD SMSC DS – LAN83C183 Programmable LED Output/MI Address Bit The default function of this pin Full Duplex Detect output. This pin can also be programmed through the MI serial port to indi- cate other events or be user controlled. This pin can drive an LED from both V and GND ...
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... SMSC DS – LAN83C183 52 Rev. 12/14/2000 ...
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... This chapter contains a description of the registers accessed over the management interface (MI) serial interface. It contains the following sections: Section 3.1, “Bit Types” Section 3.2, “MI Serial Port Register Summary” Section 3.3, “Registers” For further information about the operation of the MI serial interface, see Management SMSC DS – LAN83C183 Interface. 53 Chapter 4, Rev. 12/14/2000 ...
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... Symbol Name W Write R Read R/W Read/Write R/WSC Read/Write, Self-Clearing R/LL Read/Latching LOW R/LH Read/Latching HIGH R/LT Read/Latching on transition SMSC DS – LAN83C183 Table 3.1 MI Register Bit Type Definition Write Cycle Input No operation, Hi-Z Input Input No operation, Hi-Z No operation, Hi-Z No operation, Hi-Z 54 Definition Read Cycle No operation, Hi-Z Output Output Output ...
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... OUI11 PHY ID #2 Register (register 3) – 15 OUI19 7 PART3 AutoNegotiation Advertisement Register (register 4) – TX_HDX AutoNegotiation Remote End Capability Register (register 5) – TX_HDX SMSC DS – LAN83C183 LPBK SPEED ANEG_EN CAP_TXF CAP_TXH CAP_TF CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG ...
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... Status Output Register (register 18) – 15 INT 7 SPD_DET DPLX_DET Mask Register (register 19 MASK_INT MASK_LNK_FAIL MASK_LOSS_SYNC MASK_CWRD MASK_SSD MASK_ESD MASK_RPOL MASK_JAB 7 6 MASK_SPD_DET MASK_DPLX_DET Reserved Register (register 20) – SMSC DS – LAN83C183 XMT_DIS XMT_PDN TXEN_CRS BYP_ENC 6 5 RLVL0 TLVL[3: PLED3_0 PLED2_1 PLED2_0 ...
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... PDN Bit 1 0 MII_DIS 1 MII_DIS Bit MDA[3:0]n is not read as 0b1111 at reset time, the MII_DIS default value is changed to 0. SMSC DS – LAN83C183 LPBK SPEED ANEG_EN 6 Reset Meaning Reset. The bit is bit self-clearing in less than or equal to 200 s after reset finishes. ...
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... CAP_TXF 100BASE-TX Full Duplex Capable CAP_TXF Bit 1 0 CAP_TXH 100BASE-TX Half Duplex Capable CAP_TXH Bit 1 0 SMSC DS – LAN83C183 Restart AutoNegotiation process. The bit is self-clearing after reset is finished Normal (default) Duplex Mode Select 1 Full-duplex Half-duplex (default) Collision Test Enable Collision test enabled ...
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... JAB JAB Bit Meaning 1 Jabber detected (same as the JAB bit in “Status Output Register (Register 18),” page 0 Normal (default) SMSC DS – LAN83C183 10BASE-T Full Duplex Capable Meaning Capable of 10BASE-T Full-Duplex (default) Not capable of 10BASE-T Full-Duplex 10BASE-T Half Duplex Capable Meaning Capable of 10BASE-T Half Duplex (default) ...
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... EXREG EXREG Bit 1 0 3.3.3 PHY ID 1 Register (Register 2) 15 OUI3 7 OUI11 OUI[3:18] Company ID, Bits 3–18 SMSC DS – LAN83C183 Extended Register Capable Meaning Extended registers exist (default) Extended registers do not exist OUI4 OUI5 OUI6 OUI12 OUI13 OUI14 OUI[3:18] in this register and OUI[19:24] of the PHY ID 2 register make up the LSI OUI, whose default value is 0x00 ...
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... The default value for this register is 0x01E1 TX_HDX NP NP Bit Next page is not currently supported ACK ACK Bit Meaning 1 0 SMSC DS – LAN83C183 OUI20 OUI21 OUI22 PART2 PART1 PART0 OUI[19:24] in this register and OUI[3:18] of the PHY ID 1 register make up the LSI OUI, whose default value is 0x00 ...
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... Bit CSMA CSMA Bit Meaning Carrier-Sense, Multiple-Access SMSC DS – LAN83C183 Remote Fault Meaning AutoNegotiation remote fault detect No remote fault detect (default) Reserved These bits are reserved and must be remain at the default value of 0b00 for proper device operation 100BASE-T4 Capable ...
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... T4 Bit 1 0 TX_FDX TX_FDX Bit 1 0 TX_HDX TX_HDX Bit 1 0 10_FDX 10_FDX Bit 1 0 SMSC DS – LAN83C183 ACK 10_FDX 10_HDX Next Page Enable Meaning Next Page exists No Next Page (default) Acknowledge Received AutoNegotiation Word recognized Not Recognized (default) ...
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... Bit 1 0 TXEN_CRSTX_EN to CRS Loopback Disable R/W 12 TXEN_CRS Bit 1 0 SMSC DS – LAN83C183 10BASE-TX Half Duplex Capable Meaning Capable of 10BASE-T Half Duplex operation Not capable (default) Reserved These bits are reserved and must be remain at the default value of 0x0 for proper device operation CSMA 802 ...
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... CABLE CABLE Bit 1 0 RLVL0 RLVL0 Bit 1 0 SMSC DS – LAN83C183 Meaning Bypass 4B/5B Encoder/Decoder Normal (default) Meaning Bypass Scrambler/Descrambler Normal (default) Meaning Disable AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances Enable AutoNegotiation with devices that transmit unscrambled idle on powerup and ...
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... SMSC DS – LAN83C183 The transmit output current level is derived from an internal reference voltage and the external resistor on the REXT pin. The transmit level can be adjusted with either the external resistor on the REXT pin, or the four Transmit Level Adjust bits (TLVL[3:0]), as shown. The adjust- ment range is approximately -14% to +16 steps ...
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... JAB_DIS JAB_DIS Bit Meaning 1 0 MREG MREG Bit Meaning 1 0 SMSC DS – LAN83C183 1 Normal (PLED2n pin state is determined from the LED_DEF[1:0] bits (default is Activity). 0b11 is the default for these bits 0 LED tied to PLED2n blinks (toggles 100 ms LOW, then 100 ms HIGH) 1 ...
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... CWRD CWRD Bit 1 0 SSD SSD Bit 1 0 SMSC DS – LAN83C183 Meaning Interrupt signaled with MDIO pulse during idle Interrupt not signaled on MDIO (default) R/J Configuration Select Meaning RX_EN/JAMn pin is configured to be JAMn RX_EN/JAMn pin is configured to be RX_EN (default) Reserved This bit is reserved and must be remain at the default value of 0x0 for proper device operation ...
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... MASK_INT MASK_LNK_FAIL 7 6 MASK_SPD_DET MASK_DPLX_DET MASK_ INT MASK_INT Bit Meaning 1 0 SMSC DS – LAN83C183 End of Stream Error Meaning No End of Stream Delimiter detected on receive data Normal (default) Reversed Polarity Detect Reversed Polarity detect Normal (default) Jabber Detect Jabber detected Normal (default) ...
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... MASK_ RPOL MASK_RPOL Bit 1 0 MASK_ JAB MASK_JAB Bit Meaning 1 0 SMSC DS – LAN83C183 Interrupt Mask - Link Fail Detect Meaning Mask interrupt for LNK_FAIL bit in register 18 (default) No mask Interrupt Mask - Descrambler Loss of Sync Detect Meaning Mask interrupt for LOSS_SYNC bit in register 18 (default) ...
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... R 3.3.11 Reserved Register (Register 20) The default value for this register is 0x0000 SMSC DS – LAN83C183 Interrupt Mask - 10/100 Speed Detect Meaning Mask Interrupt for SPD_DET bit in register 18 (default) No mask Interrupt Mask - 10/100 Duplex Detect Meaning Mask Interrupt for DPLX_DET bit in ...
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... SMSC DS – LAN83C183 72 Rev. 12/14/2000 ...
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... The internal register bits control the configuration and capabilities of the device, and reflect device status. The MI serial port provides access to 11 internal registers and meets all IEEE 802.3 specifications for the Management Interface. SMSC DS – LAN83C183 73 Rev. 12/14/2000 ...
Page 74
... At powerup or reset, the PLED[3:0]n and MDINTn output drivers are 3- stated for an interval called the power-on reset time. During the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the MI serial port physical device addresses. SMSC DS – LAN83C183 74 Rev. 12/14/2000 ...
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... For more detailed timing information on t 4.3 MULTIPLE REGISTER ACCESS Multiple registers can be accessed on a single MI serial port access cycle with the multiple register access feature. Setting the Multiple Register Access Enable (MREG) SMSC DS – LAN83C183 Figure 4.1 shows a timing diagram for a MI serial port 7 ...
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... All the registers have been read or written The serial shift process is halted Data is latched into the device MDIO goes into a high-impedance state. Another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous ones) is detected. SMSC DS – LAN83C183 76 Rev. 12/14/2000 ...
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... IDLE ST[1:0] IDLE ST[1:0] READ WRITE PHYAD[4:0] REGAD[4:0] TA[1:0] D[15:0] SMSC DS – LAN83C183 4.1. Each serial port access cycle consists of 32 bits, exclusive of Figure 4.2 and Figure 4.1 Figure 4.2 shows the MI frame structure. Figure 4.2 MI Serial Frame Structure READ WRITE PHYAD[4:0] Idle Pattern These bits are an idle pattern ...
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... SMSC DS – LAN83C183 Summary”. See Chapter 3, Registers gives a summary of the functions of each register. Table 4.1 MI Serial Port Register Summary Description Name Control Register Stores various configuration bits Status Register Contains device capability and status output bits ...
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... INTERNAL INTERRUPT MDC MDIO Pulled High Externally INTERNAL INTERRUPT MDC B1 MDIO Last Two Bits of Read Cycle SMSC DS – LAN83C183 Figure 4.3. After the interrupt pulse, MDIO goes back to Figure 4.3 MDIO Interrupt Pulse MDIO HI-Z Interrupt Pulse B0 Interrupt Pulse MDIO HI-Z Pulled High Externally 79 Figure 4 ...
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... SMSC DS – LAN83C183 80 Rev. 12/14/2000 ...
Page 81
... It contains the following sections: Section 5.1, “Absolute Maximum Ratings” Section 5.2, “Electrical Characteristics” Section 5.2.2, “FX Characteristics, Transmit” Section 5.3, “AC Electrical Characteristics” Section 5.4, “LED Driver Timing Characteristics” Section 5.5, “Pinouts and Package Drawings” Section 5.6, “Mechanical Drawing” SMSC DS – LAN83C183 81 Rev. 12/14/2000 ...
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... All voltages are specified with respect to GND unless otherwise specified. Parameter V Supply Voltage DD All Inputs and Outputs Package Power Dissipation Storage Temperature Temperature Under Bias Lead Temperature (soldering, 10 sec) Body Temperature (soldering, 30 sec) SMSC DS – LAN83C183 Table 5.1 Absolute Maximum Ratings 0.3V to +4.0V 0.3V to 5.5V 2.0 @ 70° +80 °C 82 Range Units V V ...
Page 83
... Input High Voltage V DD IIL Input Low Current IIH Input High Current VOL Output Low Voltage VOH Output High V DD Voltage V DD CIN Input Capacitance SMSC DS – LAN83C183 ± 1%, no load Table 5.2 DC Characteristics Limit Min Typ Max Unit 0.8 Volt V 1.0 Volt DD 1.5 Volt 0.45 Volt 2 Volt 0 ...
Page 84
... Sym Parameter TOV TP Differential Output Voltage TOVS TP Differential Output Voltage Symmetry TORF TP Differential Output Rise and Fall Time TORFS TP Differential Output Rise and Fall Time Symmetry SMSC DS – LAN83C183 Table 5.2 DC Characteristics (Cont.) Limit Min Typ Max Unit 120 mA 140 mA 190 mA 220 mA ...
Page 85
... Link Pulse Voltage Template TOIV TP Differential Output Idle Voltage TOIA TP Output Current TOIR TP Output Current Adjustment Range TORA TP Output Current TLVL Step Accuracy TOR TP Output Resistance TOC TP Output Capacitance SMSC DS – LAN83C183 Limit Min Typ Max Unit 0.25 nS 1.4 nS 5.0 % See Figure 1.4 See Figure 1.8 See Figure 1 ...
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... TP Input Unsquelch Threshold ROCV TP Input Open Circuit Voltage RCMR TP Input Common Mode Voltage Range RDR TP Input Differential Voltage Range RIR TP Input Resistance RIC TP Input Capacitance SMSC DS – LAN83C183 Limit Min Typ Max Unit 166 500 mV pk 310 540 200 mV pk ...
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... Time Symmetry FODC FXO± Differential Output Duty Cycle Distortion FOJ FXO± Differential Output Jitter FOR FXO± Output Resistance FOC FXO± Output Capacitance SMSC DS – LAN83C183 5% 0.01% 1%, no load Table 5.5 FX Characteristics, Transmit Limit Typ Max Unit VDD - V 0.880 VDD - V 1.620 12 ...
Page 88
... SD/FXDISn VTRIP - Input Low 50 mV Voltage FSDTHR SD_THR Input VDD - Voltage 1. FIR FXI±, 5K SD/FXDISn Input Resistance FIC FX± SD/FXDISn Input Capacitance SMSC DS – LAN83C183 Table 5.6 FX Characteristics, Receive Limit Typ Max Unit V pk VDD - V 0. VDD - VDD - V 1.3V 1. ohm Conditions ...
Page 89
... Input Conditions (all inputs) Output Loading TPO± Open-drain outputs All other digital outputs Measurement Points TPO±, TPI± All other inputs and outputs SMSC DS – LAN83C183 Table 5.7 Test Conditions Parameter Value +70°C V 3.3V ± MHz ± 0.01% REXT 10K ± ...
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... OSCIN Period t2 OSCIN High Time t3 OSCIN Low Time t4 OSCIN to TX_CLK Delay 1. Refer to Figure 5.1 for Timing Diagram OSCIN TX_CLK (100 Mbits/s) TX_CLK (10 Mbits/s) SMSC DS – LAN83C183 Table 5.8 25 MHz Input/Output Clock Limit Min Typ Max 39.996 40 40.004 Figure 5.1 25 MHz Output Timing t ...
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... Transmit SOI Pulse Width t27 PLEDn Delay Time t28 PLEDn Pulse Width 1. Setup time measured with 5 pF loading on TXC. Additional leading will create a delay on TXC rise time, which requires increased setup times. SMSC DS – LAN83C183 Table 5.9 Transmit Timing Limit Min Typ 39.996 40 399 ...
Page 92
... IDLE t 27 PLEDn FBI 100 Mbits/s Same as MII 100 Mbits Except: 1. TX_ER Converted to TXD4 2. RX_ER Converted to RXD4 MII 10 Mbits/s TX_CLK t TX_EN t 17 CRS TXD[3:0] N0 TP0± PLEDn SMSC DS – LAN83C183 ...
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... RXD, RX_ER Delay t38 RX_CLK High Time t39 RX_CLK Low Time t40 SOI Pulse Minimum Width Required for Idle Detection SMSC DS – LAN83C183 shows the Receive AC timing parameters. See Table 5.10 Receive Timing Limit Min Typ Max Unit 200 200 700 130 ...
Page 94
... MII 100 Mbits/s TPI DATA CRS RX_CLK RX RX_DV RXD[3:0] DATA FBI 100 Mbits/s Same as MII 100 Mbits Except: 1. TX_ER converted to RXD4 2. RX_ER converted to TXD4 SMSC DS – LAN83C183 Table 5.10 Receive Timing (Cont.) Limit Min Typ Max Unit ±3 ±13 105 ms ...
Page 95
... Same as MII 100 Mbits Except: 1. TX_ER converted to RXD4 2. RX_ER converted to TXD4 Figure 5.6 Receive Timing, Start of Packet - 10 Mbits/s MII 10 Mbits/s TPI t 31 CRS RX_CLK TX TX RX_DV RXD[3:0] RX_ER t 43 PLEDn SMSC DS – LAN83C183 ...
Page 96
... Figure 5.7 Receive Timing, End of Packet - 10 Mbits/s MII 10 Mbits TPI DATA DATA DATA DATA CRS RX_CLK RX RX_DV RXD[3:0] DATA DATA RX_EN t RX_CLK 46 RXD[3:0] RX_DV RX_ER COL SMSC DS – LAN83C183 SOI DATA DATA DATA DATA DATA Figure 5.8 RX_EN Timing ...
Page 97
... DATA DATA TPI COL PLEDn FBI 100 Mbits/s Same as MII 100 Mbits SMSC DS – LAN83C183 shows the Collision and JAM timing parameters. See for the associated timing diagrams. Table 5.11 Collision and Jam Timing LIMIT MIN TYP MAX 200 700 130 ...
Page 98
... TPI I DATA DATA TPO COL PLEDn FBI 100 Mbits/s Same as MII 100 Mbits Figure 5.12 Collision Timing, Transmit - 10 Mbits/s MII 100 Mbits/s TPI TPO COL PLEDn SMSC DS – LAN83C183 DATA DATA DATA DATA DATA DATA DATA DATA DATA t ...
Page 99
... MII 100 Mbits/s JAMn TPO CRS TPO COL FBI 100 Mbits/s Same as MII 100 Mbits SMSC DS – LAN83C183 Figure 5.13 Collision Test Timing t 57 Figure 5.14 JAM Timing K DATA DATA DATA DATA DATA DATA DATA DATA DATA JAM ...
Page 100
... FLP Receive Link Pulse Minimum Period Required For Data Pulse Detection t75 FLP Receive Link Pulse Maximum Period Required For Data Pulse Detection SMSC DS – LAN83C183 shows the Link Pulse AC timing parameters. See Table 5.12 Link Pulse Timing Limit Min Typ Max See Figure 1 ...
Page 101
... FLP Transmit Renegotiate Link Fail Period t82 NLP Receive Link Pulse Maximum Period Required For Detection After FLP Negotiation Has Completed TPO TPI t 63 PLEDn SMSC DS – LAN83C183 Table 5.12 Link Pulse Timing (Cont.) Limit Min Typ Max 150 3 ...
Page 102
... CLK TPO CLK TPI TPI PLEDn SMSC DS – LAN83C183 Figure 5.16 FLP Link Pulse Timing a. Transmit FLP and Transmit FLP Burst DATA CLK DATA CLK Receive FLP DATA 31.25 62.50 93. Receive FLP Burst ...
Page 103
... Jabber Deactivation Delay Time MII 100 Mbits/s Not applicable FBI 100 Mbits/s Not applicable MI 10 Mbits/s TXEN TPO COL CRS SMSC DS – LAN83C183 shows the Jabber AC timing parameters. See Table 5.13 Jabber Timing Limit Min 50 250 Figure 5.17 Jabber Timing ...
Page 104
... LED DRIVER TIMING CHARACTERISTICS Table 5.14 timing diagram. Sym Parameter t96 PLED[5:0]n On Time t97 PLED[5:0]n Off Time PLED[5:0]n SMSC DS – LAN83C183 shows the Jabber AC timing parameters. See Table 5.14 LED Driver Timing Limit Min Typ Max 80 105 80 105 Figure 5.18 LED Driver Timing t 96 104 Figure 5 ...
Page 105
... MDC To MDIO Interrupt Pulse Deassert Delay MDC 0 t 103 MDIO ST1 (READ) t 103 MDIO ST1 (WRITE) MDINTn SMSC DS – LAN83C183 shows the MI Serial Port AC timing parameters. See for the associated timing diagram. Table 5.15 MI Serial Port Timing Limit Min Typ Max ...
Page 106
... Figure 5.20 MDIO Interrupt Pulse Timing Internal Interrupt Signal MDC MDIO SMSC DS – LAN83C183 t t 110 111 106 Rev. 12/14/2000 ...
Page 107
... PINOUTS AND PACKAGE DRAWINGS This section contains the alphabetical and numerical pin listings for the LAN83C183 as well as its pinouts and package drawing. 5.5.1 Pinouts Table 5.16 the signals by category and the second lists them by pin number. Table 5.16 LAN83C183 Pin List (by Signal Category) Pin Name ...
Page 108
... Table 5.16 LAN83C183 Pin List (by Signal Category) (Cont.) Pin Name Pin Number PLED1n/MDA1n 62 PLED2n/MDA2n 3 PLED3n/MDA3n 4 PLED4n 2 PLED5n 63 Miscellaneous ANEG 30 COL 12 DPLX 29 RESETn 44 RPTR 24 SPEED 28 SMSC DS – LAN83C183 Description Programmable LED Output /Management Interface Address Input Programmable LED Output /Management Interface Address Input ...
Page 109
... Table 5.16 LAN83C183 Pin List (by Signal Category) (Cont.) Pin Name Pin Number Power Ground GND1 52 GND2 60 GND3 6 GND4 41 GND5 23 GND6 31 No Connection ...
Page 110
... Table 5.17 LAN83C183 Pin List (by Pin Number) Pin Number Pin Name PLED4n 3 PLED2n/MDA2n 4 PLED3n/MDA3n GND3 7 VDD3 8 VDD4 9 MDINTn/MDA4n 10 MDC 11 MDIO 12 COL 13 CRS 14 RX_DV RX_ER/RXD4 19 RXD3 20 RXD2 21 RXD1 22 RXD0 23 GND5 24 RPTR 25 VDD5 26 RX_CLK 27 RX_EN/JAMn 28 SPEED 29 DPLX 30 ANEG 31 GND6 ...
Page 111
... Table 5.17 LAN83C183 Pin List (by Pin Number) (Cont.) Pin Number Pin Name 36 TXD1 37 TXD2 38 TXD3 39 TX_ER/TXD4 40 TX_EN 41 GND4 42 OSCIN RESETn REXT 51 SD_THR 52 GND1 53 SD/FXDISn 54 TPO+/FXI- 55 TPO-/FXI+ 56 VDD1 57 VDD2 58 TPI+/FXO- 59 TPI -/FXO+ 60 GND2 61 PLED0n/MDA0n ...
Page 112
... Figure 5.21 LAN83C183 64-Pin LQFP, Top View NC PLED4n PLED2n/MDA2n PLED3n/MDA3n NC GND3 VDD3 VDD4 MDINTn/MDA4n MDC MDIO COL CRS RX_DV pins are not connected. SMSC DS – LAN83C183 shows the pin layout for the LAN83C183 package LAN83C183 7 64-Pin LQFP 8 Top View ...
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... MECHANICAL DRAWING This section contains the mechanical drawing for the LAN83C183 64-pin LQFP package. Figure 5.22 64-Pin LQFP Mechanical Drawing Pin 1 b See Detail Detail B Note: 1. All Dimensions are in millimeters. 1. Dimensions do not include mold flash. Maximum allowable flash is 0.25. 1. All leads are coplanar to a tolerance of 0.08 (ccc). Bent leads to a tolerance of 0 ...