LAN83C180 Standard Microsystems, LAN83C180 Datasheet
LAN83C180
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LAN83C180 Summary of contents
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... Media Independent Interface (MII) and the magnetics connected to Category 5 twisted pair media designed for 10BASE-T and 100BASE-TX Ethernet, and is based on the IEEE 802.3 specifications. The LAN83C180 is compatible with the Auto Negotiation section of IEEE 802.3u and provides all the support needed for the IEEE 802.3x Full Duplex specification. The LAN83C180 can operate in adapter mode or repeater/switch modes. SMSC DS – ...
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... OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – LAN83C180 Page 2 Rev. 08/24/2001 ...
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... MAXIMUM GUARANTEED RATINGS*.................................................................................................................... 18 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 18 DIFFERENTIAL OUTPUT........................................................................................................................................ 18 AC ELECTRICAL CHARACTERISTICS .................................................................................................................. 19 REFCLK................................................................................................................................................................... 19 RX_CLK ................................................................................................................................................................... 19 TX_CLK ................................................................................................................................................................... 19 MDC......................................................................................................................................................................... 19 EXTERNAL COMPONENTS....................................................................................................................................... 20 Connecting an External 25MHz Reference.............................................................................................................. 20 nRESET Pull-up Resistor......................................................................................................................................... 20 RX Input Decoupling................................................................................................................................................ 20 Crystal Oscillator...................................................................................................................................................... 20 PACKAGE DETAILS .................................................................................................................................................. 21 LAN83C180 REVISIONS ............................................................................................................................................ 22 SMSC DS – LAN83C180 TABLE OF CONTENTS Page 3 Rev. 08/24/2001 ...
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... MINT MINT Fast Ethernet MAC (LAN91C100FD, LAN91C110, LAN83C171, or other MII compliant MAC) SMSC DS – LAN83C180 PIN CONFIGURATION FIGURE 1 – SYSTEM BLOCK DIAGRAM Page 4 Rev. 08/24/2001 ...
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... MISCELLANEOUS/LED Input/ Full duplex LED status indication when nRESET high. Active low. Input when nRESET is low. High OUTPUT input means the LAN83C180 advertises full duplex capability Input Speed (10/100) LED status indication when nRESET high. High for 100Mb/s mode. Input when nRESET is low ...
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... RXGND1, TXGND1, 38, 39 TXGND2, TXGND3, TXGND4, OSCGND 32 SUBVDD 42 OSCVDD SMSC DS – LAN83C180 TYPE DESCRIPTION Output Collision LED status indication (Active Low) if ICFG = 0. If ICFG = 1, output is MINT and collision indication is lost. Output Link LED status indication (Active Low). If ICFG = 0, LNKST flashes to indicate activity. ...
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... TXREF10 pin, which must be grounded through a resistor as described in “External Components”. If TX_ER is active while TX_EN is high, then the LAN83C180 will transmit the illegal codes JKJK ( 11) on the serial data out. This ensures that errors are propagated to the link partner. ...
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... MII interface, on the TXD[3:0] bus. This data is synchronized to the rising edge of TX_CLK. To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the LAN83C180 device to take in the data on the TXD[3:0] bus and replace the first octet of the MAC preamble with Start-of-Stream Delimiter (SSD) symbols to indicate the start of the Physical Layer Stream ...
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... MII. This appears on the RXD[3:0] bus which is clocked out on the rising edge of RX_CLK. When a frame starts the LAN83C180 decodes the SSD symbols and then asserts the RX_DV signal, in order to inform the MAC that valid data is available. When the LAN83C180 detects the ESD, it deasserts the RX_DV signal. ...
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... The LAN83C180 will disconnect from the MII if it receives two consecutive false CRS events with no good frame in between them false CRS event is longer then 480 +/- 4 bit time. If the LAN83C180 receives a good carrier event (480 +/- 4 bit time good idle event (idle symbols for a period of 25000 to 30000 bit time) it will resume frame transfer to the MII. SMSC DS – ...
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... A false CRS event happens if, at the beginning of a carrier event, the JK symbols are not received correctly. When the LAN83C180 is in 100M mode it will count all false CRS events in register 27 bits 7:0. This counter is self cleared upon read disconnect event occurs between the consecutive reads of register 27, bit 15 in the register will set high ...
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... SMSC DS – LAN83C180 FIGURE 2 – LAN83C180 BLOCK DIAGRAM Page 12 Rev. 08/24/2001 ...
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... Bits Bits of 1 WRITE RESISTER SET The following register set is implemented in the LAN83C180 device. Each of the registers is accessible to the MAC at the specified offset. The bit types in the bit description tables follow the following convention Self clear RO = Read only RW = Read or write ...
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... Remote Fault 12:10 Reserved 9:5 Technology 4:0 Selector Field SMSC DS – LAN83C180 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Next page able - the LAN83C180 is not able to perform next page remote fault detected 1= A remote fault been detected T4, 100Fdx, 100Hdx, 10Fdx, 10Hdx Page 14 DEFAULT TYPE ...
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... Aneg process finished. no fault detected 0 = Link partner is not next page able 1 = Link partner is next page able 0 = LAN83C180 is not able for next page new page been received 1= A new page has been received and is in reg Link partner is not aneg able ...
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... Reg 24 - LAN83C180 Specific Register BIT BIT NAME 15:14 Test Access 13 LED Control 12 MINT POL 11 Pol Dis 10 SQE Disable 9 JAB Disable 8 Loop 10 7 Force RX 6 Force TX 5 CRS_CTL Byp ALIGN 2 Byp ENC 1 Byp SCR 0 DISCEN Reg 25 - ANEG Status BIT BIT NAME 15 Reserved ...
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... Disconnect 14:18 Reserved 7:0 False CRS counter Reg 28 - Counter Test Register BIT BIT NAME 15:0 Reserved SMSC DS – LAN83C180 DESCRIPTION The disconnect mechanism status Number of False CRS events since last read. Active only in repeater 100 mode. DESCRIPTION Test mode only Page 17 DEFAULT TYPE 0 RO ...
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... Base-T Active 100 Base TX Mode Auto Negotiation Low Power DIFFERENTIAL OUTPUT Recommended operating conditions apply except where stated. CHARACTERISTIC High level Zero level Low level Current at Slew rate SMSC DS – LAN83C180 VALUE SYMBOL MIN MAX UNITS DC PARAMETERS – INPUT ...
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... Recommended operating conditions apply except where stated. CHARACTERISTIC REFCLK Frequency Duty cycle RX_CLK Frequency Duty cycle Frequency Duty cycle TX_CLK Frequency Duty cycle Frequency Duty cycle MDC Frequency Minimum high/low SMSC DS – LAN83C180 VALUE MIN MAX UNITS 25±100ppm MHz 25±100ppm MHz 2.5±100ppm MHz 40 ...
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... The method of using a split input load resistor and de-coupling the center tap reduces common mode noise. Crystal Oscillator For IEEE802.3 compliance the oscillator must run at 25MHz ±100ppm. The LAN83C180 on-chip circuitry contributes less than 40ppm variability to the oscillator frequency, therefore the crystal must be specified to 60ppm. This must include variations due to temperature and aging. External capacitors are required on the XTAL1 & ...
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... PACKAGE DETAILS Dimensions are shown: mm (in). 64-LEAD THIN QUAD PLASTIC FLATPACK - TQFP ( 1.0mm) FIGURE 4 – LAN83C180 PACKAGE OUTLINE SMSC DS – LAN83C180 Page 21 Rev. 08/24/2001 ...
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... DC Electrical Characteristics/ DC Parameters – Supply Current 19 Figure 3/Pin 23 20 Table SMSC DS – LAN83C180 LAN83C180 REVISIONS CORRECTION Default value changed from 1C51h to 1C52h Pin # 39 added, OSCGND - see italicized text Added section See Italicized Text See Italicized Text See Italicized Text See Italicized Text ...