CXA2150AQ Sony, CXA2150AQ Datasheet

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... CRT DRIVER Description The CXA2150AQ is a bipolar IC which integrates base-band Y/C signal processing, RGB signal processing, horizontal sync signal processing that supports 15.7/31.5/33.75/37.9/45kHz, and a vertical deflection circuit that supports 50/60/100/120Hz into a single chip. This IC has been developed for DTV, and realizes the configuration of a high-end TV system that supports 960i, 1080i, 720p, etc ...

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... YSYM2 B2_IN G2_IN R2_IN YSYM1 B1_IN G1_IN R1_IN BPH DPDT_OFF CLP_C YF_OFF VM_OUT VM_MOD – 2 – CXA2150AQ VSAW1 VSAW0 VCOMP_IN V_DRV– V_DRV+ VPROT GND_V GND_H GND_SIG GND_OUT Vcc_OUT V_AGC V_OSC Vcc5 Vcc9 VBIAS VREG5 IREF_HV IREF_YC ...

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... ABL_FIL 58 IK_IN 59 SABL_IN 60 PRE_RGB 61 Vcc_OUT 62 B_OUT 63 G_OUT 64 R_OUT – 3 – CXA2150AQ AFC_FIL 31 IREF_HV 30 VBIAS 29 VREG5 28 HS_IN 27 SCP 26 SCL 25 SDA CR_IN 21 CB_IN 20 Y_IN ...

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... 25µ 25µ 2k 12.5k 7.5k – 4 – CXA2150AQ Description GND for RGB_OUT output stage YS2/YM2 control input. When the input level reaches the YM level OFF. <YS2SW> ≥ 2.3V YS2 RGB2_IN selected ≤ 1.5V YS2: OFF V IL Internal RGB signal selected < ...

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... The differential waveforms of the Y signal are output with a positive polarity. The amplitude and phase of this waveform can be adjusted by the bus. ∗ Allowable load current: –1 to +1mA 500 30k – 5 – CXA2150AQ Description ≥ 1V MUTE ≤ 0.4V MUTE: OFF V IL ≥ 3V COLOR : OFF V IH ≤ ...

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... Reference current setting for Y/color difference signal processing system. Connect to GND via the 4.7kΩ resistor 150 (such as a metal film resistor) with an 50k error of less than 1%. 20k Power supply for Y/color difference, RGB systems and I – 6 – CXA2150AQ Description 2 C bus control bus block. ...

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... 2. Sand castle pulse output The approximately CLP pulse is output superimposed on the 150 approximately 0 to 2.5V HBLK and VBLK pulses. 1.2k ∗ Allowable load current: –0.5 to +2mA 1k 34k – 7 – CXA2150AQ Description ≥ ≤ 1.5V IL ≤ 0.6V OL ≥ ≤ 1.5V IL ...

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... A 10kΩ resistor with an error of less 150 4.9k than 1% (such as a metal film resistor) is connected between this pin and GND 11k 1.35V 9 1.2k 1.2k AFC lag-lead filter Connect the RC for the lag-lead filter. 100k 3V 50µ – 8 – CXA2150AQ Description ≥ 2. ≤ 0. ...

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... Input voltage range Voltage input for high voltage fluctuation compensation High voltage compensation is 2k performed for the V_DRV signal amplitude. The control characteristics can be 38k 13.4k varied by V_COMP. ∗ Input voltage range 9.7k – 9 – CXA2150AQ Description ...

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... GND for H deflection system VREG5 CC VSYNC input Input at the sync phase. Positive polarity input 2k 1.65V 50k ∗ Input DC coupled 9 CC General-purpose V parabola wave output ∗ Allowable load current: –0.2 to +2.6mA 35k 150 200µ – 10 – CXA2150AQ Description ≥ 2. ≤ 0. ...

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... Connect to GND via a 0.1µF capacitor. 110k sawtooth wave (VSAW0) output ∗ Allowable load current: –0.2 to +2.6mA 17k 150 40k 200µ sawtooth wave (VSAW1) output ∗ Allowable load current: –0.2 to +2.6mA 150 17k 40k 200µ – 11 – CXA2150AQ Description ...

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... This pin functions as the average value. The ABL_IN threshold voltage can be varied by the I 2k ∗ Input voltage range 50µ 200k Connect a capacitor to form the LPF 10k for the ABL_IN input signal. 45k 2k – 12 – CXA2150AQ Description 2 C bus ABL_TH. ...

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... SABL compensation. ∗ Allowable load current: –0.8 to +0.4mA 1.2k 100k 30k 2k Power supply for RGB system output stage. V _OUT and B signal outputs 2.6Vp-p signal is output at 100 IRE. 63 ∗ Allowable load current: –3.7 to +5mA 64 500 3.7m – 13 – CXA2150AQ Description ...

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... CXA2150AQ ...

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... CXA2150AQ ...

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... CXA2150AQ ...

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... VSAW1 100 Vcc5 IREF_YC BPH CLP_C VM_MOD VM_OUT YF_OFF DPDT_OFF PABL_FIL R1_IN G1_IN B1_IN YSYM1 R2_IN G2_IN B2_IN GND_SIG YSYM2 GND_OUT – 17 – CXA2150AQ 100µ 4.7k 0.1µ 4.7µ 0.47µ 100 VM 100 100 0.47µ 0.1µ 0.1µ 0.1µ 100 0.1µ 0.1µ 0.1µ 100 ...

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... Electrical Characteristics Measurement Input Signals 16.67ms = 562.5HS (60Hz) 3HS VS 2µ signal 6µs 29.63µs (33.75kHz) 18µs – 18 – CXA2150AQ 5Vp-p 5Vp-p 100 IRE (700mV) FLAT-FIELD ...

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... To VPROT 0.3V HP GEN. 5V 47µ 9V 2200p From H_DRV µPC358 20k 20k 20k 20k 20k 1.9V To AFC_IN 2200p 10k 74HC4538BP 10k – 19 – CXA2150AQ 4.1V 3.5V From V_DRV+ 2.9V H_DRV Delay 3µs AFC_IN Width 4.5µs ...

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... SABL off 1Fh Center 0 LTI off 29h 0dB 3 Max. 29h 0dB 0 Picture/Only 29h 0dB 0 B/W both sides improvement 1Fh Center 0 GAMMA off 1Fh Center 0 B/W both sides improvement 1Fh Center 0 OFF 1Fh Center 0 DC transmission ratio 100% 7h Center Fh 0dB Fh Max. 0 Min. – 20 – CXA2150AQ ...

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... AKB mode 0h VBLK-end 0H after Bch REF-P 0h VBLK-start 0H before VSYNC 1Fh Center 1 V_DRV output on 0 OFF 1Fh Center 1 Center 7h Center 0h Min. 1Fh Center 0 Most inside point compensated 1Fh Center 0 Most inside point compensated 1Fh Center 0 Min. 1Fh Center 0 Min. – 21 – CXA2150AQ ...

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... HBLK control enable 0h Min. 0 ZOOM_SW off 0 JMP_SW off 1Fh Center 1 60Hz mode 0h Min. 0h Min. 0h Compensation off 0h Compensation off Fh Center 7h Center Fh Amplitude off 0 Compensation off Fh Amplitude off 0 Compensation off 7h Center 0h Amplitude off 1Fh Center 0 OFF 0 OFF 1Fh Amplitude off 1Fh Center – 22 – CXA2150AQ ...

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... V_ASPECT V_SCROLL UP_VLIN V_COMP VSAW0_DCL VSAW0_AMP VSAW1_AMP MP_PARA_DC HC_PARA_DC HC_PARA_AMP HC_PARA_PHASE Bit 6 Bit 5 Bit 4 Bit 3 0 INTER HCENT HLOCK – 23 – CXA2150AQ Bit 2 Bit 1 Bit 0 DCOL WB_SW GAMMA_L BLK_BTM COL_AXIS CTI_LEV S_ABL LTI_LEV PLIMIT_LEV ABL_MODE CTI_MODE GAMMA LTI_MODE DPIC_LEV DC_TRAN LRGB2_LEV ...

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... LTI_LEV (2) LTI (Luminance Transient Improvement) control 0 = LTI off 1 = LTI weak 2 = LTI medium 3 = LTI strong LTI_MODE (2) LTI mode setting 0 = both of black and white side improved 1 = black side improved 2 = white side improved 3 = prohibited Description Sharpness f0 (SHP_F0 = 0) 3MHz 6MHz 12MHz 18MHz – 24 – CXA2150AQ ...

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... Y_OFFSET (4) DC_OFFSET canceling for Y signal 0h = –32mV 7h = 0mV Fh = +37mV DPIC_LEV (2) Dynamic picture (black expansion) control 0 = OFF IRE knee down IRE knee down IRE knee down DC_TRAN (2) Y system DC transmission ratio setting 0 = 103 100 90 80% – 25 – CXA2150AQ ...

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... Color OFF 1Fh = 0dB 3Fh = +4.8dB CTI_LEV (2) CTI (Chrominance Transient Improvement) setting 0 = CTI off 1 = CTI weak 2 = CTI medium 3 = CTI strong CTI_MODE (2) CTI mode setting 0 = both of black and white side improved 1 = black side improved 2 = white side improved 3 = prohibited – 26 – CXA2150AQ ...

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... DC voltage) –1.25V 3 = (AKB reference pulse DC voltage) –0.65V Gch output DC +10mV Gch output DC ±0mV Gch output DC –12mV Gch output DC +20mV Gch output DC ±0mV Gch output DC –24mV R: 98%, G: 100%, B: 102.5% R: 97%, G: 100%, B: 105% R: 96%, G: 100%, B: 106% – 27 – CXA2150AQ ...

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... PICTURE max.) 3Fh = +1.33dB B_DRIVE (6) Bch drive gain control 00h = –4.67dB 29h = 0dB (2.56Vp-p at PICTURE max.) 3Fh = +1.33dB SUB_BRIGHT (6) SUB_BRIGHT control 00h = –14 IRE 1Fh = ±0 IRE 3Fh = +14 IRE : weak : strong – 28 – CXA2150AQ ...

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... OFF Normal color temperature AKBOFF (1) Automatic cut-off/Manual cut-off setting 0 = Automatic cut-off (AKB ON Manual cut-off (AKB OFF) BLK_OFF (1) Blanking ON/OFF SW when AKBOFF = blanking blanking OFF (Blanking period: approximately 8 IRE) Low color temperature R: 100%, G: 90%, B: 70% – 29 – CXA2150AQ ...

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... V_ASPECT = 00h and ASP_SW = 0) Vertical picture size increases Picture position falls, V_DRV+ output DC down Center DC = 3.5V Picture position rises, V_DRV+ output DC up (Bottom/top of picture) Top of picture compressed; bottom of picture expanded (Bottom/top of picture) (Bottom/top of picture) Top of picture expanded; bottom of picture compressed – 30 – CXA2150AQ ...

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... Horizontal picture size decreases, EW_DRV signal output DC down EW_DRV signal center DC: 4V Horizontal picture size increases, EW_DRV signal output DC up Compensation amount min. When V_ASPECT = 00h Compensation amount max. (Compensation amount max.) (Compensation amount min.) (Compensation amount max.) (Compensation amount min.) – 31 – CXA2150AQ ...

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... Horizontal size for top of picture increases Horizontal size for bottom of picture decreases and VFREQ is 60Hz Horizontal size for top of picture decreases Horizontal size for bottom of picture increases Picture position compensated to right (Video delayed with respect to HD.) (Video advanced with respect to HD.) – 32 – CXA2150AQ ...

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... HBLK is made by processing the pulse generated from HP_IN and the pulse set by LEFT_BLK and RIGHT_BLK with OR logic. CLP_PHASE (2) Internal clamp pulse phase control (See Fig page 58, 100%: H period + +2% No compensation Picture position compensated to left HBLK width min. Center – 33 – CXA2150AQ ...

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... Vertical linearity control for bottom of picture 0h = 100 73% 16:9 CRT Full 4:3 CRT Full V_DRV signal amplitude is 10% up when V_ASPECT = 0, and BLK for top and bottom for picture are 22 lines added. (Bottom/top of picture) (Bottom/top of picture) Top of picture compressed (Bottom/top of picture) (Bottom/top of picture) Bottom of picture compressed – 34 – CXA2150AQ ...

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... No VSAW1 signal SAW component Right rising SAW component amplitude MP_PARA signal output DC down MP_PARA signal center DC 2.5V MP_PARA signal output parabola wave component Downward convex parabola wave amplitude HC_PARA signal output DC down HC_PARA signal center DC 3.5V HC_PARA signal output DC up – 35 – CXA2150AQ ...

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... Signal input status to VPROT pin (See Fig page 59 Normal status 1 = Abnormal signal input to VPROT pin Right rising SAW component amplitude No HC_PARA signal SAW component Right falling SAW component amplitude No parabola wave component Retrace start after input VSYNC Retrace start before input VSYNC – 36 – CXA2150AQ ...

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... Description of Operation 1. Power-on Sequence The CXA2150AQ does not have an internal power-on sequence. Therefore, the entire power-on sequence is controlled by the set microcomputer (I 1) Power-on reset The IC is reset during power-on and the RGB output are all blanked. Horizontal deflection output H_DRV starts to oscillate, but is free-running so that oscillation is not synchronized even if an unstable signal is input to HS_IN during power-on ...

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... Bus register data transfer The register setting sequence differs according to the TV-set sequence. Register settings for the following sequence are shown as an example. Set sequence CXA2150AQ register settings Power-on Reset status in 1) above. ↓ Degauss Reset status in 1) above. The CRT is degaussed in the completely darkened condition. ...

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... OFF VM_F0 = 0 Min. VM_LMT = 3 Max, limit VM_DLY = 0 VM_OUT delay Max. AKB_TIM = 0h Bch REF-P 10H BLK_OFF = 0 Blanking ON AKBOFF = 0 AKB mode UP_BLK = 0h VBLK-end 0H after Bch REF-P LO_BLK = 0h VBLK-start 0H before VSYNC V_SIZE = 1Fh Center (Adjust) V_ON = 1 V_DRV output ON EW_DC = 0 OFF – 39 – CXA2150AQ ...

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... Compensation OFF H_COMP = 0h Compensation OFF VSAW0_DCL = Fh Center VSAW1_DC = 7h Center VSAW0_AMP = Fh Amplitude OFF PIN_COMP = 0 Compensation OFF VSAW1_AMP = Fh Amplitude OFF AFC_COMP = 0 Compensation OFF MP_PARA_DC = 7h Center MP_PARA_AMP = 0h Amplitude OFF HC_PARA_DC = 1Fh Center ASP_SW = 0 OFF VDRV_SW = 0 OFF HC_PARA_AMP = 0 Amplitude OFF HC_PARA_PHASE = 0 Center – 40 – CXA2150AQ ...

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... Various Mode Settings 2 The CXA2150AQ contains I C bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once picture distortion adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data. • ...

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... In this mode, 4:3 images are reproduced without modification. A black border appears at the left and right of the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2150AQ performs compression with a register "EW_DC" that compresses the H size. Because excessive current flows to the horizontal deflection coil in this case, adequate consideration must be given to allowable power dissipation, etc ...

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... AKBTIM and UP/LO_BLK in the same way as 5) above. Adjust the following five registers with respect to the 4:3 CRT standard values for the register settings. V_ASPECT = Adjustment value AKBTIM = Adjustment value VBLK_SW = 1 UP_BLK = Adjustment value LO_BLK = Adjustment value – 43 – CXA2150AQ ...

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... H_DRV is high level, but doesn't have any other special sequences. Therefore it is recommended that a microcomputer be used in the TV set side for sequence control in the case of dynamic switching. H_DRV f0 Storage PS15K Normal PS31K Normal PS31K Long PS33K Normal PS45K Normal ∗ ∗ PS33K Long PS37K Normal PS45K Long ∗: Prohibited settings – 44 – CXA2150AQ ...

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... PS33K PS37K PS45K Long PS31K PS33K PS45K Fig. 2. Reference Example of Supported Storage Times for Each Mode (H-pulse Width: 4.5µs) H-pulse Storage time H-deflection circuit HD signal HOUT – 45 – CXA2150AQ To H-deflection block Storage time [µ ...

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... Table 2. Settings for Vertical Deflection Frequency (Regular Number of Lines) for Each Horizontal Mode VSYNC signal input in the range from –50% to +12.5% of the regular number of lines is accepted. Therefore, when VSYNC is not input, the CXA2150AQ is free-running as the regular number of lines +12.5%. However, when input VSYNC frequency changes, the vertical picture size also changes because V_DRV output amplitude is Auto-Gain-Controlled depending on the regular number of lines ...

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... Fig. 7: Effective video ratio conversion mode (ASP_SW = 1) Fig. 8: (VDRV_SW = 1) Fig. 9: (RST_SW = 1) Fig. 10: When a faster VSYNC than the regular cycle is input such as when switching channels Fig. 11: When VSYNC input stops or when VSYNC is input suddenly Fig. 12: When VSYNC input stops or when VSYNC is input suddenly (RST_SW = 1) – 47 – CXA2150AQ ...

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... When "HBLK_SW" the HBLK is the period that H-pulse is high level. HSYNC center Ref.0% (100%: 1H) Recommended HSYNC width : 1µs or more H_POSITION: Phpos [%] H pulse center CLP_PHASE CLP_SHIFT ∗ Clamp pulse width: Fixed Pclp [%] ∗ 1 RIGHT_BLK LEFT_BLK : Prblk [%] : Plblk [%] ∗ 2 HBLK period Fig. 13 – 58 – CXA2150AQ ...

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... DC voltage Normal input to VPROT input pin DC voltage 1.05V 0.75V Abnormal input to VPROT input pin example 2 (The bottom edge of the input signal does not fall to 0.75V or less.) Fig. 14. Signal Input Status to VPROT – 59 – CXA2150AQ ...

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... Color dependent "SHP_CD" sharpness LTI "LTI_LEV" CTI "CTI_LEV" VM output "VM_LEV" Table 3. Center Frequency f0 Reference Values by Function Center frequency f0 [MHz] by mode ("SYSTEM") "SHP_F0" "VM_F0" NORMAL (0) 0 3.0 1 4.0 0 4.0 1 5.4 0 1.7 1 2.3 0 2.0 1 2.7 0 0 4.0 – 60 – CXA2150AQ FF (1) HD (2) DTV (3) 6.0 11.9 17.9 8.1 16.1 24.2 7.9 23.8 35.7 10.8 32.3 48.4 3.4 4.8 7.1 4.6 6.5 9.7 4.0 6.0 8.9 5.4 8.1 12.1 1.7 3.4 5.1 2.3 4.6 6.9 4.0 6.0 8.9 5.4 8.1 12.1 4.8 7.9 11.9 6.5 10.8 16.1 6.0 11.9 17.9 8.1 16.1 24.2 ...

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... The plus side from 50% is improved, and the slew rate is half from the original waveform. See Fig. 15 for a description of the principle. 100% 50% [Input] 0% [Output] Normal mode Black side improvement mode White side improvement mode Fig. 15. Description of LTI/CTI Mode Principle 100% 100% 50% 50 – 61 – CXA2150AQ ...

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... AFC compensation using the RGB signal. DRIVE and B outputs fc: 2.4MHz LPF BLK H, VBLK Black level: 1.5V ± 225mV (BRIGHT: Min/Max) Fig. 16. Overview of PRE_RGB Output – 62 – CXA2150AQ 60 PRE_RGB output AMP At RGB 100 IRE input: 1.35Vp-p Blanking period: replaced with black level ...

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... AKBOFF Mode The CXA2150AQ also supports sets that do not use the AKB system. (AKBOFF mode) AKBOFF mode is established by setting the register "AKBOFF" • The R, G and B output DC levels are adjusted by "R, G, B_CUTOFF", respectively. • The AKB reference pulse (REF-P) is not added to the R, G and B outputs. ...

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... Signal Processing The CXA2150AQ consists of Y, color difference (Cb/Cr), RGB, horizontal deflection, and vertical deflection signal processing. All these types of signal processing are controlled signal processing A 0.7Vp-p (100 IRE) Y signal is input to Pin 20 (Y_IN) via a capacitor. This Y signal is input-clamped and passed through sharpness control, luminance transient improvement (LTI), DC transmission rate correction, and the auto pedestal circuits ...

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... Apply a control signal to this pin. See the pin description. The signal output from the YSYM1 circuit enters the white balance SW, where the R-G-B balance can be changed by "WB_SW". The picture control has a variable range of about 13dB. The sub-contrast control has a variable range of about –0.9 to +1.2 dB. The bright/sub-bright control has a variable range of ±14 IRE. – 65 – CXA2150AQ ...

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... CRT and this IC. This loop can also compensate for the CRT's change over its lifetime. This system adjusts color density using "R, G, B_DRV" for adjusting gain between RGB outputs with the I and "R, G, B_CUTOFF" for adjusting the DC level while AKB is active. – 66 – CXA2150AQ 2 C bus ...

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... R, G, B_OUT's DC level also starts falling. The AKB loop then becomes stable and converges. The CXA2150AQ returns a value of "1" to the "IKR" status register when the levels of all R, G and B internal capacitors drop below the specified maximum level. When the CXA2150AQ's power is turned on, the internal capacitors' voltage starts from the GND level ...

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... This status is useful for detecting an input signal. "CLP_PHASE" and "CLP_SHIFT" can be used to control the phases of CXA2150AQ's internal clamp pulse and the clamp pulse superimposed on SCP output at Pin 27. "CLP_GATE" can be used to set whether or not to gate the clamp pulse during the input H sync's High period ...

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... This feature is useful for stretching the source when there are not enough valid video lines. The SAW signal output from the wide-mode block is input to the block that forms each V output signal. Therefore, all V system output signals are handled in wide mode. – 69 – CXA2150AQ ...

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... Furthermore, a VPROT input pin (Pin 35) is provided to forcibly turn off RGB output in the event deflection error on the TV set. If input to Pin 35 (VPROT) remains erroneous for more than three V cycles, RGB output is totally blanked. In this case, a value of "1" is written in the "VNG" status register. For the input conditions, see Fig page 59. – 70 – CXA2150AQ ...

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... Notes on Operation • Because the R, G and B signals output from the CXA2150AQ are DC direct connected, the pattern (set board) must be designed with consideration given to minimizing interface from around the power supply and GND. Do not separate the GND patterns for each pin. A solid earth is ideal. Design the power supply as low impedance as possible ...

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... Vcc_OUT 62 B_OUT 63 G_OUT 64 R_OUT – 72 – CXA2150AQ Notes on operation and processing when unused Connect to GND via a 10kΩ resistor with an error less with short pattern. Locate external parts as near as possible. Locate external parts as near as possible. Unused, connect to GND. Input with the condition of Fig page 59 ...

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... Vcc5 IREF_YC BPH CLP_C VM_MOD VM_OUT YF_OFF DPDT_OFF PABL_FIL R1_IN G1_IN B1_IN YSYM1 R2_IN G2_IN B2_IN GND_SIG YSYM2 GND_OUT – 73 – CXA2150AQ 4.7µ 0.47µ 100 input modulation level VM 100 output VM 100 input Mute VM/COLOR 100 input Mute DPIC/DC-TRAN 0.47µ 0.1µ ...

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... Time [ms] V_ASPECT 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2 Time [ms] 4.4 V_SIZE = 0 4.2 V_SIZE = 1F V_SIZE = 3F 4.0 3.8 3.6 3.4 3.2 3.0 2 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2 4.4 V_ASPECT = 0 4.2 V_ASPECT = 1F V_ASPECT = 3F 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2 – 74 – CXA2150AQ V_POSITION V_POSITION = 0 V_POSITION = 1F V_POSITION = Time [ms] V_LIN V_LIN = 0 V_LIN = 7 V_LIN = Time [ms] V_SCROLL V_SCROLL = 0 V_SCROLL = 1F V_SCROLL = Time [ms] ...

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... UP_VLIN 4.2 UP_VLIN = 0 UP_VLIN = 7 4.0 UP_VLIN = F 3.8 3.6 3.4 3.2 3.0 2 Time [ms] JMP_SW 4.2 JMP_SW = 0 4.0 JMP_SW = 1 3.8 3.6 3.4 3.2 3.0 2 Time [ms] ASP_SW 4.4 ASP_SW = 0 4.2 ASP_SW = 1 4.0 3.8 3.6 3.4 3.2 3.0 2 Time [ms] LO_VLIN 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2 Time [ms] VDRV_SW (0 to 5ms magnification) 4.5 4.4 4.3 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3 Time [ms] 20 – 75 – CXA2150AQ LO_VLIN = 0 LO_VLIN = 7 LO_VLIN = VDRV_SW = 0 VDRV_SW = ...

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... V_SAW0, 1 VSAW0_AMP 4.7 4.5 4.3 4.1 3.9 VSAW0 _AMP = 0 3.7 VSAW0_AMP = F VSAW0_AMP = 1F 3 Time [ms] VSAW0_DC 5.5 5.0 4.5 4.0 VSAW0_DCL = 0, VSAW0_DCH = 0 3.5. VSAW0_DCL = F, VSAW0_DCH = 1 VSAW0_DCL = F, VSAW0_DCH = 3 3.0 2 Time [ms] 4.7 4.5 4.3 4.1 3.9 3.7 3 5.5 5.0 4.5 4.0 3.5. 3.0 2 – 76 – CXA2150AQ VSAW1_AMP VSAW1_AMP = 0 VSAW1_AMP = F VSAW1_AMP = Time [ms] VSAW1_DC VSAW1_DC = 0 VSAW1_DC = F VSAW1_DC = Time [ms] ...

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... UP_UCG 4.2 4.0 3.8 3.6 3.4 3.2 3.0 UP_UCG = 0 UP_UCG = 3 (UC_POL = 0) 2.8 UP_UCG = 3 (UC_POL = 1) 2 Time [ms] 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2 – 77 – CXA2150AQ PIN_PHASE PIN_PHASE = 0 PIN_PHASE = 1F PIN_PHASE = Time [ms] LO_CPIN LO_CPIN = 0 LO_CPIN = 1F LO_CPIN = Time [ms] LO_UCG LO_UCG = 0 LO_UCG = 3 (UC_POL = 0) LO_UCG = 3 (UC_POL = Time [ms] ...

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... UP_UCP 4.2 4.0 3.8 3.6 3.4 UP_UCP = 0 3.2 UP_UCP = 3 3 Time [ms] PIN_AMP 4.2 4.0 3.8 3.6 3.4 PIN_AMP = 0 3.2 PIN_AMP = 1F PIN_AMP = 3F 3 Time [ms] LO_UCP 4.2 4.0 3.8 3.6 3.4 LO_UCP = 0 3.2 LO_UCP = 3 3 Time [ms] EW_DC 4.2 3.8 3.4 3.0 2.6 EW_DC = 0 EW_DC = 1 2 Time [ms] – 78 – CXA2150AQ ...

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... HC_PARA_DC 4.7 4.2 3.7 3.2 HC_PARA_DC = 0 HC_PARA_DC = 1F 2.7 HC_PARA_DC = 3F 2 Time [ms] HC_PARA_PHASE 4.0 HC_PARA_PHASE = 0 HC_PARA_PHASE = 1F HC_PARA_PHASE = 3F 3.8 3.6 3.4 3.2 3 Time [ms] 3.8 3.6 3.4 3.2 3.0 2.8 2 4.0 3.8 3.6 3.4 3.2 3.0 2 4.2 4.0 3.8 3.6 3.4 3.2 3 – 79 – CXA2150AQ MP_PARA_AMP MP_PARA_AMP = 0 MP_PARA_AMP = 7 MP_PARA_AMP = Time [ms] HC_PARA_AMP HC_PARA_AMP = 0 HC_PARA_AMP = 1F HC_PARA_AMP = Time [ms] DF_PARA Time [ms] ...

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... DATA CLP_PHASE (See Fig page 58 Front adge Back adge 0.5 1.0 LEFT_BLK (See Fig page 58 AFC_BOW 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2 – 80 – CXA2150AQ 1.5 2.0 2.5 3.0 DATA 31 62 DATA 31 62 DATA ...

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... H_COMP = 7 3.1 H_COMP = F 3 Time [ms] 100 100 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 –0. – 81 – CXA2150AQ V_COMP VCOMP_IN [V] PINCOMP HCOMP_IN [V] H_COMP HCOMP_IN [V] ...

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... AFC_COMP (HCOMP_IN = 0V) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 DATA AFC_COMP 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 HCOMP_IN [V] – 82 – CXA2150AQ AFC_COMP = 3 AFC_COMP = ...

Page 83

... DATA COLOR –5 –10 –15 –20 – CB_OFFSET –20 –40 –60 – PICTURE 0 –2 –4 –6 –8 –10 –12 – – 83 – CXA2150AQ 31 62 DATA 31 62 DATA 31 62 DATA ...

Page 84

... AKB_LOOP lock range 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 CRTDC [V] (See page 17 –1 –2 –3 –4 – CUTOFF –2 –4 –6 –8 –10 –12 100 0 CUT_OFF (AKBOFF = 1, BLK_OFF = 1) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 – 84 – CXA2150AQ DRIVE 31 62 DATA 31 62 DATA 31 62 DATA ...

Page 85

... ABL_TH (Threshold in quick discharge 0.5 – 85 – CXA2150AQ ABL_MODE = 0 ABL_MODE = 1 ABL_MODE = 2 ABL_MODE = ABL_FIL voltage [V] S_ABL S_ABL = 0 S_ABL = 1 S_ABL = 2 2.4 2.6 2.8 3.0 SABL_IN voltage [V] ABL_TH = 0 ABL_TH = 7 ABL_TH = F 1.0 1.5 2.0 ABL_IN voltage [V] ...

Page 86

... COL_AXIS = 3 (NTSC JAPAN) R-Y 1.0 R-Y 0.5 0 –1.0 –0.5 0 0.5 G-Y –0.5 –1.0 COL_AXIS = 1 (PAL/SECAM) R-Y 1.0 R-Y 0.5 0 –1.0 –0.5 0 0.5 G-Y –0.5 –1.0 Detection Axis Adjustment COL_AXIS = 2 (NTSC US) R-Y 1.0 R-Y 0.5 0 B-Y 1.0 –1.0 –0.5 0 G-Y –0.5 –1.0 COL_AXIS = 0 (NTSC Projecter) R-Y 1.0 R-Y 0.5 0 B-Y 1.0 –1.0 –0.5 0 G-Y –0.5 –1.0 – 86 – CXA2150AQ B-Y 0.5 1.0 B-Y 0.5 1.0 ...

Page 87

... SHARPNESS = 0 SHARPNESS = 1F SHARPNESS = Frequency [MHz] DTV Frequency [MHz] RGB1, 2_IN → RGB_OUT RGB1 RGB2 1 10 Frequency [MHz] CB_IN → B_OUT (SHP_F0 = 0) NORMAL FF HD DTV 1 10 Frequency [MHz] – 87 – CXA2150AQ 40 45 100 100 100 ...

Page 88

... VM_MOD 3.0 VM_LEV = 1 2.5 VM_LEV = 2 VM_LEV = 3 2.0 1.5 1.0 0 VM_MOD voltage [V] VM_F0 = Frequency [MHz] VM_F0 = Frequency [MHz] VM_F0 = Frequency [MHz – 88 – CXA2150AQ ...

Page 89

... Y_IN: Phase Difference between VM_OUT and R_OUT when T-pulse Inputs SYSTEM = 1 (FF VM_DLY SYSTEM = 3 (DTV VM_DLY t VM-R – 89 – CXA2150AQ VM_F0 = 0, SHP_F0 = 0 VM_F0 = 2, SHP_F0 = 0 VM_F0 = 0, SHP_F0 = 1 VM_F0 = 2, SHP_F0 = VM_F0 = 0, SHP_F0 = 0 VM_F0 = 2, SHP_F0 = 0 VM_F0 = 0, SHP_F0 = 1 VM_F0 = 2, SHP_F0 = ...

Page 90

... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0 0.15 0.4 – 0.1 2.75 – 0.15 M 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL QFP-64P-L01 LEAD TREATMENT LEAD MATERIAL QFP064-P-1420 PACKAGE MASS – 90 – CXA2150AQ + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.05 + 0.35 0° to10° EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g Sony Corporation ...