SAF-C509-LM Infineon Technologies AG, SAF-C509-LM Datasheet
SAF-C509-LM
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SAF-C509-LM Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C509-L Data Sheet 09.96 ...
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CMOS Microcontroller Advance Information • Full upward compatibility with SAB 80C517/80C517A and 8051/C501 microcontrollers • 256 byte on-chip RAM • 3K byte of on-chip XRAM • 256 directly addressable bits • 375 ns instruction cycle at 16-MHz oscillator frequency ...
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... CMOS port structure. The C509-L is mounted in a P-MQFP-100-2 package. Ordering Information Type Ordering Code SAB-C509-LM Q67120-C1045 SAF-C509-LM Q67120-C0983 Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C509-L) and – 40 ˚C to 125 ˚C (SAK-C509-L) are available on request. Semiconductor Group SAB-C509-L T ...
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Figure 2 Logic Symbol Semiconductor Group 3 C509-L 09.96 ...
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Figure 3 C509-L Pin Configuration (P-MQFP-100-2, Top View) Semiconductor Group 4 C509-L ...
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Table 1 Pin Definitions and Functions Symbol Pin Number P1.0 - P1.7 9-6, 1, 100- 100 Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P9.0 - P9.7 74-77, 5-2 XTAL2 12 XTAL1 Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit quasi-bidirectional I/O port with ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P2.0 – P2.7 14-21 PSEN / RDF 22 ALE PRGEN Input O = Output Semiconductor Group I/O*) Function I/O Port ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P0.0 – P0.7 26, 27, 30-35 HWPD 36 P5.0 - P5.7 44- Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit open-drain ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number OWE 45 P6.0 - P6.7 46-50, 54- Input O = Output Semiconductor Group I/O*) Function I Oscillator Watchdog Enable A high level on ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P8.0 - P8.6 57-60, 51- P4.0 – P4.7 64-66, 68- SWD Input O = Output Semiconductor Group I/O*) Function I Port 8 ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number RESET AREF V 79 AGND P7.0 - P7.7 87- Input O = Output Semiconductor Group I/O*) Function I RESET A low level on this ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P3.0 – P3.7 90- 10, 28, 62 11, 29, 63 Input O = ...
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Figure 4 Block Diagram of the C509-L Semiconductor Group 13 C509-L 09.96 ...
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CPU The C509-L is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C509-L CPU manipulates data and operands in the following five address spaces: – Kbyte of external program memory – Kbyte of external data memory – 512 byte of internal Boot ROM ...
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Table 2 Overview of Program and Data Memory Organization Operating Mode Program Memory (Chipmode) Ext. Normal Mode 0000 H - FFFF H XRAM Mode 0200 H - F3FF H Bootstrap Mode 0200 H - F3FF H Programming Mode 0200 H ...
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Normal Mode Configuration The Normal Mode is the standard 8051 compatible operating mode of the C509-L. In this mode 64K byte external code memory and 61K byte external SRAM as well as 3K byte internal data memory (XRAM) are provided. ...
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XRAM Mode Configuration The XRAM Mode is implemented in the C509-L for executing e. byte diagnostic software which has been loaded into the XRAM in the Bootstrap Mode via the serial interface. In this operating mode the ...
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Bootstrap Mode Configuration In the Bootstrap Mode the Boot ROM and the external FLASH/ROM/EPROM are mapped into the code memory area. 61K byte external SRAM as well as 3K byte internal data memory (XRAM) are provided in the external data ...
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Programming Mode Configuration The External Programming Mode is implemented for the in-circuit programming of external 5V-only FLASH EPROMs. Similar as in the XRAM mode, the Boot ROM, the XRAM, and the external data memory (SRAM) are mapped into the code ...
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The Bootstrap Loader The C509-L includes a bootstrap mode, which is activated by setting the PRGEN pin at logic high level at the rising edge of the RESET or the HWPD signal (bit PRGEN1=1). In this mode software routines of ...
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Figure 10 The Three Phases of the Bootstrap Loader The serial communication, which is activated in phase II is performed with the integrated serial interface 0 of the C509-L. Using a full- or half-duplex serial cable (RS232) the MCU must ...
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Control of XRAM Access The XRAM in the C509 memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same ...
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MOVX DPTR a)P0/P2 Bus @DPTR < b)RD/WR active XRAM c)ext.memory address is used range DPTR a)P0/P2 Bus ( Data) XRAM b)RD/WR address inactive range c)XRAM is used MOVX XPAGE a)P0 Bus @ Ri < P2 I/O XRAM ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator ...
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Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C509-L contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. Several special function registers of the C509-L (CC10-17, CT1REL, CC1EN, CAFR) are located in the mapped special ...
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Table 4 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word SP Stack Pointer SYSCON1 System ...
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Table 4 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Compare / CCEN Compare/Capture Enable Register Capture CC4EN Compare/Capture 4 Enable Register Unit (CCU) CCH1 Compare/Capture Register 1, High Byte Timer 2 CCH2 Compare/Capture Register 2, High Byte ...
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Table 4 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Compare / CAFR 5) Capture 1, Falling/Rising Edge Register Capture CRCH Comp./Rel./Capt. Reg. High Byte Unit (CCU) CRCL Comp./Rel./Capt. Reg. Low Byte Timer 2 COMSETL Compare Set Register, ...
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Table 4 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name MUL/DIV ARCON Arithmetic Control Register Unit MD0 Multiplication/Division Register 0 MD1 Multiplication/Division Register 1 MD2 Multiplication/Division Register 2 MD3 Multiplication/Division Register 3 MD4 Multiplication/Division Register 4 MD5 Multiplication/Division ...
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Table 5 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after 1) Reset DIR0 ...
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Table 5 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset A2 H COMSETH COMCLRL COMCLRH ...
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Table 5 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset C2 H CCL1 CCH1 CCL2 ...
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Table 5 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset DA H ADDATL – ADCON1 0100. ADCL1 ADCL0 ADST1 ...
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Table 5 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset EE H MD5 ARCON 0XXX. MDEF XXXX ...
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Digital I/O Ports The C509-L allows for digital I lines grouped into 8 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports ...
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Port Structure Selection After a reset operation of the C509-L, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional port structure (CMOS) the bit PMOD of SFR SYSCON must be set. Because each port pin can be ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 : Table 6 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler ...
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Compare / Capture Unit (CCU) The compare/capture unit can be used in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. The CCU consists of three 16-bit timer/counters and an ...
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The block diagram in figure 18 shows the general configuration of the CCU. All CC1 to CC4 registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare registers CM0 through CM7 can either be ...
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Timer 2 Operation Gated Timer Mode : In gated timer function, the external input pin P1.7/T2 operates as a gate to the input of timer high, the internal clock input is gated to the timer. T2 ...
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Compare Timer Operation The compare timers receive its input clock from a programmable prescaler which provides input frequencies, ranging from f OSC 16-bit timers, which on overflow are automatically reloaded by the contents of the 16-bit reload registers. The compare ...
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Compare Modes The compare function of a timer/register combination operates as follows. the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register. lf the count value in the timer register matches ...
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Figure 22 Compare Function in Compare Mode 1 Compare Mode 2 In the compare mode 2 the port 5 pins are under control of compare/capture register CC4, but under control of the compare registers COMSET and COMCLR. When a compare ...
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Multiplication / Division Unit (MDU) This on-chip arithmetic unit of the C509-L provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are unsigned integer operations. Table 8 describes the five general operations the MDU ...
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For starting an operation, registers MD0 to MD5 and ARCON must be written certain sequence according table 8 and 9. The order the registers are accessed determines the type of the operation. A shift operation is started ...
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Serial Interfaces 0 and 1 The C509-L has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit and receive simultaneously. The serial channel 0 is completely ...
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For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the ...
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Table 12 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with its dependencies of the control bits BD, SMOD, S0P, and S1P. Table 12 Serial Interface 0 - Baud Rate Dependencies Serial Interface ...
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A/D Converter The C509-L has a high perfomance 10-bit A/D converter (figure 27) with 15 inputs included which uses successive approximation technique for the conversion and uses self calibration mechanisms for reduction and compensation of offset and linearity errors ...
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The A/D converter provides the following features: – 15 multiplexed input channels, which can also be used as digital inputs (port 7, port 8) – 10-bit resolution – Single or continuous conversion mode – Internal or external start-of-conversion trigger capability ...
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A/D Conversion Timing An A/D conversion is internally started by writing into the SFR ADDATL with dummy data. A write to SFR ADDATL will start a new conversion even if a conversion is currently in progress. Basically, the A/D conversion ...
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Interrupt System The C509-L provides 19 interrupt sources with four priority levels. 12 interrupts can be generated by the on-chip peripherals and 7 interrupts may be triggered externally. In the C509-L the 19 interrupt sources are combined to six groups ...
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Figure 31 Interrupt Request Sources (Part 2) Semiconductor Group 56 C509-L ...
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Figure 32 Interrupt Request Sources (Part 3) Semiconductor Group 57 C509-L 09.96 ...
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Figure 33 Interrupt Request Sources (Part 4) Semiconductor Group 58 C509-L ...
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Table 13 Interrupt Sources and their Corresponding Interrupt Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel 0 Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 ...
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... Fail Save Mechanisms The C509-L offers two on-chip peripherals which monitor the program flow and ensure an automatic "fail-safe" reaction for cases where the controller’s hardware fails or the software hangs up: – A programmable watchdog timer (WDT) with variable time-out period from 189 microseconds up to approx. 0.79 seconds at 16 MHz. – ...
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Oscillator Watchdog The oscillator watchdog of the C509-L serves for three functions : – Monitoring of the on-chip oscillator's function. The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in ...
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Power Saving Modes The C509-L provides three power saving modes in which power consumption can be significantly reduced. – Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able ...
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... ....................................... – ......................................... – 0 must not exceed the values defined by the – for the SAF-C509 A Symbol Limit Values min. V – 0 – 0.5 IL1 V – 0.5 IL2 V – 0.5 ILC ...
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Parameter Output low voltage (ports Output low voltage (port 0, ALE, PSEN/RDF, RO) Output high voltage (ports Output high voltage (port 0 in external bus mode, ...
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Parameter Power supply current: C509-L, Active mode, 12 MHz C509-L, Active mode, 16 MHz C509-L, Idle mode, 12 MHz C509-L, Idle mode, 16 MHz C509-L, Slow down mode, 12 MHz C509-L, Slow down mode, 16 MHz C509-L, Power Down Mode ...
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... A/D Converter Characteristics for the SAB-C509 – for the SAF-C509 10%, – AREF CC Parameter Analog input voltage Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog ...
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Notes may exeed AIN AGND these cases will be X000 or X3FF H 2) During the sample time the input capacitance C internal resistance of the analog source must allow the capacitance to reach their ...
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... Interfacing the C509-L to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group – for the SAF-C509 A C for all other outputs = 80 pF) L Symbol 16-MHz clock Duty Cycle ...
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External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to ...
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External Clock Drive XTAL2 Parameter Symbol Oscillator period CLP High time TCL Low time TCL t Rise time t Fall time Oscillator duty cycle DC Clock cycle TCL Note: The 16 MHz values in the tables are given as an ...
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Figure 36 Program Memory Read Cycle Figure 37 Data Memory Read Cycle Semiconductor Group 71 C509-L 09.96 ...
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Figure 38 Data Memory Write Cycle Figure 39 External Clock Drive Drive XTAL2 Semiconductor Group 72 C509-L ...
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AC Inputs during testing are driven at Timing measurements are made at Figure 40 AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins ...