MC68HC908AP64CFB Freescale Semiconductor, Inc, MC68HC908AP64CFB Datasheet
MC68HC908AP64CFB
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MC68HC908AP64CFB Summary of contents
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MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet M68HC08 Microcontrollers MC68HC908AP64 Rev. 4 01/2007 freescale.com ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ...
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Revision History Revision Date Level 15.7.2 ADC Clock Control Register January 2007 4 be set to between 500kHz and 2MHz” to “The ADC clock should be set to between 500kHz and 1MHz” Table 22 Electrical Characteristics (5V) Table ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters 6 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 11.4.3.2 Character Reception ...
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Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 13.12.5 CGND (Clock Ground ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 22.13 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 1 General Description 1.1 Introduction The MC68HC908AP64 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a ...
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General Description • Timebase module • Serial communications interface module 1 (SCI) • Serial communications interface module 2 (SCI) with infrared (IR) encoder/decoder • Serial peripheral interface module (SPI) • System management bus (SMBus), version 1.0/1.1 (multi-master IIC bus) • ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 96 BYTES USER FLASH — (SEE TABLE) USER RAM — (SEE TABLE) MONITOR ROM — 959 BYTES USER FLASH VECTOR SPACE — 48 BYTES OSCILLATORS AND CLOCK GENERATOR ...
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General Description 1.4 Pin Assignment PTB6/T2CH0 1 2 VREG 3 PTB5/T1CH1 VDD 4 5 OSC1 6 OSC2 VSS 7 8 PTB4/T1CH0 IRQ1 9 PTB3/RxD 10 RST 11 PTB2/TxD 12 NC: No connection Figure 1-2. 48-Pin LQFP Pin Assignments 22 MC68HC908AP ...
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PTB6/T2CH0 1 VREG 2 PTB5/T1CH1 3 VDD 4 OSC1 5 OSC2 6 VSS 7 PTB4/T1CH0 8 IRQ1 9 PTB3/RxD 10 RST 11 Figure 1-3. 44-Pin QFP Pin Assignments Freescale Semiconductor MC68HC908AP Family Data Sheet, Rev. 4 Pin Assignment PTD7/KBI7 33 ...
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General Description PTD2/KBI2 PTD1/KBI1 PTD0/KBI0 PTB7/T2CH1 CGMXFC PTB6/T2CH0 VREG PTB5/T1CH1 OSC1 OSC2 PTB4/T1CH0 PTB3/RxD PTB2/TxD PTB1/SCL PTB0/SDA PTC7/SCRxD PTC6/SCTxD Pins not available on 42-pin package VDD VSS ...
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Pin Functions Description of the pin functions are provided in PIN NAME V Power supply Power supply ground Power supply for analog circuits. DDA V Power supply ground for analog circuits. SSA V ADC input ...
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General Description PIN NAME 8-bit general purpose I/O port; PTB0–PTB3 are open drain when configured as output. PTB4–PTB7 have schmitt trigger inputs. PTB0 as SDA of MMIIC. PTB0/SDA PTB1 as SCL of MMIIC. PTB1/SCL PTB2/TxD PTB2 as TxD of SCI; ...
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V and V are the power supply and ground pins for the analog circuits of the MCU. These pins DDA SSA should be decoupled as per the digital power supply pins. MCU NOTE: Component values shown ...
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General Description 28 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 2 Memory 2.1 Introduction The CPU08 can address 64k-bytes of memory space. The memory map, shown in • 62,368 bytes of user FLASH — MC68HC908AP64 32,768 bytes of user FLASH — MC68HC908AP32 16,384 bytes of user FLASH — MC68HC908AP16 ...
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Memory $0000 I/O Registers ↓ 96 Bytes $005F $0060 RAM ↓ 2,048 Bytes (MC68HC908AP64) $085F $0860 FLASH Memory ↓ 62,368 Bytes (MC68HC908AP64) $FBFF $FC00 Monitor ROM 2 ↓ 512 Bytes $FDFF $FE00 SIM Break Status Register $FE01 SIM Reset Status ...
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Addr. Register Name Read: Port A Data Register $0000 Write: (PTA) Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: $0002 Port C Data Register (PTC) Write: Reset: Read: $0003 Port D Data Register (PTD) Write: Reset: Read: ...
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Memory Addr. Register Name Read: $000D Unimplemented Write: Reset: Read: $000E Unimplemented Write: Reset: Read: $000F Unimplemented Write: Reset: Read: SPI Control Register $0010 Write: (SPCR) Reset: Read: SPI Status and Control $0011 Register Write: (SPSCR) Reset: Read: SPI Data ...
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Addr. Register Name Read: Keyboard Status and Control $001A Register Write: (KBSCR) Reset: Read: Keyboard Interrupt $001B Enable Register Write: (KBIER) Reset: Read: IRQ2 Status and Control Reg- $001C ister Write: (INTSCR2) Reset: Read: Configuration Register 2 $001D Write: † ...
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Memory Addr. Register Name Read: Timer 1 Channel 0 $0026 Register High Write: (T1CH0H) Reset: Read: Timer 1 Channel 0 $0027 Register Low Write: (T1CH0L) Reset: Read: Timer 1 Channel 1 Status and $0028 Write: Control Register (T1SC1) Reset: Read: ...
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Addr. Register Name Read: Timer 2 Channel 1 Status and $0033 Write: Control Register (T2SC1) Reset: Read: Timer 2 Channel 1 $0034 Register High Write: (T2CH1H) Reset: Read: Timer 2 Channel 1 $0035 Register Low Write: (T2CH1L) Reset: Read: $0036 ...
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Memory Addr. Register Name Read: IRSCI Control Register 1 $0040 Write: (IRSCC1) Reset: Read: IRSCI Control Register 2 $0041 Write: (IRSCC2) Reset: Read: IRSCI Control Register 3 $0042 Write: (IRSCC3) Reset: Read: IRSCI Status Register 1 $0043 Write: (IRSCS1) Reset: ...
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Addr. Register Name Read: MMIIC Data Receive $004D Register Write: (MMDRR) Reset: Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0 MMIIC CRC Data Register (MMCRDR) $004E Write: Reset: Read: MMIIC Frequency Divider $004F Register Write: (MMFDR) Reset: Read: $0050 ...
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Memory Addr. Register Name Read: ADC Data Register Low 0 $005A (ADRL0) Write: Reset: Read: ADC Data Register Low 1 $005B (ADRL1) Write: Reset: Read: $005C ADC Data Register Low 2 (ADRL2) Write: Reset: Read: ADC Data Register Low 3 ...
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Addr. Register Name Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Reset: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: FLASH Block Protect $FE09 Register Write: (FLBPR) Reset: Read: $FE0A Reserved Write: Reset: Read: ...
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Memory Priority INT Flag Lowest 40 Table 2-1. Vector Addresses Address $FFD0 Reserved — $FFD1 Reserved $FFD2 TBM Vector (High) IF21 $FFD3 TBM Vector (Low) $FFD4 SCI2 (IRSCI) Transmit Vector (High) IF20 $FFD5 SCI2 (IRSCI) Transmit Vector (Low) $FFD6 SCI2 ...
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Table 2-1. Vector Addresses (Continued) Priority INT Flag Highest 2.4 Random-Access Memory (RAM) The following table shows the RAM size and address range: Device MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 The location of the stack RAM is programmable. The 16-bit stack pointer ...
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Memory For correct operation, the stack pointer must point only to RAM locations. Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O ...
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FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operation. Address: $FE08 Bit 7 Read: 0 Write: Reset: 0 Figure 2-3. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables ...
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Memory 6. Clear the ERASE bit. (5 µs). 7. Wait for a time, t nvh 8. Clear the HVEN bit. (1 µs), the memory can be accessed in read mode again. 9. After time, t rcv Programming and erasing of ...
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Wait for time, t nvh 11. Clear the HVEN bit. (1 µs), the memory can be accessed in read mode again. 12. After time, t rcv This program sequence is repeated throughout the memory until all data ...
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Memory Algorithm for programming a row (64 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to ...
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FLASH Block Protect Register The FLASH block protect register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory. Address: $FE09 Bit 7 Read: BPR7 ...
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Memory 48 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR) 3.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register, MOR. The configuration registers enable or disable these options: • Computer operating properly module ...
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Configuration & Mask Option Registers (CONFIG & MOR) 3.2 Functional Description The configuration registers and the mask option register are used in the initialization of various options. These two types of registers are configured differently: • Configuration registers — Write-once ...
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LVIPWRD — V LVI Circuit Disable Bit DD LVIPWRD disables the LVI circuit disabled LVI circuit enabled DD LVIREGD — V LVI Circuit Disable Bit REG LVIREGD disables the V REG ...
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Configuration & Mask Option Registers (CONFIG & MOR) 3.4 Configuration Register 2 (CONFIG2) Address: $001D Bit 7 Read: STOP_ ICLKDIS Write: Reset: 0 Figure 3-3. Configuration Register 2 (CONFIG2) STOP_ICLKDIS — Internal Oscillator Stop Mode Disable STOP_ICLKDIS disables the internal ...
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SCIBDSRC — SCI Baud Rate Clock Source SCIBDSRC selects the clock source used for the standard SCI module (non-infrared SCI). The setting of this bit affects the frequency at which the SCI operates Internal data bus clock, f ...
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Configuration & Mask Option Registers (CONFIG & MOR) 54 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 4 Central Processor Unit (CPU) 4.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU ...
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Central Processor Unit (CPU) 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map 4.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the ...
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Bit 14 15 Read: Write: Reset Indeterminate 4.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset ...
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Central Processor Unit (CPU) Bit 14 15 Read: Write: Reset: 4.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are ...
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After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set ...
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Central Processor Unit (CPU) 4.6 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with ...
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Source Operation Form AND #opr AND opr AND opr AND opr,X Logical AND AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX Arithmetic Shift Left ASL opr,X (Same as LSL) ASL ,X ASL opr,SP ASR opr ASRA ...
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Central Processor Unit (CPU) Source Operation Form BIT #opr BIT opr BIT opr BIT opr,X Bit Test BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Branch if Less Than or Equal To BLE opr (Signed Operands) BLO rel Branch if ...
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Source Operation Form BSR rel Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX CLRH Clear CLR ...
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Central Processor Unit (CPU) Source Operation Form DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide EOR #opr ...
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Source Operation Form LDX #opr LDX opr LDX opr LDX opr,X Load X from M LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX Logical Shift Left LSL opr,X (Same as ASL) LSL ,X LSL opr,SP LSR ...
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Central Processor Unit (CPU) Source Operation Form PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX Rotate Right through Carry ROR ...
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Source Operation Form STX opr STX opr STX opr,X STX opr,X Store STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X Subtract SUB opr,X SUB ,X SUB opr,SP SUB opr,SP SWI Software ...
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Central Processor Unit (CPU) Source Operation Form A Accumulator C Carry/borrow bit CCR Condition code register dd Direct address of operand dd rr Direct address of operand and relative offset of branch instruction DD Direct to direct addressing mode DIR ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
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Central Processor Unit (CPU) 70 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 5 Oscillator (OSC) 5.1 Introduction The oscillator module consist of three types of oscillator circuits: • Internal oscillator • RC oscillator • 32.768kHz crystal (x-tal) oscillator The reference clock for the CGM and other MCU sub-systems is selected by ...
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Oscillator (OSC) To CGM and others MOR OSCSEL1 OSCSEL0 X-TAL OSCILLATOR OSC1 Figure 5-1. Oscillator Module Block Diagram 5.2.1 CGM Reference Clock Selection The clock generator module (CGM) reference clock (CGMXCLK) is the reference clock input to the MCU. It ...
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OSCSEL1 OSCSEL0 The internal oscillator is a free running oscillator and is available after each POR or reset turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2. 5.2.2 ...
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Oscillator (OSC) 5.3 Internal Oscillator The internal oscillator clock (ICLK), with a frequency of f external components. It can be selected as the CGMXCLK for the CGM and MCU sub-systems; and the OSCCLK clock for the TBM. The ICLK is ...
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RC Oscillator The RC oscillator circuit is designed for use with an external resistor and a capacitor. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance ...
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Oscillator (OSC) From SIM CONFIG2 STOP_XCLKEN MCU See Chapter 22 for component value requirements. The series resistor ( included in the diagram to follow strict Pierce oscillator guidelines and may not S be required for all ranges of ...
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CGM Oscillator Clock (CGMXCLK) The CGMXCLK clock is output from the x-tal oscillator, RC oscillator or the internal oscillator. This clock drives to CGM and other MCU sub-systems. 5.6.5 CGM Reference Clock (CGMRCLK) This is buffered signal of CGMXCLK, ...
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Oscillator (OSC) 78 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 6 Clock Generator Module (CGM) 6.1 Introduction This section describes the clock generator module (CGM). The CGM generates the base clock signal, CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop ...
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Clock Generator Module (CGM) OSCILLATOR (OSC) MODULE OSC2 See Chapter 5 Oscillator INTERNAL OSCILLATOR OSC1 RC OSCILLATOR OSCSEL[1:0] CRYSTAL OSCILLATOR OSCCLK[1:0] SIMOSCEN From SIM PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER R RDS[3:0] V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL[11:0] ...
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Addr. Register Name Read: PLL Control Register $0036 Write: (PTCL) Reset: Read: PLL Bandwidth Control $0037 Register Write: (PBWC) Reset: Read: PLL Multiplier Select $0038 Register High Write: (PMSH) Reset: Read: PLL Multiplier Select $0039 Register Low Write: (PMSL) Reset: ...
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Clock Generator Module (CGM) • Phase detector • Loop filter • Lock detector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The ...
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Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users. In automatic bandwidth control mode (AUTO = 1), the lock ...
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Clock Generator Module (CGM) 1. Choose the desired bus frequency, f solve for the other. The relationship between f where P is the power of two multiplier, and can Choose a practical PLL ...
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Select the VCO’s power-of-two range multiplier E, according to this table: NOTE: Do not program value Select a VCO linear range multiplier, L, where f 7. Calculate and verify the adequacy of the ...
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Clock Generator Module (CGM) CGMVCLK CGMPCLK 8.0 MHz 9.8304 MHz 9.8304 MHz 10.0 MHz 10.0 MHz 16 MHz 19.6608 MHz 19.6608 MHz 20 MHz 29.4912 MHz 29.4912 MHz 32 MHz 32 MHz 32 MHz 32 MHz 6.3.7 Special Programming Exceptions ...
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CGM External Connections In its typical configuration, the CGM requires up to four external components. Figure 6-3 shows the external components for the PLL: • Bypass capacitor, C BYP • Filter network Care should be taken with PCB routing ...
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Clock Generator Module (CGM) 6.4.3 PLL Analog Ground Pin ( ground pin used by the analog portions of the PLL. Connect the V SSA potential as the V pin. SS Route V carefully for maximum noise immunity ...
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PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: PLLIE ...
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Clock Generator Module (CGM) PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when ...
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PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): • Selects automatic or manual (software-controlled) bandwidth control mode • Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition ...
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Clock Generator Module (CGM) 6.5.3 PLL Multiplier Select Registers The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the modulo feedback divider. Address: $0038 Bit 7 Read: 0 Write: Reset: 0 Figure 6-6. PLL Multiplier Select ...
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PLL and clears the BCS bit in the PLL control register (PCTL). (See Clock Selector Circuit and 6.3.7 Special Programming $40 for a default range multiply value of 64. The VCO range select bits have built-in protection ...
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Clock Generator Module (CGM) VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack ...
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Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 6.8.1 Acquisition/Lock Time ...
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Clock Generator Module (CGM) Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause ...
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Chapter 7 System Integration Module (SIM) 7.1 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in input/output (I/O) registers. The SIM ...
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System Integration Module (SIM INTERNAL PULLUP DEVICE RESET PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. Read: SIM ...
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Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 Write: $FE05 (INT2) Reset: Read: Interrupt Status Register 3 Write: $FE06 (INT3) Reset: 7.2 SIM Bus Clock Control and Generation The bus clock generator provides system ...
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System Integration Module (SIM) 7.2.2 Clock Start-up from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase ...
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ICLK RST IAB PC 7.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for ...
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System Integration Module (SIM) At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables CGMOUT. • Internal clocks to the CPU and modules are held inactive for 4096 ...
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If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all ...
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System Integration Module (SIM) 7.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. free-running after all reset states. internal reset recovery sequences.) 7.5 Exception Control Normal, sequential program execution can be changed in three ...
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YES AS MANY INTERRUPTS AS EXIST ON CHIP 7.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM ...
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System Integration Module (SIM) INT1 INT2 Figure 7-11 The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. To maintain compatibility with the ...
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Interrupt Status Register 1 Address: $FE04 Bit 7 Read: IF6 Write: R Reset Figure 7-12. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown ...
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System Integration Module (SIM) Priority Lowest Highest 108 Table 7-3. Interrupt Sources INT Vector Interrupt Source Flag Address $FFD0 — Reserved $FFD1 $FFD2 IF21 Timebase $FFD3 $FFD4 IF20 Infrared SCI Transmit $FFD5 $FFD6 IF19 Infrared SCI Receive $FFD7 $FFD8 IF18 ...
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Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.5.4 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See state by ...
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System Integration Module (SIM) IAB WAIT ADDR IDB R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 7-16 and Figure 7-17 show the timing for WAIT recovery. IAB IDB $A6 EXITSTOPWAIT ...
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A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. ...
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System Integration Module (SIM) 7.7.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode. Address: $FE00 Bit 7 Read: R Write: Reset: ...
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SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets ...
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System Integration Module (SIM) 7.7.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU break state. Address: $FE03 Bit 7 Read: BCFE Write: ...
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Chapter 8 Monitor ROM (MON) 8.1 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry ...
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Monitor ROM (MON) MAX232 C1 µ C1– GND C2 µF 6 V– 5 C2– DB9 NOTES: 1. Monitor mode entry ...
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Entering Monitor Mode Table 8-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets ...
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Table 8-1. Monitor Mode Signal Requirements and Options Address PTA0 IRQ1 RST $FFFE/ PTA2 PTA1 $FFFF X GND ( TST V TST ...
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Enter monitor mode with pin configuration shown in rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send ...
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Monitor ROM (MON) 8.3.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT 0 BIT 1 BIT 8.3.3 Break Signal A start bit (logic ...
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Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes ...
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Monitor ROM (MON) Table 8-4. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returns contents of specified address Returned Opcode $4A SENT TO MONITOR READ READ ECHO Table 8-5. WRITE (Write Memory) ...
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Table 8-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returns contents of next two addresses Returned Opcode $1A ECHO Table 8-7. IWRITE (Indexed ...
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Monitor ROM (MON) Table 8-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returns incremented stack pointer value ( Returned high-byte:low-byte order Opcode $0C ECHO Table 8-9. RUN (Run User Program) Command Description ...
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Figure 8-7. Stack Pointer at Monitor Mode Entry 8.4 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that ...
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Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH ...
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During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. FILE_PTR ADDRESS AS POINTER Figure 8-9. Data Block Format for ROM-Resident Routines ...
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Monitor ROM (MON) The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be programmed in ...
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ERARNGE ERARNGE is used to erase a range of locations in FLASH. Routine Name Routine Description Calling Address Stack Used Data Block Format There are two sizes of erase ranges: a page or the entire array. The ERARNGE will ...
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Monitor ROM (MON) 8.5.3 LDRNGE LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Routine Name Routine Description Calling Address Stack Used Data Block Format The start location of FLASH from ...
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MON_PRGRNGE In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Routine Name Routine Description Calling Address Stack Used Data Block Format The MON_PRGRNGE routine is designed to be ...
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Monitor ROM (MON) 8.5.6 EE_WRITE EE_WRITE is used to write a set of data from the data array to FLASH. Routine Name Routine Description Calling Address Stack Used Data Block Format 1. The minimum data size is 7 bytes. The ...
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Figure 8-10. EE_WRITE FLASH Memory Usage The coding example below uses the $EE00–$EFFF page for data storage. The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded ...
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Monitor ROM (MON) 8.5.7 EE_READ EE_READ is used to load the data array in RAM with a set of data from FLASH. Routine Name Routine Description Calling Address Stack Used Data Block Format 1. The start address must be a ...
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Chapter 9 Timer Interface Module (TIM) 9.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with Input capture, output compare, and pulse-width-modulation functions. a block diagram of the ...
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Timer Interface Module (TIM) 9.4 Functional Description Figure 9-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter ...
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Addr. Register Name TIM1 Status and Control Read: Register Write: $0020 (T1SC) Reset: TIM1 Counter Register Read: High Write: $0021 (T1CNTH) Reset: TIM1 Counter Register Read: Low Write: $0022 (T1CNTL) Reset: TIM Counter Modulo Read: Register High Write: $0023 (TMODH) ...
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Timer Interface Module (TIM) Addr. Register Name TIM2 Counter Modulo Read: $002F Register Low Write: (T2MODL) Reset: TIM2 Channel 0 Status Read: and Control Register Write: $0030 (T2SC0) Reset: TIM2 Channel 0 Read: Register High $0031 Write: (T2CH0H) Reset: TIM2 ...
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An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after ...
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Timer Interface Module (TIM) $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See OVERFLOW PULSE WIDTH TCHx Figure 9-3. PWM Period ...
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Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the ...
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Timer Interface Module (TIM) Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the ...
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To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To ...
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Timer Interface Module (TIM) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register ...
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TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent ...
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Timer Interface Module (TIM) 9.9.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output ...
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Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit ...
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Timer Interface Module (TIM) Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx — Toggle On Overflow Bit When channel output ...
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Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 Read: Bit 15 Write: Reset: Figure 9-12. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 Read: Bit 7 Write: Reset: Figure 9-13. TIM Channel 0 Register ...
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Timer Interface Module (TIM) 150 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 10 Timebase Module (TBM) 10.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the selected OSCCLK clock from the oscillator module. This TBM version ...
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Timebase Module (TBM) ÷ 2 ÷ 2 ÷ 2 OSCCLK From OSC module (See Chapter 5 Oscillator (OSC).) ÷ 2 ÷ 2 ÷ 2 ÷ 2 10.4 Timebase Register Description The timebase has one register, the TBCR, which is used ...
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TBR[2:0] — Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Do not change TBR[2:0] bits while the timebase is enabled (TBON = 1). Table 10-1. Timebase Rate Selection for OSCCLK ...
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Timebase Module (TBM) 10.5 Interrupts The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR[2:0]. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, ...
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Chapter 11 Serial Communications Interface Module (SCI) 11.1 Introduction The MC68HC908AP64 has two SCI modules: • SCI1 is a standard SCI module, and • SCI2 is an infrared SCI module. This section describes SCI1, the serial communications interface (SCI) module, ...
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Serial Communications Interface Module (SCI) 11.3 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full ...
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Functional Description Figure 11-2 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they ...
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Serial Communications Interface Module (SCI) 11.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT 0 BIT 1 BIT START BIT BIT 0 BIT 1 11.4.2 Transmitter Figure 11-4 shows the structure of the ...
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Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is ...
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Serial Communications Interface Module (SCI) 11.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character ...
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If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. SCIBDSRC FROM SCP1 CONFIG2 SCP0 SL CGMXCLK A PRE- ÷ ...
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Serial Communications Interface Module (SCI) 11.4.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, ...
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Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine ...
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Serial Communications Interface Module (SCI) 11.4.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should incoming character, it sets the framing error bit, FE, in SCS1. A break ...
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The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is Fast Data Tolerance Figure 11-8 shows how much a fast received character can be misaligned without causing a noise ...
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Serial Communications Interface Module (SCI) Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: • Address mark — An address mark is ...
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Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 11.5.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are ...
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Serial Communications Interface Module (SCI) The PTB2/TxD pin is an open-drain pin when configured as an output. Therefore, when configured as a general purpose output pin (PTB2), a pullup resistor must be connected to this pin. 11.7.2 RxD (Receive Data) ...
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SCI Control Register 1 SCI control register 1: • Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function ...
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Serial Communications Interface Module (SCI) WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on ...
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SCI Control Register 2 SCI control register 2: • Enables the following CPU interrupt requests: – Enables the SCTE bit to generate transmitter CPU interrupt requests – Enables the TC bit to generate transmitter CPU interrupt requests – Enables ...
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Serial Communications Interface Module (SCI) TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble logic 1s from the transmit shift register to the TxD pin. If software clears the ...
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SCI Control Register 3 SCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing ...
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Serial Communications Interface Module (SCI) NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE SCI error CPU interrupt requests from ...
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TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 ...
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Serial Communications Interface Module (SCI) FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in ...
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SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0017 Bit 7 Read: Write: Reset: 0 Figure 11-14. SCI Status Register 2 (SCS2) BKF — ...
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Serial Communications Interface Module (SCI) 11.8.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 Read: 0 Write: Reset: 0 Figure 11-16. SCI Baud Rate Register (SCBR) ...
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Table 11-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when f selected as SCI clock source. Table 11-8. SCI Baud Rate Selection Examples Prescaler SCP1 and SCP0 Divisor (PD ...
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Serial Communications Interface Module (SCI) 180 MC68HC908AP Family Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 12 Infrared Serial Communications Interface Module (IRSCI) 12.1 Introduction The MC68HC908AP64 has two SCI modules: • SCI1 is a standard SCI module, and • SCI2 is an infrared SCI module. This section describes SCI2, the infrared serial communications interface ...
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Infrared Serial Communications Interface Module (IRSCI) 12.2 Pin Name Conventions The generic names of the IRSCI I/O pins are: • RxD (receive data) • TxD (transmit data) IRSCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The ...
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IRSCI Module Overview The IRSCI consists of a serial communications interface (SCI) and a infrared interface sub-module as shown in Figure 12-2. CGMXCLK BUS CLOCK The SCI module provides serial data transmission and reception, with a programmable baud rate ...
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Infrared Serial Communications Interface Module (IRSCI) SCI_TxD SCI_R32XCLK SCI_R16XCLK SCI_RxD Figure 12-3. Infrared Sub-Module Diagram 12.4.1 Infrared Transmit Encoder The infrared transmit encoder converts the "0" bits in the serial data stream from the SCI module to narrow "low" pulses, ...
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SCI Functional Description Figure 12-5 shows the structure of the SCI. SCI DATA REGISTER RECEIVE SCI_RxD SHIFT REGISTER SCTIE TCIE SCRIE ILIE TE SCTE RE TC RWU SCRF SBK IDLE WAKEUP CONTROL CKS SL CGMXCLK A X BUS CLOCK ...
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Infrared Serial Communications Interface Module (IRSCI) The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. ...
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CKS SL PRE- CGMXCLK A X SCALER BUS CLOCK => => SCP1 SCP0 SCR1 SCR2 SCR0 12.5.2.2 Character Transmission During an SCI transmission, the transmit shift register ...
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Infrared Serial Communications Interface Module (IRSCI) The SCI transmitter empty bit, SCTE, in IRSCS1 becomes set when the IRSCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the IRSCDR can accept new data from the ...
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SCI transmitter empty (SCTE) — The SCTE bit in IRSCS1 indicates that the IRSCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, ...
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Infrared Serial Communications Interface Module (IRSCI) CKS SCP1 SCP0 SL CGMXCLK A X SCALER BUS CLOCK => => BKF RPF WAKE ILTY PEN PTY Figure 12-8. SCI ...
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Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (IRSCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete ...
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Infrared Serial Communications Interface Module (IRSCI) RT3, RT5, and RT7 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and ...
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Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should incoming character, it sets the framing error bit, FE, in IRSCS1. The FE flag is set at the ...
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Infrared Serial Communications Interface Module (IRSCI) The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is For a 9-bit character, data sampling of the stop bit takes the receiver ...
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Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in IRSCC2 puts the receiver into a ...
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Infrared Serial Communications Interface Module (IRSCI) • Framing error (FE) — The FE bit in IRSCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in IRSCC3 enables ...
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PTC6/SCTxD (Transmit Data) The PTC6/SCTxD pin is the serial data (standard or infrared) output from the SCI transmitter. The IRSCI shares the PTC6/SCTxD pin with port C. When the IRSCI is enabled, the PTC6/SCTxD pin is an output regardless ...
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Infrared Serial Communications Interface Module (IRSCI) • IRSCI status register 1 (IRSCS1) • IRSCI status register 2 (IRSCS2) • IRSCI data register (IRSCDR) • IRSCI baud rate register (IRSCBR) • IRSCI infrared control register (IRSCIRCR) 12.9.1 IRSCI Control Register 1 ...
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M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See The ninth bit can serve as an extra stop bit receiver wakeup signal parity bit. ...
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Infrared Serial Communications Interface Module (IRSCI) 12.9.2 IRSCI Control Register 2 IRSCI control register 2: • Enables the following CPU interrupt requests: – Enables the SCTE bit to generate transmitter CPU interrupt requests – Enables the TC bit to generate ...