MPC9772 Integrated Device Technology, Inc., MPC9772 Datasheet
MPC9772
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MPC9772 Summary of contents
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... The MPC9772 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys- tem baseline timing signals ...
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... CC MPC9772 Figure 2. MPC9772 52-Lead Package Pinout (Top View) 2 Bank A CLK Stop Bank B CLK Stop Bank C CLK Stop 0 CLK Stop 1 CLK Stop ...
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... PLL positive power supply (analog power supply recommended to use an external RC CC filter for the analog power supply pin V V Positive power supply for I/O and core. All V CC supply for correct operation 3 Function . Please see applications section for details. CC_PLL pins must be connected to the positive power CC MPC9772 REV 6 FEBRUARY 7, 2007 ...
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... Outputs disabled (high-impedance state) and device is reset. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9772 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted ...
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... VCO÷10 0 VCO÷8 1 VCO÷12 0 VCO÷16 1 VCO÷20 Typ Max Unit ÷ Per output 4.0 pF Inputs Min Max Unit –0.3 3.9 V –0 –0 ±20 mA ±50 mA °C –65 125 MPC9772 REV 6 FEBRUARY 7, 2007 QFB Condition Condition ...
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... CC_PLL I Maximum Quiescent Supply Current CCQ 1. The MPC9772 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current. Table 10. AC Characteristics (V Symbol ...
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... VCO_SEL) and 10 MHz ≤ XTAL(min, max) VCO(min, max) 5. Calculation of reference duty cycle limits The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t be guaranteed are within the specified range Static phase offset depends on the reference frequency Excluding QSYNC output. See application section for part-to-part skew calculation. 9. Output duty cycle (0.5 ± ...
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... MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR MPC9772 Configurations Configuring the MPC9772 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ M ÷ OUT REF f ÷VCO_SEL PLL REF ÷M where f is the reference frequency of the selected input ...
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... QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9772 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the IDT™ ...
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... QSYNC QA QC QSYNC QC(÷2) QA(÷6) QSYNC QA(÷4) QC(÷6) QSYNC QC(÷2) QA(÷8) QSYNC QA(÷6) QC(÷8) QSYNC QA(÷12) QC(÷2) QSYNC IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode Figure 6. QSYNC Timing Diagram 10 MPC9772 REV 6 FEBRUARY 7, 2007 ...
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... CMOS fanout buffers. The external feedback option of the MPC9772 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated) ...
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... When taken to its extreme the fanout of the MPC9772 clock driver is effectively doubled due to its capability to drive multiple lines. 12 Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB FB=÷ ...
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... The waveform plots in Figure 13 results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9772 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs ...
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... JIT(∅) The deviation in t for a controlled edge with respect random sample of cycles Figure 19. I/O Jitter JIT(PER Figure 21. Period Jitter V =3 2.4 0.55 MPC9772 REV 6 FEBRUARY 7, 2007 V CC ÷ GND V CC ÷ GND -T mean mean ...
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... BSC S1 6.00 BSC 0.236 BSC U 0.09 0.16 0.004 0.006 V 12.00 BSC 0.472 BSC V1 6.00 BSC 0.236 BSC W 0.20 REF 0.008 REF Z 1.00 REF 0.039 REF θ 0˚ 7˚ 0˚ 7˚ θ1 --- --- 0˚ 0˚ θ2 12˚ REF 12˚ REF θ3 12˚ REF 12˚ REF MPC9772 REV 6 FEBRUARY 7, 2007 ...
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... MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...