HYB25DC256160CF-5 Infineon Technologies AG, HYB25DC256160CF-5 Datasheet
HYB25DC256160CF-5
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HYB25DC256160CF-5 Summary of contents
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... Edition 2005-11 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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HYB25DC256160C[E/F/T], HYB25DC256800C[E/F] Revision History: Rev. 1.30 Previous Version: Rev. 1. Adjusted from 2 Table 23 DD6 73 Removed 1.0 mA from We Listen to Your Comments Any information within this document that you ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60-9 Top View, see the balls through the package . . . . . . . . . . . . . . 17 Figure 2 Pin Configuration P-TSOPII-66 ...
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List of Figures Figure 54 Package Outline of P-TFBGA-60-12 (non-green/green ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Mbit Double-Data-Rate SDRAM DDR SDRAM 1 Overview 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data used in capturing data at the ...
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Description The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double ...
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... HYB25DC256160CF–5 ×16 HYB25DC256160CF–6 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in Pin#/Buffer# column are explained in in Figure ? and that of the TSOP package in Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type J8, 26 BA0 I J7, 27 BA1 L3, ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Data Signals ×8 organization A8, 2 DQ0 I/O B7, 5 DQ1 I/O C7, 8 DQ2 I/O D7, 11 DQ3 I/O D3, 56 DQ4 I/O C3, 59 DQ5 I/O B3, ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, PWR DDQ D2, E8 ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type E9 F7 F9, 14, 17, 19 25,43, 50, 53 Table 5 Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. ...
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Figure 1 Pin Configuration P-TFBGA-60-9 Top View, see the balls through the package Data Sheet 256 Mbit Double-Data-Rate SDRAM ...
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Figure 2 Pin Configuration P-TSOPII-66-1 Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM Pin Configuration 9 ...
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Block Diagram 16 Mbit × 4 I/O × 4 Internal Memory Banks Figure 3 Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 19 Pin Configuration Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Block Diagram 8 Mbit × 8 I/O × 4 Internal Memory Banks Figure 4 Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 20 Pin Configuration Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Block Diagram 4 Mbit × 16 I/O × 4 Internal Memory Banks Figure 5 Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 21 Pin Configuration Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Functional Description The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The 256 Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to ...
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Mode Register Definition The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The ...
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Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write ...
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Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2, 2.5 and ...
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Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended ...
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Commands Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to ...
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Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write ...
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Table 8 Truth Table 1a: Commands Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge ...
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Operations 3.5.1 Bank/Row Activation Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, ...
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Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command, as shown on The starting column and bank addresses are provided with the Read command and ...
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CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 BA0, BA1 Figure 9 Read Command Data Sheet 256 Mbit Double-Data-Rate SDRAM HIGH DIS column address BA = bank ...
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CK CK Command Read Address BA a,COL n DQS Command Read Address BA a,COL n DQS DQ DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed ...
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CK CK Command Read Address BAa, COL n DQS Command Read Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of ...
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CK CK Command Read Address BAa, COL n DQS Command Read Address BAa, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS a-n = data out from bank a, column a-b = data in to bank ...
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CK CK Read Command Address BA a, COL n DQS Read Command Address BA a, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 ...
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Writes Write bursts are initiated with a Write command, as shown in The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is ...
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CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 BA0, BA1 Figure 17 Write Command Data Sheet 256 Mbit Double-Data-Rate SDRAM HIGH DIS column address BA = bank ...
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CK CK Write Command BA a, COL b Address DQS Command Write BA a, COL b Address DQS a-b = data in for bank a, column b. 3 subsequent elements of data in ...
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Write Command Address BAa, COL b t DQS Command Write Address BA, COL b DQS a-b = data in for bank a, column b, etc. 3 subsequent elements of ...
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Write Command Address BAa, COL b DQS a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 ...
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Write Command Address BAa, COL b DQS Write Command Address BAa, COL b t DQSS DQS a-b, etc. = data in for bank a, column b, etc. b', etc. ...
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Command Write Address BAa, COL b DQS Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. 3 subsequent elements of data in ...
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Command Write Address BAa, COL b DQS Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 ...
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Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied ...
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Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied ...
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Write Command Address BA a, COL b t DQS Write Command Address BA a, COL b DQS a-b = data in for bank a, column b. 3 subsequent elements ...
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Write Command Address BA a, COL b DQS Command Write Address BA a, COL b DQS a-b = data in for bank a, column b. An interrupted burst is ...
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Write Command Address BA a, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written referenced from the first positive ...
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Write Command Address BA a, COL b DQS a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is ...
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Precharge The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( issued. Input A10 ...
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Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row ...
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Table 10 Truth Table 2: Clock Enable (CKE) Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks ...
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Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not ...
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Table 12 Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active, or ...
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Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking. 9) Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. ...
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Simplified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Write A PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh ...
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Electrical Characteristics 4.1 Operating Conditions Table 14 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply relative Voltage on supply relative to ...
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Table 16 Electrical Characteristics and DC Operating Conditions Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V Supply Voltage, I/O Supply , SS V Voltage SSQ ...
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Normal Strength Pull-down and Pull-up Characteristics The nominal pull-down - curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the V inner bounding lines of the - 2. The full variation in ...
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Table 17 Normal Strength Pull-down and Pull-up Currents Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 ...
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Weak Strength Pull-down and Pull-up Characteristics The weak pull-down - curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner V I bounding lines of the - curve ...
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Table 19 Weak Strength Driver Pull-down and Pull-up Characteristics Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating I Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.) DD Notes V 1. All voltages referenced ...
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Table 20 AC Operating Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK ...
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Table 21 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol –5 t DQS falling edge hold time from CK (write cycle) t DQS falling edge to CK setup time (write cycle) t Clock Half Period t Data-out ...
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Table 21 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol –5 t Internal write to read command delay t Exit self-refresh to non-read command t Exit self-refresh to read command 1) 0 °C ≤ T ≤ 70 ...
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I Table 22 Conditions DD Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; ...
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I Table 23 Specification DD Symbol –5 DDR400B Typ. Max DD0 100 DD1 95 110 DD2P DD2F DD2Q DD3P I 38 ...
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I 4.5 Current Measurement Conditions DD Legend Activate Read Read with Autoprecharge Precharge NOP or DESELECT I : Operating Current: One Bank Operation DD1 1. General test condition a) Only ...
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Timing Diagrams The timing diagrams in this chapter give an overview of possible and recommended command sequences. 5.1 Write Command: Data Input Timing Figure 39 shows DQS versus DQ and DM Timing during write burst. DQS ...
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Read Command: Data Output Timing Figure 40 shows DQS versus DQ Timing during read burst. DQS DQ t (Data output hold time from DQS and t are only shown once and are shown referenced to different edges ...
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Initialization and Mode Register Set Command Figure 41 shows the timing diagram for initialization and Mode Register Sets. Figure 41 Initialize and Mode Register Sets Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 77 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Power: Power Down Mode Command Figure 42 shows the timing diagram for Power Down Mode. Figure 42 Power Down Mode Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 78 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Refresh: Auto Refresh Mode Command Figure 43 shows the timing diagram for Auto Refresh Mode. Figure 43 Auto Refresh Mode Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 79 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Refresh: Self Refresh Mode Command Figure 44 shows the timing diagram for Self Refresh Mode. Figure 44 Self Refresh Mode Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 80 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Read: Without Auto Precharge Command Figure 45 shows the timing diagram for Read without Auto Precharge. Figure 45 Read without Auto Precharge (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 81 Timing Diagrams Rev. 1.30, 2005-11 ...
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Read: With Auto Precharge Command Figure 46 shows the timing diagram for Read with Auto Precharge. Figure 46 Read with Auto Precharge (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 82 Timing Diagrams Rev. 1.30, 2005-11 ...
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Read: Bank Read Access Command Figure 47 shows the timing diagram for Read Bank Read Access. Figure 47 Bank Read Access (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 83 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Write: Without Auto Precharge Command Figure 48 shows the timing diagram for Write without Auto Precharge. Figure 48 Write without Auto Precharge (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 84 Timing Diagrams Rev. 1.30, 2005-11 ...
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Write: With Auto Precharge Command Figure 49 shows the timing diagram for Write with Auto Precharge. Figure 49 Write with Auto Precharge (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 85 Timing Diagrams Rev. 1.30, 2005-11 ...
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Write: Bank Write Access Command Figure 50 shows the timing diagram for Bank Write Access. Figure 50 Bank Write Access (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 86 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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Write: DM Operation Figure 51 shows the timing diagram for DM Operation. Figure 51 Write DM Operation (Burst Length = 4) Data Sheet HYB25DC256[16/80]0C[E/F/T] 256 Mbit Double-Data-Rate SDRAM 87 Timing Diagrams Rev. 1.30, 2005-11 07202005-CG4S-QV08 ...
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System Characteristics for DDR SDRAMs The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to ensure proper system performance. These characteristics are for system simulation purposes and are not subject to production test - ...
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Output Slew Rate Characteristrics (×4, ×8 Devices only) Table 28 Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Pullup Slew Rate 1.2 – 2.5 Pulldown Slew Rate 1.2 – 2.5 Table 29 Output Slew Rate Characteristics (×16 Devices only) Slew ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package • P-TSOPII: Plastic Thin Small Outline Package Type II Table 31 TFBGA ...
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Lead 1 Figure 55 Package Outline of P-TSOPII-66-1 (non-green/green) Data Sheet 256 Mbit Double-Data-Rate SDRAM Gage Plane 0.65 Basic 0.805 REF +0.1 0.1 0.35 -0.05 Seating Plane 22.22 ±0.13 91 HYB25DC256[16/80]0C[E/F/T] Package Outlines 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 GPX09261 ...
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... Published by Infineon Technologies AG ...