AM7968-125JC Advanced Micro Devices, AM7968-125JC Datasheet
AM7968-125JC
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AM7968-125JC Summary of contents
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... TM TAXIchip Transparent Asynchronous Transmitter/Receiver Interface Am7968/Am7969-125 Am7968/Am7969-175 Technical Manual Integrated Circuits Data Sheet and 1994 ...
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... Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters. Trademarks AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc. TAXIchip and TAXI are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...
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... TABLE OF CONTENTS Am7968/Am7969 TAXIchip Integrated Circuits Am7968/Am7969 Data Sheet Am7968/Am7969 Technical Manual Chapter 1 Introduction 1.1 The Am7968 TAXI 1.2 The Am7969 TAXI Receiver Chapter 2 Using the TAXIchip Set 2.1 Data and Command 2.2 Operational Modes: Local, Cascade and Test Chapter 3 Data Encoding, Violation and Syncs 3 ...
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... AMD Chapter 7 Cascade Mode Operation 7.1 Transmit Cascaded Data with a Single TAXI Transmitter 7.2 Receivers In Cascade Mode: Connections (Am7969-125 only) 7.3 Auto-Repeat Configuration 7.4 Unbalanced Configuration (Am7968/Am7969-125 only) Chapter 8 Test Mode 8.1 Transmitter Connections 8.2 Receiver Connections 8.3 Timing Relationships in Test Mode Appendix A Optical Components Manufacturers Appendix B Error Detection Efficiency ...
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... coupled — NRZI 4B/5B, 5B/6B encoding/decoding Drive coaxial cable or twisted pair directly GENERAL DESCRIPTION The Am7968 TAXIchip Transmitter and Am7969 TAXIchip Receiver Chipset is a general-purpose inter- face for very high-speed (4–17.5 Mbyte/s, 40–175 Mbaud serially) point-to-point communications over co- axial or fiber-optic media. The TAXIchip set emulates a pseudo-parallel register. They load data into one side and output it on the other, except in this case, the “ ...
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... CC2 V (TTL) 6 CC1 7 V (TTL) CC3 RESET 8 9 DMS 10 TLS TSERIN Am7968/Am7969 (X1) (X2) (DMS) Data Mode Select (CNB) Catch Next Byte (IGM) I-Got-Mine (CLK) Clock (DSTRB) Data Strobe (CSTRB) Command Strobe 07370F-2 LCC/PLCC DI2 DI1 24 23 ...
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... RESET (TTL) CC1 V (CML) 8 CC2 9 SERIN+ 10 SERIN- 11 DMS SERIN+ ACK X1 X2 CLK 07370F GND = Ground (2) Am7968/Am7969 LCC/PLCC DO7 CNB GND2 (CML) 20 GND1 (TTL) 19 CLK Am7969 RESET CNB DMS ...
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... AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of: AM7968 AM7969 –125 D DEVICE NUMBER/DESCRIPTION Am7968 TAXIchip Transmitter Am7969 TAXIchip Receiver Valid Combinations AM7968-125 AM7969-125 DC, JC AM7968-175 AM7969-175 4 C ...
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... Products List) products are compliant with MIL-STD-883C requirements with exceptions for V order number (Valid Combination) is formed by a combination of: AM7968 -125 /L AM7969 DEVICE NUMBER/DESCRIPTION Am7968 – TAXIchip Transmitter (Local Mode only) Am7969 – TAXIchip Receiver (Local Mode only) Pkg Temps (TC) VCC LCC – 125 C 4 ...
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... DMS . DMS Data Mode Select (Input) Data Mode Select input determines the Data pattern width. When it is wired to GND, the Am7968 Transmitter will assume Data to be eight bits wide, with four bits of 6 Command. When it is wired to V Transmitter will assume Data to be nine bits wide, with three bits of Command ...
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... The byte rate matches the crystal frequency. During normal operation, the byte rate is set by the crystal frequency. Alternatively, X1 can be driven by an external TTL fre- quency source. In multiple TAXI systems this external source could be another Am7968’s CLK output. powers ECL and Am7968/Am7969 AMD 7 ...
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... High level signal is at VCC. SERIN+, SERIN– Differential Serial Data In (ECL Inputs) ), the Am7969 Re- Data is shifted serially into the Shifter. The SERIN+ and SERIN– differential ECL inputs accept ECL voltage Am7968/Am7969 ...
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... During normal operation, the byte rate is set by the crystal frequency. Alternatively, X1 can be driven by an external frequency source. In multiple TAXI systems, this external source could be a TAXI Transmitter’s CLK output or an external TTL fre- quency source. Am7968/Am7969 AMD 9 ...
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... STRB pulse arrives, Data is stored in the input latch, and the second ACK response is delayed until the next CLK cycle. The inputs to an Am7968 Transmitter can be either Data or Command and may originate from two different parts of the host system. A byte cycle may contain Data or Command, but not both ...
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... Operational Modes In normal operational mode, a single Transmitter/ Receiver pair is used to transfer bits of parallel Data over a private serial link. (On the Am7968, the TLS pin is tied to ground and TSERIN is left unconnected). On the Am7969, CNB must be connected to the CLK output. The Am7969 Receiver continuously deserial- ...
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... The Sync symbol, and all subsequent data will be processed correctly. TAXI User Test Modes TLS input can be used to force the Am7968 Transmitter into either of the two Test modes. If TLS is open or termi- nated to approximately V VCO is switched out and everything is clocked directly from the CLK input ...
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... Oscillator The Am7968 and Am7969 contain an inverting amplifier intended to form the basis of a parallel mode oscillator. The design of this oscillator considered several factors related to its application. The first consideration is the desired frequency accu- racy. This may be subdivided into several areas. An os- ...
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... Am7968/Am7969 5-Bit 6-Bit Binary Encoded Data* Symbol 00000 110110 00001 010001 00010 100100 00011 100101 00100 010010 00101 010011 00110 010110 00111 010111 01000 100010 01001 110001 01010 ...
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... Notes: 1. Command pattern Sync cannot be explicitly sent by Am7968 Transmitter with any combination of inputs and STRB, but is used to pad between user data strobe with all Os on the Command input lines will cause Data to be sent. See Table 1. 3. While these Commands are legal data and will not disrupt normal operation if used occasionally, they may cause data errors if grouped into recurrent fields ...
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... The serial link speed is derived from a master frequency source (byte rate). This source can either be the built-in Crystal Oscillator clock signal applied through the 1 X pin. This signal is buffered and sent to the CLK out- put when Am7968 Transmitter is in Local mode. Crystal Mode Frequency 8-Bit 12.50 MHz 9-Bit 11 ...
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... Sync is a valid Command code. Any pattern which does not decode to a valid Command or Data pattern is flagged as a violation. The output of the decoder during these violations is indeterminate and will result in either a CSTRB or DSTRB output when the indeterminate pattern is transferred to the output latch. Am7968/Am7969 AMD 17 ...
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... Control ACK Logic N Data Source Data Signals Note: N can bits of parallel data; total 12. 18 Am7968 Am7969 Transmission Media Figure 2. TAXIchip System Block Diagram Am7968/Am7969 M Command Destination Command Signals CSTRB Data Path VLTN Control Logic DSTRB N Data Destination Data ...
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... IGM CNB VLTN CSTRB DSTRB Data Destination Pin 11 = Don’t Connect = Local Mode Pin 11 = Don’t Connect = Local Mode Figure 3. TAXIchip System in Local Mode Am7968/Am7969 Message Transfer Control Logic Data Command Source Source 9 3 DI0 – DI8 CI0 – CI2 STRB ...
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... SERIN– SERIN+ RX1 DMS V CC Am7969 Primary RX CNB IGM CLK X2 X1 Figure 4. Cascaded Receiver Clock Connections (Commercial –125 only) 20 SERIN– SERIN+ RX2 DMS Am7969 CNB IGM X2 X1 Crystal OSC Am7968/Am7969 SERIN– SERIN+ RX3 DMS Am7969 CNB IGM N 07370F-13 ...
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... Commercial (C) Devices Temperature (T – +150 C Supply Voltage (V – +125 C Operating ranges define those limits between which the func- tionality of the device is guaranteed. –0 +7.0 V –0 Max CC –0 +5.5 V 100 mA – +5.0 mA Am7968/Am7969-125 AMD ) . . . . . . . . . . . . . . . . . + +4 +5 ...
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... AMD DC CHARACTERISTICS over operating range unless otherwise specified Am7968-125 TAXIchip Transmitter Parameter Symbol Parameter Description Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK V Output HIGH Voltage OH1 ACK V Output HIGH Voltage OH2 CLK V Output LOW Voltage OL ACK, CLK ...
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... V –1. Max – Max Pin V (TTL) CC1 CC2 CC1 DMS = 0 V Pin V (CML) CC2 Am7968/Am7969-125 AMD Min Max Unit 2.4 V 0.45 V 2.0 V 0.8 V –1.5 V –400 –15 – –1.165 – ...
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... AMD SWITCHING CHARACTERISTICS (Note 20) Am7968-125 TAXIchip Transmitter (Notes 10, 13, 22) Parameter No. Symbol Parameter Description Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK 1 t CLK Period CLK Pulse Width HIGH CLK Pulse Width LOW STRB Pulse Width HIGH (Note 7) ...
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... TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load Am7968/Am7969-125 AMD Min Max Unit 8n 25n ...
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... AMD 26 (Page intentionally left blank) Am7968/Am7969-175 ...
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... Commercial (C) Devices Temperature (T – Supply Voltage (V – +125 C Operating ranges define those limits between which the func- tionality of the device is guaranteed. –0 +7.0 V –0 Max CC –0 +5.5 V +100 mA – +5.0 mA Am7968/Am7969-175 AMD ) . . . . . . . . . . . . . . + +4 +5 ...
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... AMD DC CHARACTERISTICS over operating range unless otherwise specified Am7968-175 TAXIchip Transmitter Parameter Symbol Parameter Description Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK V Output HIGH Voltage OH1 ACK V Output HIGH Voltage OH2 CLK V Output LOW Voltage OL ACK, CLK ...
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... Max – Max Pin V (TTL) CC1 CC2 CC1 DMS = 0 V Pin V (CML) CC2 Am7968/Am7969-175 AMD Min Max Unit 2.4 V 0.45 V 2.0 V 0.8 V –1.5 V –400 –15 – –1.165 –0.88 ...
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... AMD SWITCHING CHARACTERISTICS (Note 20) Am7968-175 TAXIchip Transmitter (Notes 10, 13, 22) Parameter No. Symbol Parameter Description Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK 1 t CLK Period CLK Pulse Width HIGH CLK Pulse Width LOW STRB Pulse Width HIGH (Note 7) ...
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... X1 Pulse Width LOW PW Test Conditions TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load Am7968/Am7969-175 AMD Min Max Unit 5 –2 ...
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... AMD 32 (Page intentionally left blank) Am7968/Am7969-125 Military ...
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... Am7968/Am7969-125 MILITARY ABSOLUTE MAXIMUM RATINGS StorageTemperature . . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . Supply Voltage to Ground Potential Continuous . . . . . . . . . . . . DC Voltage Applied to Outputs . . . . . . . . . . . . . . . . . . . . . DC Input Voltage . . . . . . . . . . . . . . . DC Output Current . . . . . . . . . . . . . . . . . . . DC Input Current . . . . . . . . . . . . . Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- mum ratings for extended periods may affect device reliability ...
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... AMD DC CHARACTERISTICS over operating range unless otherwise specified (for CPL Prod- ucts Group A, Subgroups are tested unless otherwise noted) Am7968-125 Military TAXIchip Transmitter Parameter Symbol Parameter Description Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK V Output HIGH Voltage ...
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... Max – Max Pin V (TTL) CC1 CC2 CC1 DMS = 0 V Pin V (CML) CC2 Am7968/Am7969-125 Military AMD Min Max Unit 2.4 V 0.45 V 2.0 V 0.8 V –1.5 V –400 –15 – –1.165 – ...
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... AMD SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Note 20) (for CPL Products Group A, Subgroups 9, 10, and 11 are tested unless other- wise noted) Am7968-125 Military TAXIchip Transmitter (Notes 10, 13, 22) Parameter No. Symbol Parameter Description Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK ...
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... CLK (pin 19) must be connected to CNB (pin 24). Test Conditions TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load TTL Output Load Am7968/Am7969-125 Military AMD Min Max Unit ...
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... SERIN– “n” 8 Bit < OPEN THTMAX Test Mode 8 Bit > 2 10; Local Mode 9 Bit < OPEN THTMAX Test Mode 9 Bit > 2 11; Local Mode 10 Bit < OPEN THTMAX Test Mode 10 Bit > 2 12; Local Mode Am7968/Am7969 ...
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... The limit for this parameter cannot be derived from t 37 and 24. This specification does not apply during reacquisition when CLK stretch can occur. This parameter is guaranteed but is not included in production tests. * Notes listed correspond to the respective references made in the DC Characteristics and the Switching Characteristics tables. Am7968/Am7969 AMD and V for OH OL VCC VCC = 0 ...
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... R1 V 07370F-14 Notes < includes scope probe, wiring and stray capacitances without device in test fixture. 2. AMD uses Automatic test equipment load configurations and forcing functions. This figure is for reference only. Am7968/Am7969 OUT – 07370F-15 ECL Output Load ...
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... ECL Input Waveform WAVEFORM INPUTS Must Be Steady May Change from May Change from Don’t Care Any Change Permitted Does Not Apply Am7968/Am7969 AMD 2 0.2 ns 07370F-16 2 0.2 ns 07370F-17 OUTPUTS Will Be Steady Will Be Changing from Will Be Changing from ...
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... AMD SWITCHING WAVEFORMS 42 Am7968/Am7969 ...
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... SWITCHING WAVEFORMS Am7968/Am7969 AMD 43 ...
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... AMD SWITCHING WAVEFORMS 44 Am7968/Am7969 ...
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... SWITCHING WAVEFORMS Am7968/Am7969 AMD 45 ...
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... AMD SWITCHING WAVEFORMS 46 Am7968/Am7969 ...
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... SWITCHING WAVEFORMS #1 TAXI Am7968/Am7969 AMD #2 TAXI 47 ...
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... MIN TOP VIEW .015 .060 SIDE VIEW .050 REF .042 .056 .026 .032 .009 .015 .450 .456 .485 .495 TOP VIEW Am7968/Am7969 .590 .615 .008 .012 .150 MIN 0° 15° 06837D .700 BZ13 CD 028 MAX 1/8/ END VIEW .020 MIN .025 R ...
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... BOTTOM VIEW .300 BSC .150 BSC .022 .028 .300 BSC .150 BSC .015 MIN TOP VIEW .442 .458 .430 MAX INDEX CORNER .020 X 45 REF. (OPTIONAL) Am7968/Am7969 AMD SIDE VIEW .054 .065 .064 .075 PLANE 2 PLANE 1 07703D CS47 CLT 028 04/28/ ...
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... Each nibble is encoded into a 5-bit symbol. The 10-bit encoded byte is format- ted into an NRZI data stream for output to the media. This 4B/5B encoding is 80% efficient, using a 125 Mbaud transmission rate to send 100 Mbps of data. The Am7968 Transmitter has differential pseudo-ECL (referenced outputs which can drive 50 shielded twisted pair or coaxial cables. ...
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... Figure 1-1 Am7968 TAXI Transmitter Block Diagram Strobe (STRB) Acknowledge (ACK X1 X2 Clock (CLK) Data Mode Select (DMS) Test Serial In (TSERIN) Note: N can bits. Total 12. Figure 1-2 Am7969 TAXI Receiver Block Diagram (SERIN+) Serial In + Media Interface (SERIN–) Serial In – ...
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... TAXI Transmitter will fill the gaps with Syncs, which do not disturb Receiver output data. 2.1 Data and Command The Am7968 TAXI Transmitter and the Am7969 TAXI Receiver interface directly bit data bus. Each TAXlchip has 12 parallel interface lines which are designated as either Command or Data bits ...
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... A TAXIchip set point-to-point link can be operated in one of three modes: Local, Cascade, or Test. Local mode consists of a single Transmitter communicating with a single Receiver over the serial medium. Cascade mode for Am7968/7969-125 consists of a single Transmitter driving two or more daisy chained (cascaded) Receivers over a single serial medium ...
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AMD The TAXIchip set uses 4B/5B or 5B/6B coding, so that m is either and n is either 8-bit mode, each 4-bit nibble is presented to one of two 4B/5B encoders to produce ...
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Table 3-1 TAXlchip Encoder Patterns 4B/5B ENCODER SCHEME HEX Data Notes: HEX data is parallel input data which is represented by the 4- ...
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... Notes: 1. Command pattern Sync cannot be explicitly sent by Am7968 Transmitter with any combination of inputs and STRB, but is used to pad between user data strobe with all Os on the Command input lines will cause Data to be sent. See Table 3-1. 3. While these Commands are legal data and will not disrupt normal operation if used occasionally, they may cause data errors if grouped into recurrent fields ...
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Violation Logic The TAXI Receiver logic has been designed to detect the most common types of transmission errors. It detects these errors by completely decoding the incoming data patterns, and recognizes the following types of VIOLATIONS: 1. Illegal, reserved ...
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AMD This optimization is at the expense of lock-up time. In TAXI systems, lock-up time is relatively unimportant, since the system must achieve lock only during system power-up. If the PLL achieves proper lock within a few tens, or even ...
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... CLOCK GENERATION AND DISTRIBUTION The serial baud rate for the Am7968 Transmitter is derived from a byte rate frequency source. The TAXI Receiver must run at the same frequency as the TAXI Transmitter. The relationship between serial baud rate and data byte rate depends on the width of the transmitted data ...
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... In addition to the bit synchronization accomplished by the PLL, the logic will maintain byte synchronization (framing) with the incoming data 60 TAXIchip Integrated Circuits Technical Manual Typical Crystal Specification 4.0 MHz –17.5 MHz +0.1% Parallel 1.00 ppm (max) Low Profile 10 ppm RESET Am7968 or, Am7969 12330E-5 ...
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... TAXI Receivers. 5.0 INTERFACING WITH THE SERIAL MEDIA The Am7968/Am7969 TAXlchip set is capable of providing a high speed point-to-point serial link over fiber-optic, coaxial, or twisted pair media. The choice of the appropriate medium depends primarily on line length and data rate. This chapter discusses the issues involved in media choice and the requirements for driving different types of media ...
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AMD common mode range. The average DC value of the input signal is therefore relatively unimportant. There are three broad classes of TAXl-to-media interface: 1. Very short (<3 link length), usually DC coupled. 2. Terminated, DC coupled. 3. Terminated, AC ...
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TAXIchip set in order for the DC connection to work. If the supply voltage or the logic levels are incompatible connection must be used. 5.2 Terminated, DC Coupled ...
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AMD threshold level of the receiver’s differential amplifier. Once the Receiver recognizes the state change, variations in the falling edge are not significant. To avoid edge rate variations due to driver turn-off, we must equate the voltage to which the ...
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Figure 5-5. In Figure 5-5a, the average DC fluctuates between 40% and 60% of the maximum level (+10% of midpoint). After the signal is capacitively coupled (Figure 5-5b), the average DC component ...
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... Driver LED or Electronics Laser Diode TAXI /Optical Interface Fiber Optic Receiver Optical Detector: Receiver PIN or Electronics Avalanche Photodiode = + Data Command Am7968 Transmitter Transceiver Am7969 Receiver Data Command 12330E-13 = GND) and if the two components ...
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For DC-coupled interconnections in which the distance between the TAXIchip set and the optical module is less than 3 , transmission line terminations are not necessary. All that is required is the appropriate ECL pull-down as shown in Figure 5-7 ...
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AMD 5.5.2 AC-Coupled TAXl-Fiber Optic Transceiver Interface Some applications will require the TAXIchip set to optical transceiver interconnection to be AC-coupled. AC coupling should be used in the following situations: a) when the TAXIchip set and optical components are driven ...
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Because of the resultant lower system costs, coaxial cable is the recommended serial medium for short-to-moderate length links. At longer lengths, the advantages of fiber optic transmission (low attenuation, immunity to EMI and ground loops, etc.) make it the media ...
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AMD Sample Values Using RG-58A/U, 50 following component values: 5.7 Interfacing to Twisted-Pair Cable Another low cost alternative twisted pair cable. Twisted pair cable is generally more lossy than coaxial cable making it suitable only for short distances. To reduce ...
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Sample Values Using IBM Type 1 STP 150 shielded twisted pair cable, a successful TAXI link was established using the following component values 101 R2 = 291 R3 = 300 C = 0.1 F 6.0 BOARD LAYOUT CONSIDERATIONS ...
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... AMD Figure 6-1 Transmitter and Receiver Decoupling Layouts Transmitter Am7968 V CC1 (TTL) V CC2 (ECL) GND1 V CC3 (CML) GND2 (CML 0.1 F (ceramic Tantalum C3 = 0.01 F (ceramic) To further decouple the TAXIchip set highly recommended that ferrite beads be inserted at locations A, B and D. Figure 6-3 Jogs and Glitches in the Clock Line CLK ...
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When terminating serial lines to or from the TAXls ensure that the Vcc rail or ground tap is not at a noisy location. Resistors can couple noise from a power supply rail into the Serial lines. Vcc to Ground ...
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AMD Figure 6-5 Fiber Optic Data Link Decoupling FODL V CC Plane Power Supply Ground Note: This connection includes a ferrite bead in the V 7.0 CASCADE MODE OPERATION The TAXIchip set can be cascaded to send multiple byte words ...
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Figure 7-1 Cascaded TAXI System Mixed Data Sources 8 4 DI0–DI7 CI0–CI7 (Note 2) SEROUT+ TAXI RX #1 SEROUT– TAXI TX #1 TLS DMS 12.5 MHz VCC SERIN+ SERIN– DMS CNB TAXI RX #1 (Note ...
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AMD 7.1 Transmit Cascaded Data with a Single TAXI Transmitter For systems that require data transfer wider than a single byte, a single TAXI Transmit- ter can be used to cascade the multiple bytes. This operation allows the data to ...
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Figure 7-2 Cascade with One TAXI Transmitter LOAD1- U1 STROBE D Q DFF CK 32 DATA 8 OE BUFFERS CK 74ALS374 8 BYTE1 7.2 Receivers In Cascade Mode: Connections (Am7969-125 Only) Unlike transmitters, all cascaded receivers are directly ...
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AMD X1 is connected to a common Crystal Oscillator or a TTL Clock Source not recommended that X1 be connected to another Receiver’s CLK output grounded. The DMS pins of all TAXls must be tied in ...
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Figure 7-4 Receiver Timing—8-Bit Cascade Mode Internal Clock* SERIN DATA N Serial Data NRZ Data* DATA N CLK OUT 1 CNB TAXI # IGM TAXI #1 = CNB TAXI #2 Command NO CHANGE OUT CSTRB OUT TAXI #1 ...
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AMD Figure 7-5 CNB and IGM Propagating Down Cascaded Receivers Serial Data CNB1 = V CC IGM1 CNB2 IGM2 CNB3 IGM3 = N/C Note: Half of the byte is sufficient for the Receiver to decide whether the byte is a ...
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The Data Out Lines When a Receiver sees the Sync symbol it sends the data byte it just received from its Input Latch to its Decoder Latch, and then the receiver lowers its IGM. One more clock cycle is required ...
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AMD Figure 7-7 Receiver Timing in Auto-Repeat Configuration Serial Data CNB1 IGM1 CNB2 IGM2 CNB3 IGM3 = CNB1 Note: Only when a Receiver has a CNB = 1, can it accept new data. It then raises its IGM when it ...
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Figure 7-8 Receiver Timing in Auto-Repeat Configuration Serial Data CNB1 IGM1 CNB2 IGM2 CNB3 IGM3 = CNB1 Note: When IGM3 goes HIGH CNB1 goes LOW. Thus, IGM1 = CNB2 goes LOW t that. This will ripple down to IGM3. TAXIchip ...
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AMD Figure 7-9 Receiver Timing in Auto-Repeat Configuration Serial Sync Data CNB1 IGM1 CNB2 IGM2 CNB3 IGM3 = CNB1 Note: IGM3 = CNB1 so RX1 is now ready to receive new data. The cycle can now be repeated. 7.3.2 Timing ...
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... Receivers and their IGMs so the upstream (Primary) Receiver receives the next non Sync byte of data. This remains as the method of recovering from byte framing errors. 7.4 Unbalanced Configuration (Am7968/Am7969-125 Only) In reality there is no difference in connection between balanced and Unbalanced Configurations. The name only indicates that the number of Transmit bytes and the number of Receive bytes are unequal ...
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... Test Mode need not be used. When there is no data to be sent, the TAXlchips will keep the line active by sending Syncs. 86 TAXIchip Integrated Circuits Technical Manual TTL Data Am7968 X1 X2 Clock X1 SERIN IGM CNB ...
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The serial link will operate in the 40 to 175 MHz range as determined by the byte rate clock, but the byte data rate will be determined by how often the user strobes the TAXI Transmitter. The transmission speed is ...
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... Byte Rate Clock Data Command TAXIchip Integrated Circuits Technical Manual N/C ACK TLS X1 STROBE X2 RESET Am7968 CLK CLS DMS SEROUT+ SEROUT– 300 300 Media Interface Bit Rate Clock Generator N/C = Test Mode Can Be Set for 10-Bit Mode ...
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Receiver Connections Refer to Figure 8-2. Grounding SERIN– puts the Receiver in Test Mode. SERIN single ended 100K ECL NRZ input. The X1 pin now becomes the bit rate clock input (bitclk), just like the CLK pin ...
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APPENDIX A Fiber Optic Data Link Manufacturer List Presented below is a partial listing of fiber optic data link suppliers that manufacture or market optical components in a data rate range compatible with the TAXIchip set. Several of these components ...
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APPENDIX B Error Detection Efficiency When a received data pattern does not represent a valid coding symbol, the TAXI Receiver asserts the VLTN pin to indicate that the current data contains an error. The Receiver cannot detect the occurrence of ...
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AMD For example, consider transmitting Hex B [1011], encoded as 10111. Error E occurs changes bits b0 & b1, resulting in encoded pattern 10100, which is Hex 2 [0010] 2 bits changed, and the run length the error = 4 ...
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Figure B Percent of Error 30 Events Figure B Percent of 30 Undetected Error Events TAXIchip Integrated Circuit Technical Manual Violation 1-Bit Error 2-Bit Error 8 Bit 9 Bit ...
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APPENDIX C TAXI Technical Information Publications The TAXI applications team has documented questions and answers that are general purpose in nature and applicable to a wide range of applications. This documentation has taken the form of TAXI Technical Information Publications ...
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TAXI TIPs TAXI Technical Information Publication #89-01 Subject: Receiver Response to Loss of Input Signal Question desired that the TAXI Receiver outputs be predictable and stable during conditions when the TAXI Transmitter may cease transmitting (power-off ...
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AMD TAXI Technical Information Publication #89-02 Subject: TAXlchip RESET Pin Function Question: How long must the RESET pin be held low in order to insure that the TAXIchip has reset? Answer: The RESET pin is level sensitive and after a ...
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TAXI Technical Information Publication #89-03 Subject: Proper Use for TAXI Sync Question: What is the proper use for Sync? How often is a Sync needed? Answer: When a Transmitter has no data to send, it sends Sync. This symbol allows ...
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AMD TAXI Technical Information Publication #89-04 Subject: TAXI PLL Lock-Up During Power-On! Question: Is there a recommended power-on sequence for the TAXIchips to prevent PLL lock-up? Answer: Early versions of the -70 TAXIchips did have some sensitivities associated with hot- ...
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TAXI Technical Information Publication #89-05 Subject: TAXIchip Set Crystal Specification Question: What are the design considerations for crystals used with TAXIchip set? Answer: The TAXIchip’s parallel mode oscillator uses a 4.0 MHz – 17.5 MHz crystal with a frequency tolerance ...
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AMD TAXI Technical Information Publication #89-06 Subject: TAXl for FDDI Applications? Question: Can the TAXIchip set be used for FDDI physical layer applications? Answer: The TAXIchip set is code compatible with the FDDI physical layer but there are restric- tions ...
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TAXI Technical Information Publication #89-07 Subject: Synchronous vs. Asynchronous Strobe Question: When should synchronous vs. asynchronous strobing be employed? Answer: Inputs to the TAXI Transmitter can be strobed asynchronously, but with some limita- tions. In local mode, the STROBE edge ...
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AMD TAXI Technical Information Publication #89-08 Subject: TAXI Receiver Lock Time Question fully operational system in which both the Transmitter and Receiver are powered on, how long will it take for the Receiver to lock to new data ...
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TAXI Technical Information Publication #89-10 Subject: TAXI Receiver CSTRB and DSTRB Pulse Width Question: What is the maximum CSTRB and DSTRB pulse width? Answer: The internal logic of the TAXI Receiver determines the pulse width of CSTRB and DSTRB based ...
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AMD Figure 11 (8-Bit Mode Example) TAXI Receiver Internal Clock Distribution Internal Bit Clock Internal Clock (Byte Rate) External Clock (CLK) Internal CSTRB & DSTRB External CSTRB & DSTRB Internal Data External Data 104 TAXIchip Integrated Circuits Technical Manual 9 ...
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TAXI Technical Information Publication #89-11 Subject: Using Receiver CLK Output to Run a TAXI Transmitter Question possible to use the Receiver CLK output to drive the X1 input of a TAXI Transmitter? Answer: To assure accurate transmission of ...
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... Crystal Filter 15K 15K U1 - GND V+ LMC660C 15K 15K GND SEROUT + SERIN + SEROUT - SERIN - Am7968 Am7969 Transmitter Receiver 7 X1 CLK X1 CLK X2 X2 12330E-41 GND SEROUT + VCM2 V SEROUT – CC MC4024 Am7968 VCX2 TAXI Transmitter OUT 2 X1 CX2 CLK GND X2 12330E-42 ...
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TAXI Technical Information Publication #89-12 Subject: TAXlchip Pins Internal Circuit Question: What do the TAXIchip I/O circuits look like? Answer: There are five different input circuits and two different output circuits in the TAXIchip set. Each I/O circuit has Electro ...
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AMD GND 12330E-43 ESD 300 ECL IN 300 ESD 50K GND ECL IN 108 TAXIchip Integrated Circuits Technical Manual TTL IN ESD DMS/CLS IN ESD 12330E- 22K 11K GND 12330E-44 TTL ...
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48K RESET ESD GND HIGH Threshold TTL OUT ESD 12330E-49 GND TTL OUT TAXIchip Integrated Circuits Technical Manual X1 ESD REF. X2 ESD 12330E- 300 GND AMD 125 5.3K GND ...
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AMD TAXI Technical Information Publication #89-13 Subject: Demuxing A TAXIchip Receiver Output to Multi-Byte Words Question: How can a single TAXI Receiver be used to receive multi-byte words? Answer: INTRODUCTION For systems that require data reception wider than a single ...
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Figure 14 Logic Diagram of Cascaded Data with One TAXI Receiver /RESET DMS CNB TAXIchip Integrated Circuits Technical Manual PRB CLK PRB X2 X1 VCC2 VCC1 AMD CLK PRB CLK CLK PRB PRB PRB CLK 12330E-51 111 ...
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AMD The circuitry that handles the Sync Commands or Sync Bytes generates several signals. The CMND0, CLR_CNTR, Sync and PCO are the signals that are generated by Sync Command logic. The CLR_CNTR signal is generated from the CMND0 and the ...
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High, without any additional logic. The VLTN signal is used for both Command and Data violations. Buffering of the DSTRB and VLTN signals may be necessary as illustrated in Figure 15 to meet the drive requirements of the first ...
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AMD Figure 15 Timing Diagram of 4-Demux Cascaded Receiver TAXI CLK /CLK DSTRB CSTRB RCVR DATA CLKCNTR CLK1 CLK2 CLK3 CLK4 CLKCNTR PCO Sync CLKOUT DATA OUT 114 TAXIchip Integrated Circuits Technical Manual Byte 4 ...
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... There are several advantages to using the multiplexed data scheme utilizing one TAXI Transmitter as opposed to a system using several Transmitters implement the mux circuit for 32 bits requires one Am7968 TAXI Transmitter and three relatively small integrated circuits. A 32-bit wide data path without multiplexing requires four Am7968 TAXI Transmitters ...
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... ACK0, auto-run ACK1 and Normal run modes. V. CONCLUSION To increase the length of a data word beyond eight bits, multiplex the data into an Am7968 TAXI Transmitter. This method uses less power, less board space, and lowers the parts cost of the system. 116 ...
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Figure 16 32-Bit Multiplexed Transmitter Circuit TAXIchip Integrated Circuits Technical Manual AMD 12330E-53 117 ...
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AMD Figure 17 AUTORUN ACK 0 (No Sync Between Data Bytes STRB TXCLK CSTRB DSTRB Figure 18 AUTORUN ACK 1 (One Sync Between Every ...
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Figure 19 Normal Run Mode (Transmission of Syncs Depends on Host STRB TXCLK CSTRB DSTRB TAXIchip Integrated Circuits Technical Manual AMD 12330E-56 119 ...
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... Receiver: 272 Wafer Fab: Location: Metal One: Metal Two: Passivation: 120 TAXIchip Integrated Circuits Technical Manual Transmitter (TX) Am7968-125 Am7968-175 4768 170 x 167 mils 3386 14 2504 87 595 See TAXI TIP #89-12 Typical Values (mA 5.5 V Process=Nominal, CD 028 package, CC Temp. forced with moving air flow (approx. theta ...
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Assembly/Packaging: Assembly Location: Ld. Frame Material: Bond Wire: Bonding Method: Die Attach: Molding Compound: Lead Finish Thermal Impedance RX: TX, RX socketed 2 surface mounted TAXIchip Integrated Circuits Technical Manual CerDIP (CD 028) LCC (CLT028) ...
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AMD TAXI Technical Information Publication #89-Nov ’89 Subject: TAXIchip Error Rate Example INTRODUCTION A method was devised to establish a baseline TAXIchip set error rate. A series of tests were conducted at a transmission rate of 125 MHz at room ...
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Board #4 failed on another occasion after the errors indicated above, but this failure was due to a power supply failure. Failure time was subtracted from the total run time, and errors were not indicated in the total. Also, boards ...