UPD720101F1-EA8 Renesas Electronics Corporation., UPD720101F1-EA8 Datasheet
UPD720101F1-EA8
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UPD720101F1-EA8 Summary of contents
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The PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The interface and ...
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BLOCK DIAGRAM PME0 INTA0 WakeUp_Event OHCI Host Controller #1 PHY Port 1 Port 2 Remark INTB0/INTC0 can be shared with INTA0 through BIOS setting. (Planning) 2 PCI Bus INTB0 PCI Bus Interface WakeUp_Event Arbiter OHCI Host Controller #2 Root Hub ...
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PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI specification release 2.2. The number of enabled ports is set by bit in configuration space. Arbiter : arbitrates among two OHCI host ...
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PIN CONFIGURATION • 144-pin plastic LQFP (Fine pitch) (20 × 20) µ PD720101GJ-UEN µ PD720101GJ-UEN OCI1 PPON1 OCI2 5 PPON2 OCI3 PPON3 OCI4 PPON4 10 OCI5 PPON5 VCCRST0 PME0 15 PCLK VBBRST0 V DD_PCI V ...
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Pin No. Pin Name Pin No OCI1 39 AD23 4 PPON1 40 AD22 5 OCI2 41 AD21 6 PPON2 42 AD20 7 OCI3 PPON3 44 AD19 ...
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FBGA (12 × 12) µ PD720101F1-EA8 µ PD720101F1-EA8 111 112 113 114 115 116 117 118 119 120 22 69 110 21 68 109 20 67 108 136 ...
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Pin No. Pin Name Pin No AD23 AD20 39 PPON2 4 AD18 40 OCI4 5 CBE20 41 PPON5 6 TRDY0 42 PCLK 7 SERR0 43 INTC0 8 AD15 44 AD31 9 ...
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PIN INFORMATION Pin Name I/O Buffer Type PCI I/O CBE (3 : 0)0 I PCI I/O PAR I PCI I/O FRAME0 I PCI I/O IRDY0 I/O ...
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Pin Name I/O Buffer Type SMC I Input with 50 kΩ pull down R TEB I Input with 50 kΩ pull down R AMC I Input with 50 kΩ pull down R TEST I Input with 50 kΩ pull down ...
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HOW TO CONNECT TO EXTERNAL ELEMENTS 2.1 Handling Unused Pins To realize less than 5 ports host controller implementation, appropriate value shall be set to Port No field in EXT1 register. And unused pins shall be connected as shown ...
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PLL Capacitor Connection 2.4 X’tal Connection LSI XT1/SCLK The following crystals are evaluated on our reference design board. Table 2-1 shows the external parameters. Figure 2-2. RREF Connection LSI RREF ± 9.1kΩ ( Figure ...
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Vender Note 1 KDS AT-49 30.000 MHz Note 2 NDK AT-41 30.000 MHz AT-41CD2 30.000 MHz NX3225DA 30.000 MHz NX5032GA 30.000 MHz NX8045GB 30.000 MHz Notes 1. DAISHINKU CORP. 2. NIHON DEMPA KOGYO CO., LTD. In using these crystals, contact ...
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ELECTRICAL SPECIFICATIONS 3.1 Buffer List • input buffer with pull down resistor NTEST1, TEST, SRMOD, NANDTEST, SMC, AMC, TEB • PCI 3-state output buffer OL PPON(5:1), SRCLK • ...
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Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage DD_PCI Input voltage V I Output voltage V O Operating ambient temperature T A Storage temperature T stg Terms Used in Recommended ...
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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage DD_PCI Input voltage buffer V I Input voltage, 3.3 V buffer V I Output voltage buffer V O Output voltage, ...
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DC Characteristics (V = 3 Control pin block Parameter Off-state output current Output short circuit current Low-level output current 3.3 V low-level output current 3.3 V low-level output current 5.0 V low-level output current 5.0 ...
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USB interface block Parameter Serial resistor between DP (DM) and RSDP (RSDM) Output pin impedance Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for ...
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Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed −1.0 0.0 0.2 0.4 0.6 0.8 Figure 3-2. Full-speed Buffer V −3.3 −2 Min. Max. Figure 3-3. Full-speed Buffer 0.5 18 ...
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Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 Level 2 0% Figure 3-5. Receiver Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω Pin capacitance Parameter Input capacitance Output capacitance I/O capacitance PCI input pin ...
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Power consumption Parameter Symbol Power Consumption P Device state = D0, All the ports does not connect to WD0-0 any function, and each OHCI controller is under UsbSuspend and EHCI controller is stopped. P The power consumption under the state ...
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System clock ratings Parameter Clock frequency Clock duty cycle Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply ...
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AC Characteristics (V = 3 PCI interface block Parameter PCI clock cycle time PCI clock pulse, high-level width PCI clock pulse, low-level width PCI clock, rise slew rate PCI clock, fall slew rate PCI reset ...
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USB interface block Parameter Low-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Differential rise and fall time matching Low-speed data rate Source jitter total (including frequency tolerance): To next transition For paired transitions Source ...
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Parameter High-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance Hub Event Timings Time to detect a downstream ...
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Figure 3-6. Transmit Waveform for Transceiver at DP/DM Level 1 Point 3 Point 1 Point 5 Level 2 Unit Interval 0% Figure 3-7. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Vbus Connector D+ Nearest D- 15.8 Ω Device ...
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Timing Diagram PCI clock 0.6V DD 0.5V DD 0.4V DD 0.3V DD 0.2V DD PCI reset PCLK PWR_GOOD VBBRST0 PCI Signals 26 t cyc t t high low 100 ms (typ.) t rst-clk t rst Data Sheet S16265EJ5V0DS µ ...
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PCI output timing measurement condition PCLK Output delay Output PCI input timing measurement condition PCLK Input 0. (ptp) val val 0.615V (for falling edge) DD 0.285V (for falling edge ...
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USB differential data jitter for full-speed t PERIOD Differential Data Lines N × t USB differential-to-EOP transition skew and EOP width for low-/full-speed t PERIOD Crossover Point Differential Data Lines Diff. Data-to- SE0 Skew N × t USB receiver jitter ...
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Low-/full-speed disconnect detection D+/D− V (min) IZH V IL D−/ Device Disconnected Full-/high-speed device connect detection Device Connected Low-speed device connect detection Device Connected t DDIS Disconnect Detected D+ D− ...
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PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) 108 109 144 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC FBGA (12x12) E INDEX MARK φ φ ...
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RECOMMENDED SOLDERING CONDITIONS µ The PD720101 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. ...
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Data Sheet S16265EJ5V0DS µ PD720101 33 ...
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Data Sheet S16265EJ5V0DS µ PD720101 ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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USB logo is a trademark of USB Implementers Forum, Inc. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. • The information in this document is current as of Macrh, ...