EP910ILI-12

Manufacturer Part NumberEP910ILI-12
ManufacturerAltera Corporation
EP910ILI-12 datasheet
 


Specifications of EP910ILI-12

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Classic EPLD Family Data Sheet
Table 30. EP1810-35 & EP1810-45 External Timing Parameters
Symbol
Parameter
t
Input to non-registered output
PD1
t
I/O input to non-registered output
PD2
t
Global clock setup time
SU
t
Global clock hold time
H
t
Global clock high time
CH
t
Global clock low time
CL
t
Global clock to output delay
CO1
t
Minimum global clock period
CNT
f
Maximum internal frequency
CNT
t
Array clock setup time
ASU
t
Array clock hold time
AH
t
Array clock to output delay
ACO1
t
Output data hold time after clock
ODH
t
Array clock maximum clock period
ACNT
f
Maximum internal array clock
ACNT
frequency
f
Maximum clock frequency
MAX
Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters
Symbol
Parameter
t
Input pad and buffer delay
IN
t
I/O input pad and buffer delay
IO
t
Logic array delay
LAD
t
Output buffer and pad delay
OD
t
Output buffer enable delay
ZX
t
Output buffer disable delay
XZ
t
Register setup time
SU
t
Register hold time
H
t
Array clock delay
IC
t
Global clock delay
ICS
t
Feedback delay
FD
t
Register clear time
CLR
784
Note (1)
Conditions
EP1810-35 EP1810-45 Non-Turbo
Min Max Min Max
C1 = 35 pF
35.0
C1 = 35 pF
40.0
25.0
0.0
12.0
12.0
C1 = 35 pF
20.0
(3)
35.0
(3)
28.6
10.0
15.0
C1 = 35 pF
35.0
C1 = 35 pF
(4)
1.0
(3)
35.0
(3)
28.6
(5)
40
EP1810-35 EP1810-45 Non-Turbo
Conditions
Min Max Min Max
7.0
5.0
19.0
C1 = 35 pF
9.0
C1 = 35 pF
9.0
C1 = 5 pF
(6)
9.0
10.0
15.0
19.0
4.0
6.0
24.0
Unit
Adder
(2)
45.0
30.0
ns
50.0
30.0
ns
30.0
30.0
ns
0.0
0.0
ns
15.0
0.0
ns
15.0
0.0
ns
25.0
0.0
ns
45.0
0.0
ns
22.2
0.0
MHz
11.0
30.0
ns
18.0
0.0
ns
45.0
30.0
ns
1.0
ns
45.0
0.0
ns
22.2
0.0
ns
33.3
0.0
MHz
Unit
Adder
(2)
6.0
0.0
ns
5.0
0.0
ns
28.0
30.0
ns
11.0
0.0
ns
11.0
0.0
ns
11.0
0.0
ns
10.0
0.0
ns
18.0
0.0
ns
28.0
30.0
ns
8.0
0.0
ns
7.0
–30.0
ns
32.0
30.0
ns
Altera Corporation