AS7C1026-15JC

Manufacturer Part NumberAS7C1026-15JC
Description5V 64K x 16 CM0S SRAM , 15ns access time
ManufacturerAlliance Semiconductor
AS7C1026-15JC datasheet
 
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Functional description

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Functional description

The AS7C1026 and AS7C31026 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
for high-performance applications.
When CE is high the devices enter stanby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in
CMOS standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply
(AS7C31026). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in
manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and
external dimensions of 8 mm × 6 mm.
Absolute maximum ratings
Parameter
Voltage on V
relative to GND
CC
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
H
X
X
L
H
L
L
H
L
L
H
L
L
L
X
L
L
X
3/23/01; v.1.0
®
, t
, t
) of 12/15/20 ns with output enable access times (t
AA
RC
WC
Symbol
AS7C1026
V
t1
AS7C31026
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
LB
UB
I/O0–I/O7
X
X
High Z
L
H
D
OUT
H
L
High Z
L
L
D
OUT
L
L
D
IN
L
H
D
IN
Alliance Semiconductor
AS7C1026
AS7C31026
) of 6,7,8 ns are ideal
OE
Min
Max
–0.50
+7.0
–0.50
+5.0
–0.50
V
+0.50
CC
1.0
–65
+150
–55
+125
20
I/O8–I/O15
Mode
High Z
Standby (I
), I
SB
SBI
High Z
Read I/O0–I/O7 (I
D
Read I/O8–I/O15 (I
OUT
D
Read I/O0–I/O15 (I
OUT
D
Write I/O0–I/O15 (I
IN
High Z
Write I/O0–I/O7 (I
P. 2 of 10
Unit
V
V
V
W
C
C
mA
)
)
CC
CC)
)
CC
)
CC
)
CC