HY57V658020BLTC-10 Hynix Semiconductor, HY57V658020BLTC-10 Datasheet

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HY57V658020BLTC-10

Manufacturer Part Number
HY57V658020BLTC-10
Description
4Mbit x 2 bank x 8 SDRAM, LVTTL, low power, 100MHz
Manufacturer
Hynix Semiconductor
Datasheet
DESCRIPTION
The Hynix HY57V658020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V658020B is organized as 4banks of 2,097,152x8.
HY57V658020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
ORDERING INFORMATION
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.6/Nov. 01
HY57V658020BLTC-10P
HY57V658020BLTC-10S
HY57V658020BTC-10P
HY57V658020BTC-10S
Single 3.3 0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of sys-
tem clock
Data mask function by DQM
Internal four banks operation
HY57V658020BLTC-75
HY57V658020BLTC-10
HY57V658020BTC-75
HY57V658020BTC-10
HY57V658020BLTC-8
HY57V658020BTC-8
Part No.
Clock Frequency
133MHz
125MHz
100MHz
100MHz
100MHz
133MHz
125MHz
100MHz
100MHz
100MHz
Low power
Power
Normal
4Banks x 4Mbits x4
4 Banks x 2M x 8Bit Synchronous DRAM
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
Programmable CAS Latency ; 2, 3 Clocks
Organization
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Interface
LVTTL
HY57V658020B
400mil 54pin TSOP II
Package
1

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HY57V658020BLTC-10 Summary of contents

Page 1

... HY57V658020BTC-10 HY57V658020BLTC-75 HY57V658020BLTC-8 HY57V658020BLTC-10P HY57V658020BLTC-10S HY57V658020BLTC-10 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.6/Nov Banks 8Bit Synchronous DRAM • ...

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PIN CONFIGURATION PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A11 Address Row Address Strobe, RAS, CAS, WE Column Address Strobe, Write Enable DQM Data Input/Output Mask DQ0 ~ ...

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FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 8 I/O Synchronous DRAM Self refresh logic & timer CLK Row active CKE CS RAS CAS refresh WE Column Active DQM Bank Select A0 Address Registers A1 A11 BA0 BA1 Mode Registers Rev. ...

Page 4

ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Short Circuit Output Current Power Dissipation Soldering Temperature Time Note : Operation at above absolute maximum ...

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CAPACITANCE (TA=25 C, f=1MHz) Parameter Input capacitance CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM Data input / output capacitance DQ0 ~ DQ7 OUTPUT LOAD CIRCUIT Output DC Output Load Circuit DC CHARACTERISTICS I Parameter Symbol ...

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... Note : 1.I and I depend on output loading and cycle rates. Specified values are measured with the output open DD1 DD4 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V658020BTC-75/8/10P/10S/10 4.HY57V658020BLTC-75/8/10P/10S/10 Rev. 1.6/Nov. 01 (TA =3.3 0.3V, V =0V Test Condition Burst length=1, One bank active ...

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AC CHARACTERISTICS I Parameter Symbol CAS Latency = 3 tCK3 System clock cycle time CAS Latency = 2 tCK2 Clock high pulse width tCHW Clock low pulse width tCLW CAS Latency = 3 tAC3 Access time from clock CAS Latency ...

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AC CHARACTERISTICS II Parameter Symbol t Operation RC RAS Cycle Time t Auto Refresh RRC t RAS to CAS Delay RCD t RAS Active Time RAS t RAS Precharge Time RP t RAS to RAS Bank Active Delay RRD t ...

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IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage (Min) (Max) (V) I(mA) I(mA) 3.45 -2.4 3.3 -27.3 3.0 0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197 1.8 -67.3 -226.2 1.65 -73 -248 1.5 -77.9 -269.7 1.4 ...

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DEVICE OPERATING OPTION TABLE HY57V658020B(L)TC-75 CAS Latency 133MHz(7.5ns) 3CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs HY57V658020B(L)TC-8 CAS Latency 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs 83MHz(12ns) 2CLKs HY57V658020B(L)TC-10P CAS Latency 100MHz(10ns) 2CLKs 83MHz(12ns) 2CLKs 66MHz(15ns) 2CLKs HY57V658020B(L)TC-10S CAS Latency 100MHz(10ns) 3CLKs 83MHz(12ns) 2CLKs 66MHz(15ns) 2CLKs ...

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COMMAND TRUTH TABLE Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Entry 1 Self Refresh Exit Entry Precharge power down ...

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PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 0.400(0.016) 0.80(0.0315)BSC 0.300(0.012) Rev. 1.6/Nov. 01 UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 5deg 0.210(0.0083) 0.597(0.0235) 0deg 0.406(0.0160) 0.120(0.0047) HY57V658020B 1.194(0.0470) 0.991(0.0390) 12 ...

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