DA28F016XS-25 Intel Corporation, DA28F016XS-25 Datasheet
DA28F016XS-25
Related parts for DA28F016XS-25
DA28F016XS-25 Summary of contents
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MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY n Effective Zero Wait-State Performance MHz Synchronous Pipelined Reads n SmartVoltage Technology User-Selectable 3. User-Selectable 5V or 12V 0.33 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493 ...
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INTRODUCTION ............................................ 7 1.1 Product Overview ........................................ 7 2.0 DEVICE PINOUT........................................... 10 2.1 Lead Descriptions ...................................... 12 3.0 MEMORY MAPS ........................................... 14 3.1 Extended Status Register Memory Map..... 15 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 16 4.1 ...
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FLASH MEMORY REVISION HISTORY Number -001 Original Version Removed support of the following features: -002 All page buffer operations (read, write, programming, Upload Device Information) Command queuing Software Sleep and Abort Erase all Unlocked Blocks and Two-Byte Write RY/BY# ...
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REVISION HISTORY (Continued) Number Require all V Tolerences to be within 5% of Operational Voltage -004 Pushed to 200 µA from 50 Max PPES I Is Pushed to 10 µA from 5 Max CCD Updated t at ...
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FLASH MEMORY This page intentionally left blank 6 ...
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INTRODUCTION The documentation of the Intel 28F016XS Flash memory device includes this datasheet, a detailed user’s manual, a number of application notes and design tools, all of which are referenced in Appendix B. The datasheet is intended to give ...
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FLASH MEMORY address inputs. During read operations, addresses are latched and accesses are initiated on a rising CLK edge in conjunction with ADV# low. Both CLK and ADV# are ignored by the 28F016XS during command/data write sequences. The 28F016XS ...
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DQ 8-15 Output Buffer CLK ADV# Input Buffer Y Decoder X Decoder Address Register X Decoder Y Decoder Figure 1. 28F016XS Block Diagram Architectural Evolution Includes Synchronous Pipelined Read Interface, SmartVoltage Technology, and Extended Status Registers 4/15/97 9:41 AM INTEL ...
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FLASH MEMORY The BYTE# pin allows either x8 read/programs to the 28F016XS. BYTE# at logic low selects 8-bit mode with address A 0 between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit ...
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... Figure 3. 28F016XS 56-Lead SSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV, Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY DA28F016XS 45 56-LEAD SSOP 44 STANDARD PINOUT 23 TOP VIEW ...
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FLASH MEMORY 2.1 Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device mode. This address is latched in x8 data programs and ignored in x16 mode (i.e., the ...
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Lead Descriptions (Continued) Symbol Type CLK INPUT CLOCK: Provides the fundamental timing and internal operating frequency. CLK latches input addresses in conjunction with ADV#, times out the desired output SFI Configuration as a function of the CLK period, and ...
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FLASH MEMORY 2.1 Lead Descriptions (Continued) Symbol Type GROUND FOR ALL INTERNAL CIRCUITRY: GND SUPPLY Do not leave any ground pins floating. NO CONNECT: NC Lead may be driven or left floating. 3.0 MEMORY MAPS x8 Mode A 20-0 ...
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Extended Status Register Memory Map x8 Mode A 20-0 1FFFFFH RESERVED 1E0006H RESERVED 1E0005H GSR 1E0004H RESERVED 1E0003H BSR 15 1E0002H RESERVED 1E0001H RESERVED 1E0000H . . . 01FFFFH RESERVED 000006H RESERVED 000005H GSR 000004H RESERVED 000003H BSR 0 ...
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FLASH MEMORY 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE Mode Notes RP 0–1 Latch Read 1,9, Address Inhibit 1 ...
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Bus Operations for Byte-Wide Mode (BYTE Mode Notes RP 0–1 Latch Read 1,9, Address Inhibit 1 Latching Read Address Read 1,2,7 Output 1,6,7,9 ...
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FLASH MEMORY 4.3 28F008SA—Compatible Mode Command Bus Definitions Command Notes Read Array Intelligent Identifier 1 Read Compatible Status Register 2 Clear Status Register 3 Program Alternate Program Block Erase/Confirm Erase Suspend/Resume ADDRESS AA = Array Address BA = Block ...
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Command Bus Definitions Command Notes Read Extended Status Register 1 Lock Block/Confirm Upload Status Bits/Confirm 2 Device Configuration 3 ADDRESS DATA BA = Block Address AD = Array Data RA = Extended Register Address BSRD = BSR Data ...
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FLASH MEMORY 4.5 Compatible Status Register WSMS ESS CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ...
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Global Status Register WSMS OSS DOS GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION ...
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FLASH MEMORY 4.7 Block Status Register BS BLS BOS BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase ...
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... Undocumented combinations of SFI2-SFI0 are reserved by Intel Corporation for future implementations and should not be used. Undocumented combinations of RB are reserved by Intel Corporation for future implementations and should not be used ...
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FLASH MEMORY 5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings* Temperature Under Bias ....................0°C to +80°C Storage Temperature ................... –65°C to +125° 3.3V ± 5% Systems CC Symbol Parameter T Operating Temperature, Commercial with Respect ...
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Capacitance For a 3.3V ± 5% System: Symbol Parameter C Capacitance Looking into an IN Address/Control Pin C Capacitance Looking into an OUT Output Pin C Load Capacitance Driven by LOAD Outputs for Timing Specifications For 5.0V ± 5% ...
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FLASH MEMORY 5.3 Transient Input/Output Reference Waveforms 2.4 2.0 INPUT 0.8 0.45 AC test inputs are driven at V (2.4 VTTL) for a Logic “1” and V OH (2.0 VTTL) and V (0.8 VTTL). Output timing ends at V ...
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DC Characteristics V = 3.3V ± 5 0°C to +70° 3/5# = Pin Set High for 3.3V Operations Symbol Parameter Notes I Input Load Current Output Leakage 1 LO Current I V ...
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FLASH MEMORY 5.4 DC Characteristics (Continued 3.3V ± 5 0°C to +70° 3/5# = Pin Set High for 3.3V Operations Symbol Parameter Notes I V Program 1,6 CCW CC Current I V Block ...
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DC Characteristics (Continued 3.3V ± 5 0°C to +70° 3/5# = Pin Set High for 3.3V Operations Symbol Parameter Notes V V 3,6 PPLK PP Erase/Program Lock Voltage V V during 3 PPH1 ...
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FLASH MEMORY 5.5 DC Characteristics V = 5.0V ± 5 0°C to +70° 3/5# = Pin Set Low for 5.0V Operations Parameter Notes Symbol I Input Load Current Output Leakage 1 LO ...
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DC Characteristics (Continued 5.0V ± 5 0°C to +70° 3/5# = Pin Set Low for 5.0V Operations Parameter Notes Symbol I V Program 1,6 CCW CC Current I V Erase 1,6 CCE CC ...
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FLASH MEMORY 5.5 DC Characteristics (Continued 5.0V ± 5 0°C to +70° 3/5# = Pin Set Low for 5.0V Operations Parameter Notes Symbol V V 3,6 PPLK PP Program/Erase Lock Voltage V V ...
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Timing Nomenclature All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems, use the standard JEDEC cross point definitions (standard testing) or from where signals cross 1.5V (high speed testing). Each timing parameter consists of ...
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FLASH MEMORY 5.7 AC Characteristics—Read Only Operations V = 3.3V ± 5 0°C to +70° (3) Versions Symbol Parameter f CLK Frequency CLK t CLK Period CLK t CLK High Time CH t CLK Low ...
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AC Characteristics—Read Only Operations V = 5.0V ± 5 0°C to +70° (3) Versions Symbol Parameter f CLK Frequency CLK t CLK Period CLK t CLK High Time CH t CLK Low Time CL t ...
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FLASH MEMORY CLCH Figure 10. CLK Waveform CLK ADDR t CHAX CLK Periods t AVCH ADV# t VLCH t CHVH CEx# t ELCH t ELQX OE# t GLCH Even t GLQX DATA NOTE: ...
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CLK ADDR t CHAX CLK Periods t AVCH ADV# t VLCH t CHVH CEx# t ELCH t ELQX OE# t GLCH Even t GLQX DATA NOTE: 1. The 28F016XS can sustain an optimized burst access throughout the ...
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FLASH MEMORY CLK ADDR t CHAX CLK Periods t AVCH ADV# t VLCH t CHVH CEx# t ELCH t ELQX OE# t GLCH Even t GLQX DATA NOTES: 1. The 28F016XS can sustain an optimized burst ...
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CLK ADDR t CHAX CLK Periods t AVCH ADV# t VLCH t CHVH CEx# t ELCH t ELQX OE# t GLCH Even t GLQX DATA t PHCH RP# NOTE: 1. The 28F016XS can sustain an optimized burst ...
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FLASH MEMORY 5.8 AC Characteristics for WE#—Controlled Write Operations V = 3.3V ± 5 0°C to +70° Versions Symbol Parameter t Write Cycle Time AVAV t 1,2 V Setup to WE# Going VPWH PP High ...
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AC Characteristics for WE#—Controlled Write Operations V = 5.0V ± 5 0°C to +70° Versions Symbol Parameter t Write Cycle Time AVAV t 1,2 V Setup to WE# Going VPWH PP High t RP# Setup ...
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FLASH MEMORY NOTES: 1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. Guaranteed by design. 4. ...
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CLK NOTE 6 WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND V IH ADDRESSES ( NOTE AVAV t AVWH V IH ADDRESSES (A) A ...
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FLASH MEMORY 5.9 AC Characteristics for 3.3V ± 5 0°C to +70° Versions Symbol Parameter t Write Cycle Time AVAV t 1,2 V Setup Going VPEH PP X High ...
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AC Characteristics for 5.0V ± 5 0°C to +70° Versions Symbol Parameter t Write Cycle Time AVAV t 1,2 V Setup Going VPEH PP X High t RP# Setup ...
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FLASH MEMORY NOTES: 1. Read timings during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. Guaranteed by design. 4. ...
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CLK NOTE 6 WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND V IH ADDRESSES ( NOTE AVAV t AVEH V IH ADDRESSES (A) A ...
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FLASH MEMORY 5.10 Power-Up and Reset Timings V POWER-UP CC RP# t YHPH (P) 3/5# (Y) 3. (3V,5V) NOTE: For read timings following reset see Section 5.7. Figure 17 Symbol Parameter t RP# Low ...
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Erase and Program Performance V = 3.3V ± 5 5.0V ± 5 0°C to +70° Symbol Parameter Notes t 1A Byte Program Time 2,5 WHRH t 1B Word Program Time 2,5 WHRH ...
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FLASH MEMORY 5.11 Erase and Program Performance V = 5.0V ± 5 5.0V ± 5 0°C to +70° Symbol Parameter Notes t 1A Byte Program Time 2,5 WHRH t 1B Word Program ...
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MECHANICAL SPECIFICATIONS Figure 18. Mechanical Specifications of the 28F016XS 56-Lead TSOP Type I Package Family: Thin Small Out-Line Package Symbol Minimum 0.050 A 2 0.965 b 0.100 c 0.115 D 1 18.20 E 13. ...
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FLASH MEMORY Figure 19. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package Family: Shrink Small Out-Line Package Symbol Minimum A A1 0.47 A2 1.18 B 0.25 C 0.13 D 23.40 E 13.10 ...
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... Mbit Product Family X = Fast Flash Option Order Code V 1.5V I/O Levels 1 E28F016XS15 2 E28F016XS20 3 DA28F016XS15 4 DA28F016XS20 NOTE: 1. See Section 5.3 for Transient Input/Output Reference Waveforms. 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY APPENDIX Period of Maximum CLK Input Frequency (ns) Device Type S = Synchronous Pipelined ...
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FLASH MEMORY ADDITIONAL INFORMATION Order Number 16-Mbit Flash Product Family User’s Manual 297372 292147 AP-398 Designing with the 28F016XS 292146 AP-600 Performance Benefits and Power/Energy Savings of 28F016XS- Based System Designs 292163 AP-610 Flash Memory In-System Code and Data ...