82C55 Intel Corporation, 82C55 Datasheet
82C55
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82C55 Summary of contents
Page 1
... RAD (Si)/s - Latch Up Free EPI-CMOS • Low Power Consumption - IDDSB = 20 A • Pin Compatible with NMOS 8255A and the Intersil 82C55A • High Speed, No “Wait State” Operation with 5MHz HS-80C86RH • 24 Programmable I/O Pins • Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors • ...
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... Chip Select: A “low” on this input pin enables the communication between the HS-82C55ARH and the CPU. Read: A “low” on this input pin enables the HS-82C55ARH to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the HS-82C55ARH. Write: A “ ...
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... No internal current limiting exists on the Port Outputs. A resistor must be added externally to limit the current. 4. For VIH (VDD = 5.5V) and VIL (VDD = 4.5V) each of the following groups is tested separately with all other inputs using VIH = 2.6V, VIL = 0.4V: PA, PB, PC, Control Pins (Pins 35, 36). Specifications HS-82C55ARH Reliability Information Thermal Resistance SBDIP Package ...
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... TKLKH STB Pulse Width TSLSH Peripheral Data Before TPVSH STB High Peripheral Data After TSHPX STB High ACK = 0 to Output TKLPV ACK = 1 to output Float TKHPZ Specifications HS-82C55ARH SUB- CONDITIONS GROUPS TEMPERATURE VDD = 4.5, 5.5V 9, 10, 11 -55 VDD = 4.5, 5.5V 9, 10, 11 -55 VDD = 4.5, 5.5V 9, 10, 11 -55 VDD = 4 ...
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... NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics TALBE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS o See +25 C limits in Table 1 and Table 2 for Post RAD limits (Subgroups Specifications HS-82C55ARH A SUB- CONDITIONS GROUPS TEMPERATURE VDD = 4 ...
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... Group C Sample 5005 Group D Sample 5005 Group E, Subgroup 2 Sample 5005 NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only Specifications HS-82C55ARH SYMBOL IDDSB IIL, IIH IOZL, IOZH VOL VOH1 VOH2 TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS ...
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... Group B and D attributes and/or Generic data is included when required by the P.O. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HS-82C55ARH 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) ...
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... TEST CONDITIONS DEFINITION TABLE 1.7V 523 Open HS-82C55ARH 100% Dynamic Burn-In, Condition D, 160 Hours, +125 Equivalent, Method 1015 100% Interim Electrical Test 100% PDA, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 ...
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... CS, A1 TRLDV FIGURE 1. MODE 0 (BASIC INPUT) TSLSH STB IBF TRLNL TSLIH INTR TSHNH RD INPUT FROM PERIPHERAL TPVSH FIGURE 3. MODE 1 (STROBED INPUT) DATA FROM CPU TO HS-82C55ARH WR TKLOH OBF TWHOL INTR ACK TSLSH STB IBF TSLIH TKLPV TPVSH PERIPHERAL BUS TSHPX RD DATA FROM ...
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... STATIC CONFIGURATION NOTES: 1. VDD = 6. IDD <500 Min = +125 C A HS-82C55ARH PROGRAMMABLE PERIPHERAL INTERFACE VDD DYNAMIC CONFIGURATION NOTES: 1 ...
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... Irradiation Circuit CMOS PROGRAMMABLE PERIPHERAL INTERFACE +5.5V NOTE: 1. VDD = 5.5V HS-82C55ARH +5. 980 518060 Spec Number ...
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... MONITORING. Data Bus Buffer This tri-state bidirectional 8-bit buffer is used to interface the HS-82C55ARH to the system data bus (see Figure 8). Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer ...
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... After reset, the HS- 82C55ARH can remain in the input mode with no additional initialization required. This eliminates the need for pullup or pulldown resistors in all CMOS designs. During the execution of the system program, any of the other modes may be selected using a single output instruction ...
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... The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the HS-82C55ARH has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional fl ...
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... CONTROL WORD # HS-82C55ARH GROUP A PORT A PORT C (UPPER) Output Output Output Output Output Output Output Output Output Input Output Input Output Input Output Input Input Output Input ...
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... CONTROL WORD # HS-82C55ARH PA7 - PA0 4 PC7 - PC4 PC3 - PC0 8 PB7 - PB0 ...
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... A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. HS-82C55ARH ...
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... WR input and reset by ACK input being low. ACK (Acknowledge Input) A “low” on this input informs the HS-82C55ARH that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data ...
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... INTE 2 (The INTE Flip-Flop Associated with IBF) Controlled by Bit Set/Reset of PC4. HS-82C55ARH CONTROL WORD 1/0 1/0 1/0 FIGURE 20. MODE CONTROL WORD WR RD FIGURE 21. MODE 2 (BIDIRECTIONAL) DATA FROM CPU TO HS-82C55ARH WR OBF TWHOL INTR ACK STB IBF TSLIH PERIPHERAL BUS RD DATA FROM PERI- ...
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... Reset Port C Bit” command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the “Set/ Reset Port C Bit” command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 25. HS-82C55ARH MODE DEFINITION SUMMARY MODE 1 OUT ...
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... Current Drive Capability Any output on Port can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. Reading Port C Status (Figures 23 and 24) In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes Port C generates or accepts “ ...
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... Type: SiO2 Å Å Thickness WORST CASE CURRENT DENSITY 7 A/cm Metallization Mask Layout PC2 (16) PC3 (17) PB0 (18) PB1 (19) PB2 (20) PB3 (21) PB4 (22) PB5 (23) PB6 (24) PB7 (25) HS-82C55ARH HS-82C55ARH 991 (5) RD (4) PA0 (3) PA1 (2) PA2 (1) PA3 (40) PA4 (39) PA5 (38) PA6 (37) PA7 (36) WR 518060 Spec Number ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HS-82C55ARH EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...