CS4226-BQ Cirrus Logic, Inc., CS4226-BQ Datasheet
CS4226-BQ
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CS4226-BQ Summary of contents
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... ORDERING INFORMATION CS4226-KQ -10° to +70° C 44-pin TQFP CS4226-KQZ -10° to +70° C 44-pin TQFP Lead Free CS4226-BQ -40° to +85° C 44-pin TQFP CS4226-BQZ -40° to +85° C 44-pin TQFP Lead Free CS4226-DQ -40° to +85° C 44-pin TQFP CDB4226 2 VD+ ...
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... DTS is a registered trademark of the Digital Theater Systems, Inc. Dolby, Dolby Digital, AC-3, AAC, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. THX is a registered trademark of Lucasfilms Ltd Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys 2 C system. CS4226 DS188F4 ...
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... Table 4. DSP Serial Interface Ports .............................................................................................. 15 Table 5. S/PDIF Receiver Status Outputs..................................................................................... 18 Revision Date F1 September 1998 Initial release. F2 March 2003 Update drawings. F3 September 2004 Added lead free part information. F4 November 2004 Added lead free part information. DS188F4 2 C Mode....................................................................................... 20 Table 1. Change History Changes CS4226 3 ...
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... Notes: 1. Any pin except supplies. Transient currents ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over or under voltage is limited by the input current. 4 Symbol Digital VD+ 4.75 Analog VA+ 4.75 CS4226-KQ/-KQZ T A CS4226-BQ/-BQZ CS4226-DQ (AGND, DGND = 0V, all voltages with respect to 0V.) Symbol Min Digital VD+ -0.3 Analog VA+ -0.3 (Note 1) - (Note 2) -0 ...
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... Min Typ 16 Mono channel 16 THD 0.003 (Note 3) THD+N - (Note 2.7 - 0.90 - 100 (Note (Note 5) 0.02 - (Note 5) 27.56 (Note 15/Fs gd ∆ 15/44.1 kHz = 340 µs gd CS4226 CS4226-BQ/-BQZ/-DQ Max Min Typ Max - 0.003 - -88 -82 - -86 - -70 90 ...
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... Notes: 8. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz, the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs. 9. Digital filter characteristics. 10. Measurement bandwidth Fs. 6 (Continued) CS4226-KQ/-KQZ CS4226-BQ/-BQZ/-DQ Symbol Min Typ (Note ...
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... SCLK Duty Cycle Slave Mode SCLK Period SCLK High Time SCLK Low Time SCLK Rising to LRCK Edge LRCK Edge to SCLK Rising Notes: 11. After powering up the CS4226, PDN should be held low until the power supply is settled. SCLK* SCLKAUX* (output) LRCK LRCKAUX (output) ...
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... CS4226 (Inputs: logic 0 = DGND, logic 1 = Min Max Units - 6 MHz µs 1 100 ns 100 ...
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... N V 200 HYST (Note 15) - (Note 16) 40 Symbol Min (except RX1) V 2.8 IH (except RX1 (VD+)-1 (Digital Inputs CS4226 Min Max Units - 100 kHz µs 4.7 µs 4.0 µs 4.7 µs 4.0 µs 4.7 µs 0 250 ns µs 1 300 ns µs 4.7 Typ Max Units 10 - kΩ ...
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... R R FILT X1 Loop Current Normal High 180 nF FILT RIP FILT R 43 kΩ 3.3 kΩ FILT C 1 RIP Figure 1. Recommended Connection Diagram CS4226 21 ANALOG AOUT1 FILTER 22 ANALOG AOUT2 FILTER 23 ANALOG AOUT3 FILTER 24 ANALOG AOUT4 FILTER 25 ANALOG AOUT5 FILTER 26 ANALOG AOUT6 ...
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... CMOUT voltage µF DC blocking ca- pacitor placed in series with the input pins al- lows signals centered around input to the CS4226. Figure 2 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2 Vrms to 1 Vrms. The CMOUT refer- ence level is used to bias the op-amps to ap- proximately one half the supply voltage ...
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... High Pass Filter The operational amplifiers in the input circuitry driving the CS4226 may generate a small DC offset into the A/D converter. The CS4226 in- cludes a high pass filter after the decimator to remove any DC offset which could result in re- cording a DC level, possibly yielding “clicks” ...
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... PLL as the clock source, all DACs will instantly mute when the PLL detects an error. 2.4 Clock Generation _ The master clock to operate the CS4226 may + be generated by using the on-chip inverter and Example Op-Amps an external crystal, by using the on-chip PLL, are or by using an external clock source ...
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... DCK1/0 bits in the DSP Port Mode Byte. The Left/Right clock (LRCK) is used to indicate left and right data and the start of a new sam- ple period. It may be output from the CS4226 may be generated from an external CS4226 DS188F4 ...
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... ADC channels are com- bined onto a single output. Format 6 is avail- able in Master Mode only. See figure 6 for details. Left LSB MSB LSB M SCLKs Left MSB LSB MSB Left MSB LSB MSB CS4226 Right MSB LSB M SCLKs Right LSB MSB Right LSB 15 ...
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... SDOUT2 SDOUT1 20 clks 20 clks 128 SCLKS MSB LSB MSB LSB DAC #3 DAC #5 32 clks 32 clks SDOUT2 32 clks Figure 6. One data line modes CS4226 Right MSB LSB M SCLKs Right LSB MSB Right MSB LSB 64 SCLKS MSB LSB MSB LSB MSB DAC #4 ...
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... DSP port in multi-data line mode. LRCKAUX is used to indicate left and right data samples, and the start of a new sample period. SCLKAUX and LRCKAUX may be output from the CS4226, or they may be generated from an external source, as set by the AMS1/0 con- trol bits in the Auxiliary Port Mode Byte. 2.5.5 ...
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... The state of this pin is continuously monitored. 2.6.1 SPI Mode In SPI mode the CS4226 chip select sig- nal, CCLK is the control port bit clock, (input into the CS4226 from the microcontroller), CDIN is the input data line from the microcon- troller, CDOUT is the output data line to the mi- ...
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... To communicate with a CS4226, the LSBs of the chip address field, which is the first byte sent to the CS4226, should match the set- tings of the AD1, AD0 pins. The eighth bit of the address bit is the R/W bit (high for a read, low for a write) ...
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... The CS4226 can be re-calibrated whenever desired. A control bit, CAL, in the Converter Control Byte, is provided to initiate a calibra- tion. The sequence is: 1) Set CAL to 1, the CS4226 sets CALP to 1 and begins to calibrate. 2) CALP will when the calibration is completed. Additional calibrations can be implemented by setting CAL to 0 and then to 1 ...
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... F1 Figure 9. De-emphasis Curve 2.10 HOLD Function If the digital audio source presents invalid data to the CS4226, the CS4226 may be configured to cause the last valid digital input sample to be held constant. Holding the previous output sample occurs when the user asserts the HOLD pin (HOLD=1) at any time during the ...
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... Rules for Data Converters and Other Mixed Signal Devices, and the CDB4226 evaluation board data sheet for recommended layout of the decoupling components. The CS4226 will mute the analog outputs and enter the Power Down Mode if the supply drops below approximately 4V ...
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... Figure 14. DAC Passband Ripple DS188F4 0.02 0.01 dB 0.00 -0.01 -0.02 0.0 0.6 0.7 0.8 0.9 1.0 Figure 11. 20-bit ADC Passband Ripple 0 -10 -20 -30 -40 -50 -60 dB -70 -80 -90 -100 -110 -120 -130 -140 0.6 0.65 0.70 0.0 0.1 Figure 13. DAC Frequency Response 0 -10 -20 -30 -40 -50 dB -60 -70 -80 -90 -100 -110 -120 0.40 0.3 0.4 0.5 Figure 15. DAC Transition Band CS4226 0.1 0.2 0.3 0.4 Normalized Frequency (Fs) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Frequency (Fs) 0.45 0.50 0.55 0.6 0.65 Normalized Frequency (Fs) 0.5 0.9 1.0 0.70 23 ...
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... PLL will not resynchronize to the new sample rate. You must either change input pins or change the Clock Mode Byte to something else and then change it back to the correct value. This will cause the PLL to resync MAP4 MAP3 CI1 CI0 CS4226 MAP2 MAP1 MAP0 CS2 CS1 CS0 DS188F4 ...
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... ZCD Zero crossing disable 0 - DAC mutes and volume control changes occur on zero-crossings DAC mutes and volume control changes occur immediately. This register defaults to 3Fh. DS188F4 AUTO MUT5 MUT4 CS4226 CAL MUT3 MUT2 MUT1 25 ...
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... Auxiliary Digital Input Port or S/PDIF Receiver to SDOUT1, Stereo ADC output to SDOUT2 3 - Not used. This register defaults to 00h ATT4 ATT3 ACC5 ACC4 AIS1 AIS0 CS4226 ATT2 ATT1 ATT0 ACC3 ACC2 ACC1 MUTM MUTR MUTL DS188F4 ...
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... These bits are 'sticky'. They constantly monitor the ADC output for the peak levels and hold the max- imum output. They are reset to 0 when read. This register is read only. DS188F4 GNR1 LVR1 LVR0 CS4226 GNR0 GNL1 GNL0 LVL2 LVL2 LVL0 27 ...
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... DCK1-DCK0 * Set number of bit clocks per Fs period 0 - 128 Master Burst or Slave mode only All formats will default to 16 bits This register defaults to 00h. * DCK1-DCK0 are ignored in formats 5 and DMS0 DSCK CS4226 DDF2 DDF1 DDF0 DS188F4 ...
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... Master Non-Burst - SCLKAUXs are evenly distributed in LRCKAUX frame 3 - Not used - default to slave ACK1-ACK0 Set number of bit clocks per Fs period 128 Master Burst or Slave mode only All input formats will default to 16 bits This register defaults to 00h. DS188F4 AMS0 ASCK CS4226 ADF2 ADF1 ADF0 29 ...
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... HOLD/RUBIT Pin Control 0 - HOLD/RUBIT is an input (HOLD HOLD/RUBIT is an output (RUBIT) CSP Channel Status output to pins Analog inputs to pins. AIN2R, AIN2L, AIN3R, AIN3L 1 - Channel status to pins. (This forces AIS1/0=0) This register defaults to 00h MOH DEM24 CS4226 DEM2 DEM1 DEM0 DS188F4 ...
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... Byte 18h Channel B Status Byte 3 Byte 19h Channel B Status Byte 4 Bit definition changes depending upon PRO bit setting. When these bits are updating and may be invalid. DS188F4 LOCK CS4 CS3 CS4226 CONF BIP PAR CS2 CS1 CS0 31 ...
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... LRCK SDOUT1 SDOUT2 SDIN1 SDIN2 SDIN3 1 33 CLKOUT 2 32 OVL/ERR XTO 5 29 top XTI 6 28 view 7 27 DEM 8 26 AOUT6 AOUT5 11 23 AOUT4 AOUT3 AOUT2 AOUT1 AGND2 VA+ AGND1 FILT CS4226 DS188F4 ...
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... AGND. Digital Audio Interface Signals SDIN1 - Serial Data Input 1, PIN 34. Digital audio data for the DACs 1 and 2 is presented to the CS4226 on this pin. This pin is also used for one-line data input modes. SDIN2 - Serial Data Input 2, PIN 33. Digital audio data for the DACs 3 and 4 is presented to the CS4226 on this pin. ...
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... When the S/PDIF receiver is chosen as the clock source ( and HPC = 1), then this pin outputs the received user bit. When HPC = 0, this pin is sampled on the active edge of SCLKAUX high any time during the frame, DATAUX data is ignored and the previous “good” sample is output to the serial output port. 34 CS4226 DS188F4 ...
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... PDN - Powerdown Pin, PIN 8. When low, the CS4226 enters a low power mode and all internal states are reset, including the control port. When high, the control port becomes operational and the RS bit must be cleared before normal operation will occur. ...
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... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts. 36 CS4226 DS188F4 ...
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... DIM ∝ DS188F4 ∝ L INCHES MIN MAX 0.000 0.065 0.002 0.006 0.012 0.018 0.478 0.502 0.404 0.412 0.478 0.502 0.404 0.412 0.029 0.037 0.018 0.030 0.000 7.000 JEDEC #: MS-026 CS4226 A A1 MILLIMETERS MIN MAX 0.00 1.60 0.05 0.15 0.30 0.45 11.70 12.30 9.90 10.10 11.70 12.30 9.90 10.10 0.70 0.90 0.45 0.75 0.00 7.00 37 ...