CS4227-KQ Cirrus Logic, Inc., CS4227-KQ Datasheet

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CS4227-KQ

Manufacturer Part Number
CS4227-KQ
Description
Six channel, 20-bit codec
Manufacturer
Cirrus Logic, Inc.
Datasheet

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CS4227-KQ
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CRYSTAL
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Part Number:
CS4227-KQ
Manufacturer:
CRYSTAL
Quantity:
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Features
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Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Stereo 20-bit A/D Converters
Six 20-bit D/A Converters
108 dB DAC Signal-to-Noise Ratio (EIAJ)
Mono 20-bit A/D Converter
Programmable Input Gain & Output
Attenuation
On-chip Anti-aliasing and Output Smoothing
Filters
De-emphasis for 32 kHz, 44.1 kHz, 48 kHz
I
SDOUT1
SDOUT2
SDIN1
SDIN2
SDIN3
LRCK
SCLK
DEM
PDN
OVL
CLKOUT XTI
SCL/CCLK
DEM
Six Channel, 20-Bit Codec
Clock Osc/
Divider
SDA/CDOUT
MUX
XTO
Control Port
AD1/CDIN AD0/CS SPI/I
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
HOLD
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
Right
Mono
ADC
ADC
Left
ADC
DATAUX
Copyright
Description
The CS4227 is a single-chip codec providing stereo an-
alog-to-digital and six digital-to-analog converters using
delta-sigma conversion techniques. This +5 V device
also contains volume controls that are independently se-
lectable for each of the six D/A channels. Applications
include Dolby
3™ home theater systems, DSP based car audio sys-
tems, and other multi-channel applications.
ORDERING INFORMATION
Auxiliary Input
LRCKAUX
(All Rights Reserved)
Volume
Volume
Volume
Volume
Volume
Volume
Control
Control
Control
Control
Control
Control
CS4227-KQ
CS4227-BQ
CDB4227
2
C
Cirrus Logic, Inc. 1999
VD+
SCLKAUX
®
Pro-logic™, THX
VA+
-10° to +70° C 44-pin TQFP
-40° to +85° C 44-pin TQFP
Reference
Voltage
DGND1
DGND2
®
, and Dolby Digital AC-
CS4227
Evaluation Board
AOUT5
AOUT6
CMOUT
AOUT1
AOUT2
AOUT3
AOUT4
AINAUX
AIN1L
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AGND1
AGND2
DS281PP2
SEP ‘99
1

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CS4227-KQ Summary of contents

Page 1

... This +5 V device also contains volume controls that are independently se- lectable for each of the six D/A channels. Applications include Dolby 3™ home theater systems, DSP based car audio sys- tems, and other multi-channel applications. ORDERING INFORMATION CS4227-KQ CS4227-BQ CDB4227 2 AD1/CDIN AD0/CS SPI/I C Control Port ...

Page 2

... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4227 DS281PP2 ...

Page 3

... Figure 16. 20-bit ADC Passband Ripple ....................................................................................... 21 Figure 17. 20-bit ADC Transition Band ......................................................................................... 21 Figure 18. DAC Frequency Response .......................................................................................... 21 Figure 19. DAC Passband Ripple ................................................................................................. 21 Figure 20. DAC Transition Band ................................................................................................... 21 LIST OF TABLES Table 1. Single-ended vs Differential Input Pin Assignments .............................................................. 12 Table 2. High Pass Filter Characteristics ............................................................................................ 13 Table 3. DSP Serial Input Ports........................................................................................................... 15 DS281PP2 2 ® C Mode................................................................................... 18 CS4227 3 ...

Page 4

... The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 5.6448 MHz ±20.0 kHz where n = 0,1,2,3...). 5. Group delay for Fs = 44.1 kHz °C; VA+, VD Full Scale Input Sine wave, 997 kHz; A CS4227-KQ Symbol Min 16 Mono channel 16 THD 92 ...

Page 5

... THD - (Stereo) THD 0.7 - Resistance: 10 Capacitance (Notes (Note 7) - (Notes 6 ,7) 24.1 (Note 8) 70 (Note 5) tgd - - Operating - Power Down - (1 kHz rms CS4227-KQ CS4227-BQ Typ Max Min Typ 3 3 108 - 99 106 0.003 - - 0.003 -88 -83 - -86 90 ...

Page 6

... Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge. Jitter is greater for 384x Fs and 512x Fs as selected output frequency. 10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section. 11. After powering up the CS4227, PDN should be held low for allow the power supply to settle. 1 12. ...

Page 7

... SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively. Figure 2. Audio Ports Slave Mode and Data I/O Timing DS281PP2 SCLK* SCLKAUX* (output) LRCK LRCKAUX (output) SDOUT1 SDOUT2 Figure 1. Audio Ports Master Mode Timing lrckd lrcks sckh SDIN1 SDIN2 SDIN3 lrpd ds dh MSB CS4227 t mslr t sckl t sckw t dpd MSB-1 7 ...

Page 8

... CS t css t scl t sch CCLK CDIN t dsu CDOUT Figure 3. Control Port SPI Mode CS4227 ( °C; VA+, VD ±5%; A Min Max Unit - 6 MHz 1.0 - µ ...

Page 9

... Repeated Start t high t t hdst sud t sust low hdd 2 Figure 4. Control Port I C Mode CS4227 ( °C; VA+, VD ±5%; A Min Max - 100 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - Stop susp hdst ...

Page 10

... DGND = 0 V, all voltage with respect to Symbol Digital VD+ Analog VA °C; VA+, VD ±5%) A Symbol (Except XTI (Except XTI (Except XTO) V (VD+) - 1.0 OH (Except XTO (Digital Inputs) CS4227 Min Max Unit -0.3 6.0 V -0.3 6.0 - ±10 mA -0.7 (VA+) + 0.7 V -0.7 (VD+) + 0.7 V -55 +125 °C -65 +150 °C Min Typ ...

Page 11

... AIN3L 9 * AIN3R 15 * AINAUX 27 DEM 2 HOLD 1 DATAUX 44 LRCKAUX 43 SCLKAUX 8 PDN 7 SPI/I2C AGND1, 2 DGND1 Figure 5. Recommended Connection Diagram CS4227 21 ANALOG AOUT1 FILTER 22 ANALOG AOUT2 FILTER 23 ANALOG AOUT3 FILTER 24 ANALOG AOUT4 FILTER 25 ANALOG AOUT5 FILTER 26 ANALOG AOUT6 FILTER 3 SCL/CCLK 4 SDA/CDOUT 6 AD0/CS ...

Page 12

... FUNCTIONAL DESCRIPTION 2.1 Overview The CS4227 has 2 channels of 20-bit analog-to- digital conversion and 6 channels of 20-bit digital- to-analog conversion. A mono 20-bit ADC is also provided. All ADCs and DACs are delta-sigma converters. The stereo ADC inputs have adjustable input gain, while the DAC outputs have adjustable output attenuation ...

Page 13

... High Pass Filter The operational amplifiers in the input circuitry driving the CS4227 may generate a small DC offset into the A/D converter. The CS4227 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC lev- el, possibly yielding " ...

Page 14

... Each output can be independently muted via mute control bits, MUT6-1, in the DAC Control Byte (#3). The mute also takes effect on a zero-crossing or after a timeout. In addition, the CS4227 has an optional mute on consecutive zeros feature, where all DAC outputs will mute if they receive between 512 and 1024 consecutive zeros (or -1 code) on all six channels ...

Page 15

... The active edge of SCLK is chosen by setting the DSCK bit in the DSP Port Mode Byte (#14). SCLK can be generat the CS4227 (master mode can be input from an external SCLK source (slave mode). Mode selection is set with the DMS1/0 bits in the DSP Port Mode Byte (#14) ...

Page 16

... MSB LSB 64 SCLKS LSB MSB LSB MSB LSB DAC #2 DAC #4 DAC #6 20 clks 20 clks 20 clks SDOUT2 20 clks 20 clks 128 SCLKS MSB LSB MSB LSB DAC #4 DAC #2 32 clks 32 clks SDOUT1 SDOUT2 32 clks 32 clks CS4227 MSB MSB LSB DAC #6 32 clks DS281PP2 ...

Page 17

... The control port has 2 modes: SPI and I the CS4227 as a slave device. The SPI mode is se- lected by setting the SPI/I2C pin low, and I selected by setting the SPI/I2C pin high. The state of this pin is continuously monitored ...

Page 18

... RS bit, the CE bit (Clock Enable) in the Clock Mode Byte (#1) should also be set to zero. The CS4227 will also enter a stand by mode if the master clock source stops for approximately 10 µ the LRCK is not synchronous to the master clock. The control port will retain its current set- tings ...

Page 19

... The CS4227 can be re-calibrated whenever de- sired. A control bit, CAL, in the Converter Control Byte, is provided to initiate a calibration. The se- quence is: 1) Set CAL to 1, the CS4227 sets CALP to 1 and begins to calibrate. 2) CALP will when the calibration is com- pleted. Additional calibrations can be implemented by set- ting CAL to 0 and then to 1 ...

Page 20

... The CS4227 will mute the analog outputs and enter the Power Down Mode if the supply drops below approximately 4 volts. 2.12 ADC and DAC Filter Response Plots Figures 15 through 20 show the overall frequency response, passband ripple and transition band for the CS4227 ADC’s and DAC’s. ...

Page 21

... Figure 15. 20-bit ADC Filter Response Figure 17. 20-bit ADC Transition Band Figure 19. DAC Passband Ripple DS281PP2 Figure 16. 20-bit ADC Passband Ripple Figure 18. DAC Frequency Response Figure 20. DAC Transition Band CS4227 21 ...

Page 22

... Determines frequency of XTI 0 - 256 384 512 not used CO1-CO0 Sets CLKOUT frequency 0 - 256 384 512 This register defaults to 01h MAP4 MAP3 CO0 CI1 CI0 CS4227 MAP2 MAP1 MAP0 DS281PP2 ...

Page 23

... ZCD Zero crossing disable 0 - DAC mutes and volume control changes occur on zero-crossings 1 - DAC mutes and volume control changes occur immediately. This register defaults to 3Fh. DS281PP2 MUT6 MUT5 MUT4 CS4227 CAL MUT3 MUT2 MUT1 23 ...

Page 24

... Auxiliary Digital Input Port to SDOUT1, Stereo ADC output to SDOUT2 3 - Not used. This register defaults to 00h ATT5 ATT4 ATT3 ACC6 ACC5 ACC4 AIS1 AIS0 CS4227 ATT2 ATT1 ATT0 ACC3 ACC2 ACC1 MUTM MUTR MUTL DS281PP2 ...

Page 25

... These bits are ’sticky’. They constantly monitor the ADC output for the peak levels and hold the max- imum output. They are reset to 0 when read. This register is read only. DS281PP2 GNR1 LVR2 LVR1 LVR0 CS4227 GNR0 GNL1 GNL0 LVL2 LVL1 LVL0 25 ...

Page 26

... DCK1-DCK0* Set number of bit clocks per Fs period 0 - 128 Master Burst or Slave mode only All formats will default to 16 bits This register defaults to 00h. * Ignored in data formats 5 and DMS1 DMS0 DSCK CS4227 DDF2 DDF1 DDF0 DS281PP2 ...

Page 27

... Not used - default to slave ACK1-ACK0 Set number of bit clocks per Fs period 128 Master Burst or Slave mode only All input formats will default to 16 bits This register defaults to 00h. DS281PP2 AMS1 AMS0 ASCK CS4227 ADF2 ADF1 ADF0 27 ...

Page 28

... Extended Hold (16 frames) mutes DAC outputs 1 - DACs not muted UMV Unmute on Valid Data 0 - DACs unmute when HOLD is removed 1 - DACs must be unmuted in DAC control byte after HOLD is removed. This register defaults to 00h UMV MOH 0 CS4227 DEM2 DEM1 DEM0 DS281PP2 ...

Page 29

... Analog grounds. VD+ - Digital Power Input + 5 V digital supply. DGND1, DGND2 - Digital Ground Digital grounds. DS281PP2 CS4227- 44-pin TQFP Top View CS4227 ...

Page 30

... AGND. Digital Audio Interface Signals SDIN1 - Serial Data Input 1 Digital audio data for the DACs 1 and 2 is presented to the CS4227 on this pin. This pin is also used for one-line data input modes. SDIN2 - Serial Data Input 2 Digital audio data for the DACs 3 and 4 is presented to the CS4227 on this pin. ...

Page 31

... AD1 is a chip address bit. In SPI software control mode, CDIN is the input data line for the control port interface. SDA/CDOUT - Serial Control Data Out 2 ® mode, SDA is the control data I/O line. In SPI software control mode, CDOUT is the output data from the control port interface on the CS4227. DS281PP2 CS4227 31 ...

Page 32

... Miscellaneous Pins PDN - Powerdown Pin When low, the CS4227 enters a low power mode and all internal states are reset, including the control port. When high, the control port becomes operational and the RS bit must be cleared before normal operation will occur. ...

Page 33

... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts. DS281PP2 CS4227 33 ...

Page 34

... INCHES MIN MAX 0.000 0.065 0.002 0.006 0.012 0.018 0.478 0.502 0.404 0.412 0.478 0.502 0.404 0.412 0.029 0.037 0.018 0.030 0.000 7.000 TYP MAX .001 .004 JEDEC # : MS-026 CS4227 A A1 MILLIMETERS MIN MAX 0.00 1.60 0.05 0.15 0.30 0.45 11.70 12.30 9.90 10.10 11.70 12.30 9.90 10.10 0.70 0.90 0.45 0.75 0.00 7.00 TYP MAX .025 .10 DS281PP2 ...

Page 35

Notes • ...

Page 36

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