S1D13806 EPSON Electronics, S1D13806 Datasheet
S1D13806
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S1D13806 Summary of contents
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... S1D13806 Embedded Memory Display Controller Hardware Functional Specification Document Number: X28B-A-001-12 Copyright © 2001, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13806 X28B-A-001-12 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/04/10 ...
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... Motorola MC68K Bus 2 Interface Timing (e.g. MC68030 6.3.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire 6.3.8 PC Card Timing (e.g. StrongARM 6.3.9 Philips Interface Timing (e.g. PR31500/PR31700 6.3.10 Toshiba Interface Timing (e.g. TX39xx 6.4 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.4.1 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Hardware Functional Specification Issue Date: 02/04/10 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . 34 Page 3 S1D13806 X28B-A-001-12 ...
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... Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.2.1 MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.2 LCD PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.3 CRT/TV PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.4 MediaPlug Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.4 Clocks vs. Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.1 Initializing the S1D13806 . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.1.1 Register Memory Select Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.1.2 SDRAM Initialization Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.2 Register Mapping 8.3 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.4.1 Basic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.4.2 General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8.4.3 Configuration Readback Register . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8 ...
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... Luminance Filter (REG[05Bh] bit .166 13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1 166 13.4 TV Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.4.1 TV Image Display and Positioning . . . . . . . . . . . . . . . . . . . . . . . . . .170 13.4.2 TV Cursor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 14 Ink Layer/Hardware Cursor Architecture . . . . . . . . . . . . . . . . . . . . . . . 173 14.1 Ink Layer/Hardware Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . 173 14.2 Ink/Cursor Data Format Hardware Functional Specification Issue Date: 02/04/ 150 . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Page 5 S1D13806 X28B-A-001-12 ...
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... Frame Rates for LCD and CRT (1024x768) with EISD Enabled . . . . . . . . . . .199 18.2.7 Frame Rates for LCD and NTSC TV with EISD Enabled . . . . . . . . . . . . . .200 18.2.8 Frame Rates for LCD and PAL TV with EISD Enabled . . . . . . . . . . . . . . .201 S1D13806 X28B-A-001-12 Epson Research and Development Vancouver Design Center ...
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... Epson Research and Development Vancouver Design Center 19 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 19.2 Power Save Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 19.3 Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . 203 20 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 22 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Hardware Functional Specification Issue Date: 02/04/10 Page 7 S1D13806 X28B-A-001-12 ...
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... Page 8 S1D13806 X28B-A-001-12 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/04/10 ...
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... Epson Research and Development Vancouver Design Center Table 2-1 : S1D13806 Features Table 4-1: PFBGA 220-pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4-2 : Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4-3 : LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 4-4 : MediaPlug Pin Description Table 4-5 : CRT Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 4-6 : General Purpose IO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 4-7 : Configuration Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 4-8 : Miscellaneous Interface Pin Descriptions ...
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... Table 6-31: MediaPlug A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 7-1 : Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 7-2: Clocks vs. Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 8-1 : Register Mapping with CS and M/ Table 8-2 : S1D13806 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 8-3 : Media Plug/GPIO12 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Table 8-4 : MCLK Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Table 8-5 : LCD PCLK Divide Selection .104 Table 8-6 : LCD PCLK Source Selection .105 Table 8-7 : CRT/TV PCLK Divide Selection ...
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... Table 8-38: Cable Detect and Remote Powered Status .151 Table 8-39: MediaPlug CMD Read/Write Descriptions . . . . . . . . . . . . . . . . . . . . . . . .153 Table 8-40: MediaPlug Commands .154 Table 10-1 : S1D13806 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Table 13-1 : Required Clock Frequencies for NTSC/PAL . . . . . . . . . . . . . . . . . . . . . . .165 Table 13-2 : NTSC/PAL SVideo-Y (Luminance) Output Levels . . . . . . . . . . . . . . . . . . .167 Table 13-3 : NTSC/PAL SVideo-C (Chrominance) Output Levels . . . . . . . . . . . . . . . . . . 168 Table 13-4 : NTSC/PAL Composite Output Levels ...
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... Page 12 S1D13806 X28B-A-001-12 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/04/10 ...
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... Figure 6-21: Single Color 8-Bit Panel A.C. Timing (Format Figure 6-22: Single Color 8-Bit Panel Timing (Format Figure 6-23: Single Color 8-Bit Panel A.C. Timing (Format Figure 6-24: Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Hardware Functional Specification Issue Date: 02/04/10 List of Figures Page 13 S1D13806 X28B-A-001-12 ...
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... Figure 14-3: Clipped Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 15-1: Relationship Between Screen Image and 90° Rotated Image in the Display Buffer . . . 178 Figure 20-1: Mechanical Drawing 144-pin QFP20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 20-2: Mechanical Drawing 220-pin PFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . 205 S1D13806 X28B-A-001-12 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
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... Products requiring digital camera input can take advantage of the directly supported WINNOV Videum® Cam digital interface. While focusing on devices targeted by the Microsoft Windows CE Operating System, the S1D13806’s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. Hardware Functional Specification ...
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... TFT/D-TFD. Direct support for CRT. Direct support for S-Video/Composite TV output (NTSC or PAL format). S1D13806 X28B-A-001-12 Table 2-1 : S1D13806 Features S1D13806 Features Display Modes 4/8/16 bit-per-pixel (bpp) color depths 64K colors on TFT,CRT and TV 64K colors in 16 bpp mode on color passive LCD panels using dithering (4096 colors in 4/8 bpp) ...
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... FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx RED,GREEN,BLUE HRTC HRTC CRT VRTC VRTC IREF IREF 8-bit Single FPDAT[7:0] D[7:0] LCD FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx GREEN Composite Video Composite TV IREF IREF S1D13806 X28B-A-001-12 ...
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... X28B-A-001-12 . Oscillator Oscillator VDD A0 M/R# CS# AB[20:1] DB[15:0] WE1# S1D13806 BS# RD/WR# RD# WE0# WAIT# BUSCLK RESET# . Oscillator Oscillator M/R# CS# AB[20:1] DB[15:0] S1D13806 AB0 WE1# BS# RD/WR# WAIT# BUSCLK RESET# Epson Research and Development Vancouver Design Center Oscillator FPDAT[7:4] UD[3:0] FPDAT[3:0] LD[3:0] FPSHIFT FPSHIFT FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx RED,GREEN,BLUE RED,GREEN,BLUE ...
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... FPDAT[15:0] D[15:0] LCD FPSHIFT FPSHIFT Panel FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx RED,GREEN,BLUE HRTC HRTC CRT VRTC VRTC IREF IREF 12-bit TFT FPDAT[11:0] D[11:0] Display FPSHIFT FPSHIFT FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx Composite Video Composite TV IREF IREF S1D13806 X28B-A-001-12 ...
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... Oscillator Oscillator VDD BS# RD/WR# M/R# CS# AB[20:0] DB[15:0] S1D13806 WE0# WE1# RD# WAIT# BUSCLK RESET# . Oscillator Oscillator BS# A0 M/R# CS# AB[20:1] DB[15:0] S1D13806 WE0# WE1# RD# RD/WR# WAIT# RESET# BUSCLK Epson Research and Development Vancouver Design Center Oscillator FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx RED,GREEN,BLUE RED,GREEN,BLUE HRTC ...
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... FPLINE DRDY MOD GPIOx RED,GREEN,BLUE RED,GREEN,BLUE HRTC HRTC VRTC VRTC IREF IREF Oscillator FPDAT[11:0] D[11:0] FPSHIFT FPSHIFT FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPIOx RED,GREEN,BLUE Composite Video Composite TV IREF IREF X28B-A-001-12 Page 21 16-bit Dual LCD Panel CRT 12-bit TFT Panel S1D13806 ...
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... Figure 4-1: Pinout Diagram 144-Pin QFP20 Surface Mount Packages S1D13806 X28B-A-001- S1D13806 Epson Research and Development Vancouver Design Center ...
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... FPDAT22 FPDAT19 HRTC BLUE AVDD NC NC VRTC AVSS GREEN AVSS NC VSS NC NC IREF AVDD Page FPFRAME NC NC FPSHIFT VSS FPDAT1 NC FPDAT4 NC PFDAT7 COREVDD NC IOVDD FPDAT11 FPDAT13 FPDAT14 VSS NC NC FPDAT23 S1D13806 X28B-A-001-12 ...
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... H3, H2, H4, H1, AB[12:1] I 14-25 H5, J3, J1, J4, K2, J5, K1, L2 S1D13806 X28B-A-001-12 Table 4-2 : Host Interface Pin Descriptions RESET# Cell State • For Generic Bus, this pin must be connected to V • For SH-4/SH-3 Bus, this pin must be connected to V • For MC68K Bus 1, this pin inputs the lower data strobe (LDS#). ...
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... For PowerPC Bus, this pin inputs the system address bit 11 (A11). • For all other busses, this pin inputs the system address bit 20 (A20). See Table 4-10, “CPU Interface Pin Mapping,” on page 34 for summary. See the respective AC Timing diagram for detailed functionality. Page 25 Description . DD S1D13806 X28B-A-001- ...
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... For all other busses, this input pin is used to select between the C Hi-Z display buffer and register address spaces of the S1D13806. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping . See Table 4-10, “CPU Interface Pin Mapping,” on page 34. ...
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... This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13806 needs this signal for early decode of the bus cycle. • For MC68K Bus 1, this pin inputs the read write signal (R/W#). • For MC68K Bus 2, this pin inputs the read write signal (R/W#). ...
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... WE0 RESET S1D13806 X28B-A-001-12 RESET# Cell State This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read signal (RD#). • For MC68K Bus 1, this pin is connected to V • For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1). ...
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... For PowerPC Bus, this pin outputs the transfer acknowledge signal (TA#). • For PC Card (PCMCIA) Bus, this pin outputs the wait signal (WAIT#). See Table 4-10, “CPU Interface Pin Mapping,” on page 34 for summary. See the respective AC Timing diagram for detailed functionality. Page 29 Description S1D13806 X28B-A-001-12 ...
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... D8, A8, C8, VMP[5:2] IO 129-126 VMP[1] O 125 VMP[0] O 124 S1D13806 X28B-A-001-12 Table 4-3 : LCD Interface Pin Descriptions RESET# Cell Pin # State Panel data bus. Not all pins are used for some panels - see Table CO2 0 4-10, “CPU Interface Pin Mapping,” on page 34 for details. Unused pins are driven low ...
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... Table 4-6 : General Purpose IO Pin Descriptions PFBGA RESET# Cell Pin # State Bi-directional GPIO pin. D7 C/TS2 1 or Hi-Z When the MediaPlug interface is enabled, GPIO12 is configured as the MediaPlug output pin VMPEPWR. N9, R11, C/TS2 Hi-Z Bi-directional GPIO pin. T14 Page 31 Description Description S1D13806 X28B-A-001-12 ...
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... Table 4-7 : Configuration Pin Descriptions PFBGA RESET# Cell Pin # State Input Configuration pin. C Hi-Z State of pins are latched at RESET# to configure S1D13806 -- Table D3, F5 4.3, “Summary of Configuration Options,” on page 33 for details. Table 4-8 : Miscellaneous Interface Pin Descriptions PFBGA RESET# Cell Pin # State Input clock for the internal pixel clock (PCLK), memory clock ...
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... SH4; Big Endian; Active High WAIT# with tristate 1 1 Reserved BUSCLK input not divided Configure GPIO12 for normal use and disables MediaPlug functionality. Page 33 (1/0) 0 note note note note note note note note note note note note note note note S1D13806 X28B-A-001-12 ...
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... AB0 is not used internally for these busses and must be connected to either For further information on interfacing the S1D13806 to the PC Card bus, see Interfac- ing to the PC Card Bus, document number X28B-G-005-xx. S1D13806 X28B-A-001-12 Table 4-10 : CPU Interface Pin Mapping Motorola ...
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... G01 G02 G00 G01 B02 B03 B01 B02 B00 B01 driven 0 R00 R12 R13 driven 0 G00 G12 G13 G11 G12 driven 0 B00 B12 B13 B11 B12 R11 R12 R10 R11 driven 0 R10 G10 G11 driven 0 G10 B10 B11 driven 0 B10 S1D13806 ...
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... IREF 150 1% DAC V DAC Figure 4-3: External Circuitry for CRT Interface Note Example implementation only, individual characteristics of components may affect actual IREF current. S1D13806 X28B-A-001-12 CRT/TV CRT Only (REG[05Bh] bit 3 =1) DAC 1.5k 1% 9.2 mA 4.6 mA 2N2222 2N2222 69.8 1k 140 ...
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... -65 to 150 260 for 10 sec. max at lead Condition -40 Rating Units Min Typ Max 3.3 3.6 V 3.3 3.6 V 3.3 3.6 V 3.3 3 X28B-A-001-12 Page 37 Units C S1D13806 ...
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... Low Level Input Voltage T- V Hysteresis Voltage H1 R Pull-Down Resistance PD R Pull-Up Resistance PU C Input Pin Capacitance I C Output Pin Capacitance O C Bi-Directional Pin Capacitance IO S1D13806 X28B-A-001-12 Condition Min Quiescent Conditions — -1 — -1 VDD = min I = -2mA (Type1 0 -6mA (Type2) VDD = min I ...
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... Hardware Functional Specification Issue Date: 02/04/10 = 3.3V ± 10% (IO and Core) DD for all inputs must be < (10% ~ 90%) fall t t PWH PWL OSC Figure 6-1: Clock Input Requirement Parameter Page 39 Min Max Units Note MHz 1/f ns OSC S1D13806 X28B-A-001-12 ...
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... Note For PCLK source selection see Section 7.3, “Clock Selection” on page 94. Note For maximum internal clock frequency values see Table 6-4:, “Internal Clock Require- ments,” on page 41. S1D13806 X28B-A-001-12 Parameter when Source Divided Parameter Epson Research and Development Vancouver Design Center ...
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... Epson Research and Development Vancouver Design Center 6.2 Internal Clocks This section provides the minimum and maximum required frequencies of the internal clocks used by the S1D13806. For detailed information on the internal clocks, refer to Section 7, “Clocks” on page 92. Symbol f Memory Clock Frequency MCLK f LCD Pixel Clock Frequency ...
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... WE0#, WE1# WAIT# D[15:0](write) D[15:0](read) Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note WAIT# is always driven when CONF6 =1. S1D13806 X28B-A-001- t11 Figure 6-2: Generic Interface Timing Epson Research and Development Vancouver Design Center ...
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... D[15:0] setup to rising edge WAIT# (read cycle) t13 Rising edge of RD0#, RD1# to D[15:0] tri-state (read cycle) Hardware Functional Specification Issue Date: 02/04/10 Table 6-5 : Generic Interface Timing Parameter Page 43 Min Max Units 50 MHz 1/f ns CLK S1D13806 X28B-A-001-12 ...
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... BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note The SH-4 Wait State Control Register for the area in which the S1D13806 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). ...
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... Hardware Functional Specification Issue Date: 02/04/10 Table 6-6 : Hitachi SH-4 Interface Timing Parameter CKIO after BS# (write cycle) Page Min Max Units 66 MHz 1/f ns CKIO S1D13806 X28B-A-001-12 ...
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... D[15:0](read) Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note The SH-3 Wait State Control Register for the area in which the S1D13806 resides must be set to a non-zero value. Note WAIT# is always driven when CONF6 =1. S1D13806 ...
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... Table 6-7 : Hitachi SH-3 Interface Timing Parameter CKIO after BS# (write cycle) Page Min Max Units 66 MHz 1/f ns CKIO greater than 33MHz. CKIO S1D13806 X28B-A-001-12 ...
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... MEMW# IOCHRDY SD[15:0](write) SD[15:0](read) Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note IOCHRDY is always driven when CONF6 =1. S1D13806 X28B-A-001- t11 Figure 6-5: MIPS/ISA Interface Timing Epson Research and Development Vancouver Design Center ...
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... SD[15:0] setup to rising edge IOCHRDY# (read cycle) t13 Rising edge of MEMR# toSD[15:0] tri-state (read cycle) Hardware Functional Specification Issue Date: 02/04/10 Table 6-8 : MIPS/ISA Interface Timing Parameter Page 49 Min Max Units 50 MHz 1/f ns BUSCLK S1D13806 X28B-A-001-12 ...
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... D[15:0](write) D[15:0](read) Figure 6-6: Motorola MC68K Bus 1 Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note DTACK# is always driven when CONF6 =1. S1D13806 X28B-A-001- t12 t14 Epson Research and Development Vancouver Design Center ...
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... UDS# and LDS# high to D[15:0] invalid/high impedance (read t16 cycle) t17 AS# high setup to CLK Hardware Functional Specification Issue Date: 02/04/10 Parameter Page 51 Min Max Units 50 MHz 1/f ns CLK S1D13806 X28B-A-001-12 ...
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... DSACK1# D[31:16](write) D[31:16](read) Figure 6-7: Motorola MC68K Bus 2 Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note DSACK1# is always driven when CONF6 =1. S1D13806 X28B-A-001- t12 t14 Epson Research and Development ...
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... DS# high to D[31:16] invalid/high impedance (read cycle) t17 AS# high setup to CLK Hardware Functional Specification Issue Date: 02/04/10 Parameter Page 53 Min Max Units 50 MHz 1/f ns CLK S1D13806 X28B-A-001-12 ...
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... CS# TS# TA# BI# D[0:15](write) D[0:15](read) Figure 6-8: Motorola PowerPC Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note TA# is always driven when CONF6 =1. S1D13806 X28B-A-001- t10 t14 t17 t19 Epson Research and Development ...
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... Output pin loading on DB[15:0], TA#, BI# is 10pF. Hardware Functional Specification Issue Date: 02/04/10 Parameter Page 55 Min Max Units 45 MHz 1/f ns CLKOUT S1D13806 X28B-A-001-12 ...
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... A[20:1] M/R# CE1#, CE2# CS# OE# WE# WAIT# D[15:0](write) D[15:0](read) Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). S1D13806 X28B-A-001- t11 Figure 6-9: PC Card Timing Epson Research and Development Vancouver Design Center t10 ...
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... D[15:0] setup to rising edge WAIT# (read cycle) t13 Rising edge of OE# to D[15:0] tri-state (read cycle) Hardware Functional Specification Issue Date: 02/04/10 Table 6-12: PC Card Timing Parameter Page 57 Min Max Units 50 MHz 1/f ns CLK S1D13806 X28B-A-001-12 ...
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... DCLKOUT ADDR[12: ALE /CARDREG /CARDxCSH /CARDxCSL /CARDIORD /CARDIOWR /WE /RD /CARDxWAIT D[31:16](write) D[31:16](read) Note /CARDxWAIT is always driven when CONF6 =1. S1D13806 X28B-A-001- t11 t13 Figure 6-10: Philips Interface Timing Epson Research and Development Vancouver Design Center t5 t8 t10 t12 t15 ...
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... If BUSCLK exceeds 37.5MHz, it must be divided by 2 using CONF5 (see Table 4-9, “Summary of Power-On/Reset Options,” on page 33). Hardware Functional Specification Issue Date: 02/04/10 Table 6-13 : Philips Interface Timing Parameter Page 59 Min Max Units 75 MHz 1/f ns DCLKOUT S1D13806 X28B-A-001-12 ...
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... DCLKOUT ADDR[12: ALE CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) Note CARDxWAIT* is always driven when CONF6 =1. S1D13806 X28B-A-001- t11 t13 Figure 6-11: Toshiba Interface Timing Epson Research and Development Vancouver Design Center t5 t8 t10 t12 t15 ...
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... If BUSCLK exceeds 37.5MHz, it must be divided by 2 using CONF5 (see Table 4-9, “Summary of Power-On/Reset Options,” on page 33). Hardware Functional Specification Issue Date: 02/04/10 Table 6-14 : Toshiba Interface Timing Parameter Page 61 Min Max Units 75 MHz 1/f ns DCLKOUT S1D13806 X28B-A-001-12 ...
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... DRDY inactive LCD Enable Bit high to FPFRAME, FPLINE, FPSHIFT, FPDATA, t2 DRDY active Note Where T Note The above timing assumes REG[1F0h] bit 4 is set to 1. S1D13806 X28B-A-001-12 t1 Table 6-15 : LCD Panel Power-off/Power-on Parameter is the period of FPLINE. FPLINE Epson Research and Development Vancouver Design Center ...
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... Hardware Functional Specification Issue Date: 02/04/ not allowed not allowed Parameter SDRAM Refresh Period REG[021h] bits 2:0 (MCLKs) 000 76 001 140 010 268 011 524 Page allowed allowed Min Max Units FPLINE note 1 MCLK 1 T FPFRAME 12 MCLK 8 MCLK S1D13806 X28B-A-001-12 ...
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... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6-14: Single Monochrome 4-Bit Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP ...
Page 65
... Min Typ Max Units note 2 Ts (note note note 4 Ts note 5 Ts t10 + note 6 Ts note S1D13806 X28B-A-001-12 Page 65 ...
Page 66
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-16: Single Monochrome 8-Bit Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-1 1-9 ...
Page 67
... Min Typ Max Units note 2 Ts (note note note 4 Ts note 5 Ts t10 + note 6 Ts note S1D13806 X28B-A-001-12 Page 67 ...
Page 68
... Invalid FPDAT5 Invalid FPDAT4 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE1 LINE2 LINE3 LINE4 HDP 1-R1 1-G2 1-B3 1-G1 1-B2 1-R4 ...
Page 69
... Min Typ Max Units note 2 Ts (note note 3 3 note 4 note 5 t10 + 0.5 1 note 6 note 7 0.5 0.5 0.5 0.5 8] S1D13806 X28B-A-001-12 Page ...
Page 70
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-20: Single Color 8-Bit Panel Timing (Format 1) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE1 LINE2 LINE3 LINE4 HDP 1-R1 1-G1 1-G6 ...
Page 71
... Min Typ Max Units note 2 Ts (note note 3 Ts note 4 Ts note note 6 Ts note 7 Ts note S1D13806 X28B-A-001-12 Page 71 ...
Page 72
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-22: Single Color 8-Bit Panel Timing (Format 2) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-B3 1-G6 ...
Page 73
... Min Typ Max Units note 2 Ts (note note 3 3 note 4 note 5 t10 + 2 2 note 6 note S1D13806 X28B-A-001-12 Page ...
Page 74
... Invalid FPDAT0 1-R6 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE1 LINE2 LINE3 LINE4 HDP 1-G6 1-R1 1-B11 1-G12 1-R7 ...
Page 75
... Min Typ Max Units note 2 Ts (note note 3 3 note 4 note 5 t10 + 3 5 note 6 note S1D13806 X28B-A-001-12 Page ...
Page 76
... Example timing for a 640x480 panel Figure 6-26: Dual Monochrome 8-Bit Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 HDP 1-5 ...
Page 77
... Min Typ Max Units note 2 Ts (note note 3 3 note 4 note 5 t10 + 2 4 note 6 note S1D13806 X28B-A-001-12 Page ...
Page 78
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 HDP 1-R1 1-G2 ...
Page 79
... Min Typ Max Units note 2 Ts (note note 3 3 note 4 note 5 t10 + 0.5 1 note 6 note 7 0.5 0.5 0.5 0.5 8] S1D13806 X28B-A-001-12 Page ...
Page 80
... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 HDP 1-G6, 1-R1, ...
Page 81
... Min Typ Max Units note 2 Ts (note note 3 3 note 4 note 5 t10 + 2 2 note 6 note S1D13806 X28B-A-001-12 Page ...
Page 82
... FPSHIFT DRDY R[5:1] G [5:0] B[5:1] Note: DRDY is used to indicate the first pixel Example Timing for 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13806 X28B-A-001-12 VNDP LINE1 Invalid HDP HNDP 1 Invalid 1-1 1-2 Invalid 1-1 1-2 Invalid ...
Page 83
... Hardware Functional Specification Issue Date: 02/04/10 t9 t12 t7 t17 t11 Invalid t26 t21 Invalid Figure 6-33: TFT/D-TFD A.C. Timing t8 t6 t14 t13 t16 639 640 t10 t14 t22 t23 t24 t25 637 639, 640 638 t10 X28B-A-001-12 Page 83 t15 t27 S1D13806 ...
Page 84
... S1D13806 X28B-A-001-12 Table 6-27 : TFT/D-TFD A.C. Timing Parameter 8 + ((REG[034h] bits [4:0 for 4 bpp or 8 bpp color depth for 16 bpp color depth ...
Page 85
... Issue Date: 02/04/10 VNDP VDP LINE1 HDP HNDP 1 1-1 1-2 Figure 6-34: CRT Timing = (REG[057h] bits [1:0], REG[056h] bits [7:0 (REG[058h] bits [6:0 ((REG[050h] bits [6:0 HNDP + HNDP ((REG[052h] bits [5:0 (REG[053h] bits [5:0]) = (REG[053h] bits [5:0]) LINE480 HNDP 2 1-640 8Ts 8Ts 8 + 4Ts for 4/8 bpp 8 + 5Ts for 16 bpp S1D13806 X28B-A-001-12 Page 85 ...
Page 86
... VRTC pulse width low t3 VRTC falling edge to FPLINE falling edge phase difference [((REG[057h] bits 1:0, REG[056h] bits 7: ((REG[058h] bits 6: [((REG[05Ah] bits 2: [((REG[053h] bits 4: S1D13806 X28B-A-001- Figure 6-35: CRT A.C. Timing Table 6-28 : CRT A.C. Timing Parameter 8] Epson Research and Development Vancouver Design Center ...
Page 87
... VNDP 261 262 263 start of field 2 VNDP Start of Vertical Sync Figure 6-36: NTSC Video Timing post-equalizing pulse interval X28B-A-001-12 Page 87 S1D13806 ...
Page 88
... VRTC Start Position = 0 Field 1 TV VRTC Start Position (field 1) Field 2 TV VRTC Start Position (field 2) Field 3 TV VRTC Start Position (field 3) Field 4 TV VRTC Start Position (field 4) S1D13806 X28B-A-001-12 vertical blanking interval = 25 lines 620 621 622 623 624 625 ...
Page 89
... Page 89 Blanking Level Blanking Level Units ns T 4SC T 4SC T 4SC T 4SC T 4SC T 4SC T 4SC T 4SC T 4SC T 4SC T 4SC S1D13806 X28B-A-001-12 ...
Page 90
... PAL = ((REG[059h] bits[6:0]) + 4.5) for field 2 and field 4 Important REG[056], REG[057], and REG[058] must be programmed to satisfy the Frame Period (t5). For NTSC, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0 For PAL, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0 S1D13806 X28B-A-001- Vertical Sync t4 ...
Page 91
... VMPCLK, VMPCLKN are twice the period of the MediaPlug Clock. See Section 7, “Clocks” on page 92. Hardware Functional Specification Issue Date: 02/04/ Figure 6-40: MediaPlug A.C. Timing Table 6-31: MediaPlug A.C. Timing Parameter Page 91 t8 Min Max Units 50 ns 0 1.1 ns 0.4 1.4 ns S1D13806 X28B-A-001-12 ...
Page 92
... Page 92 7 Clocks 7.1 Clock Overview The following diagram provides a logical representation of the S1D13806 internal clocks. CLKI BUSCLK CLKI3 11 Reserved REG[010h] bit 1,0 CLKI2 S1D13806 X28B-A-001- ÷2 00 REG[010h] bit REG[014h] bits 1 REG[018h] bits 1 REG[01Ch] bits 1,0 ...
Page 93
... Epson Research and Development Vancouver Design Center 7.2 Clock Descriptions 7.2.1 MCLK MCLK should be configured as close to its maximum (50MHz) as possible. The S1D13806 contains sophisticated clock management, therefore, very little power is saved by reducing the MCLK frequency. The frequency of MCLK is directly proportional to the bandwidth of the video memory. ...
Page 94
... MCLK 4 Note 1. The CRT/TV pixel clock may be further multiplied by 2 when TV with Flicker Filter is enabled using REG[018h] bit 7. 2. MCLK may be a previously divided down version of CLKI, CLKI3, or BUSCLK. S1D13806 X28B-A-001-12 Table 7-1 : Clock Selection Internal Clocks MCLK LCD PCLK REG[014h] = 00h REG[014h] = 10h — ...
Page 95
... Epson Research and Development Vancouver Design Center 7.4 Clocks vs. Functions The S1D13806 has five clock signals. Not all clock signals must be active for certain functions to be carried out. The following table shows which clocks are required for each function. Function BUSCLK 2 Register read/write ...
Page 96
... SDRAM Initialization Bit To initialize the embedded SDRAM in the S1D13806, this bit must be set minimum of 200 s after reset. This bit must be set to 1 before memory access is performed. S1D13806 ...
Page 97
... Epson Research and Development Vancouver Design Center 8.2 Register Mapping The S1D13806 registers are memory-mapped. When the system decodes the input pins as CS and M/ the registers may be accessed. The register space is decoded by A[20:0]. When A20 = 1 the BitBLT data register ports are decoded allowing the system to access the display buffer through the 2D BitBLT engine using address lines A[19:0] ...
Page 98
... Page 98 8.3 Register Set The S1D13806 register set is as follows. Register REG[000h] Revision Code Register REG[004h] General IO Pins Configuration Register 0 REG[008h] General IO Pins Control Register 0 REG[00Ch] Configuration Status Register REG[010h] Memory Clock Configuration Register REG[018h] CRT/TV Pixel Clock Configuration Register REG[01Eh] CPU To memory Wait State Select Register ...
Page 99
... REG[1F4h] CPU-To-Memory Access Watchdog Timer Register 148 REG[1FCh] Display Mode Register REG[1000h] MediaPlug LCMD Register REG[1004h] MediaPlug CMD Register Hardware Functional Specification Issue Date: 02/04/10 Table 8-2 : S1D13806 Register Set Pg LCD Ink/Cursor Registers 128 REG[071h] LCD Ink/Cursor Start Address Register 129 REG[073h] LCD Cursor X Position Register 1 ...
Page 100
... Page 100 Register REG[1008h] to REG[1FFEh] MediaPlug Data Registers REG[100000h] to REG[1FFFFEh] BitBLT Data Registers S1D13806 X28B-A-001-12 Table 8-2 : S1D13806 Register Set Pg MediaPlug Data Registers 155 BitBLT Data Registers 155 Epson Research and Development Vancouver Design Center Register Pg Hardware Functional Specification Issue Date: 02/04/10 ...
Page 101
... Product Code Bit 5 Bit 4 bits 7-2 Product Code Bits [5:0] This read-only register indicates the product code of the controller. The product code for S1D13806 is 000111b. bits 1-0 Revision Code Bits [1:0] This read-only register indicates the revision code of the controller. The revision code is 00b. Miscellaneous Register ...
Page 102
... When GPIO[n] is configured as an output, writing bit n drives GPIO[n] high and writing this bit drives GPIO[n] low. (n ranges from When GPIO[n] is configured as an input, a read from bit n returns the status of GPIO[n]. (n ranges from S1D13806 X28B-A-001-12 GPIO4 Pin GPIO3 Pin IO Config ...
Page 103
... CONF[4] CONF[3] Config. Status Config. Status MCLK n/a n/a Divide Select GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Status IO Status IO Status CONF[2] CONF[1] CONF[0] Config. Status Config. Status Config. Status MCLK Source MCLK Source n/a Select Bit 1 Select Bit 0 S1D13806 X28B-A-001-12 Page 103 ...
Page 104
... LCD PCLK Divide Select Bits [1:0] These bits determine the divide used to generate the LCD pixel clock from the LCD pixel clock source. LCD PCLK Divide Select Bits S1D13806 X28B-A-001-12 Table 8-4 : MCLK Source Select MCLK Source 00 01 BUSCLK 10 11 ...
Page 105
... Table 8-6 : LCD PCLK Source Selection CRT/TV PCLK Divide n/a Select Bit 0 Table 8-7 : CRT/TV PCLK Divide Selection CRT/TV PCLK Source to DPCLK Frequency LCD PCLK Source CLKI BUSCLK CLKI2 MCLK CRT/TV CRT/TV n/a PCLK Source PCLK Source Select Bit 1 Select Bit 0 Ratio 1:1 2:1 3:1 4:1 X28B-A-001-12 Page 105 RW S1D13806 ...
Page 106
... MediaPlug Clock Divide Select Bits [1:0] These bits determine the divide used to generate the MediaPlug Clock from the MediaPlug Clock source. MediaPlug Clock Divide Select Bits S1D13806 X28B-A-001-12 Table 8-8 : CRT/TV PCLK Source Selection MediaPlug Clock Divide n/a Select Bit 0 Table 8-9 : MediaPlug Clock Divide Selection ...
Page 107
... Wait State Bits [1:0] Hardware Functional Specification Issue Date: 02/04/10 n/a n/a n period (MCLK) - 4ns > period(BCLK) 10 period(MCLK) - 4ns > period(BCLK) 11 MediaPlug Clock Source CLKI BUSCLK CLKI2 MCLK CPU to Memory Wait Memory Wait n/a State Select State Select Bit 1 Condition no restrictions Reserved X28B-A-001-12 Page 107 RW CPU to Bit 0 S1D13806 ...
Page 108
... The default SDRAM refresh rate is based on the MCLK source frequency and is set us- ing REG[21h] bits 2-0. If the refresh rate or MCLK rate is changed, the wait time will be different. Reset Set SDRAM Reset starts Init bit ends min 200 s S1D13806 X28B-A-001-12 n/a n/a n/a Initialization Sequence Starts max 1 ref. period 16 Tmclk Figure 8-1: SDRAM Initialization Sequence ...
Page 109
... Reserved Refresh Rate Refresh Rate Bit 1 Bit 0 SDRAM SDRAM SDRAM Timing Timing Timing Control Bit 2 Control Bit 1 Control Bit 0 SDRAM SDRAM SDRAM Timing Timing Timing Control Bit 10 Control Bit 9 Control Bit 8 REG[02Bh] 01h 12h 13h S1D13806 X28B-A-001-12 Page 109 ...
Page 110
... When this bit = 1, EL Panel support circuit is enabled. When this bit = 0, there is no hardware effect. This bit enables the S1D13806 built-in circuit for EL panels which require the Frame Rate Modulation (FRM) to remain static for one frame every 262143 frames (approximately 1 hour at 60Hz refresh). When this bit is enabled, the need for external circuitry to perform the above function is eliminated ...
Page 111
... TFT must be divisible by 8 MOD Rate Bit MOD Rate Bit MOD Rate Bit 2 1 LCD LCD LCD Horizontal Horizontal Horizontal Display Width Display Width Display Width Bit 2 Bit 1 Bit (32 pixels). S1D13806 X28B-A-001-12 Page 111 ...
Page 112
... FPLINE start position in number of pixels = [(ContentsOfThisRegister) For TFT 2x Data Format at 4/8 bpp color depth: FPLINE start position in number of pixels = [(ContentsOfThisRegister) For TFT 2x Data Format at 16 bpp color depth: FPLINE start position in number of pixels = [(ContentsOfThisRegister) Note REG[034h (REG[035h (REG[036h] bits 3 S1D13806 X28B-A-001-12 LCD LCD Horizontal Horizontal n/a ...
Page 113
... Bit 2 Bit 1 Bit 0 TFT FPLINE Polarity active low active high 8 LCD Vertical LCD Vertical LCD Vertical Display Display Display Height Bit 2 Height Bit 1 Height Bit 0 LCD Vertical LCD Vertical n/a Display Display Height Bit 9 Height Bit 8 S1D13806 X28B-A-001-12 Page 113 ...
Page 114
... For TFT/D-TFD panels only, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the FPFRAME pulse. FPFRAME start position in number of lines = (ContentsOfThisRegister Note (REG[03Ah] bits 5 (REG[03Bh (REG[03Ch] bits 2 S1D13806 X28B-A-001-12 LCD Vertical LCD Vertical Non-Display ...
Page 115
... TFT FPFRAME FPFRAME FPFRAME Pulse Width Pulse Width Pulse Width Bit 2 Bit 1 Bit 0 TFT FPFRAME Polarity active low active high LCD Bit-per- LCD Bit-per- LCD Bit-per- pixel Select pixel Select pixel Select Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 115 RW RW ...
Page 116
... LUT and supports up to 64K colors (4096 colors if dith- ering disabled, see REG[041h] bit 1). TFT/D-TFD panels support up to 64K colors. Bit-per-pixel Select Bits [1:0] 000-001 010 011 100 101 110-111 S1D13806 X28B-A-001-12 Table 8-18: Setting SwivelView Modes SwivelView Normal SwivelView 90° ...
Page 117
... This expands the original 16 shades of color from the FRM logic to 64 shades per RGB component which results in 256K colors per pixel (64x64x64). For the S1D13806, 16 bpp is arranged as 5-6-5 RGB. In this mode, when dithering is enabled, the LUT is bypassed and the original 16-bit data is used as a pointer into the 64 shades per color in the following manner ...
Page 118
... These bits are the LCD display’s 11-bit address offset from the starting word of line “n” to the starting word of line “n + 1”. A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. S1D13806 X28B-A-001-12 LCD Display LCD Display ...
Page 119
... FIFO High Threshold Threshold Bit 5 Bit 4 Bit 3 LCD Pixel LCD Pixel n/a Panning Bit 1 Panning Bit 0 Bits [1:0] Bit 0 --- LCD Display LCD Display LCD Display FIFO High FIFO High FIFO High Threshold Threshold Threshold Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 119 RW RW ...
Page 120
... Horizontal non-display period width in number of pixels = ((ContentsOfThisRegister (ContentsOfThisRegister (ContentsOfThisRegister Note For CRT, the recommended minimum value which should be programmed into this register is 3 (32 pixels). Note REG[052h (REG[053h (REG[054h] bits 3 S1D13806 X28B-A-001-12 ) LCD Display LCD Display FIFO Low FIFO Low Threshold Threshold ...
Page 121
... Pulse Width Bit 3 (REG[053h (REG[054h] bits 3 CRT/TV CRT/TV CRT/TV HRTC Start HRTC Start HRTC Start Position Bit 2 Position Bit 1 Position Bit 0 CRT HRTC CRT HRTC CRT HRTC Pulse Width Pulse Width Pulse Width Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 121 RW RW ...
Page 122
... When a read from this bit = 0, the CRT/TV output vertical display period. bits 6-0 CRT/TV Vertical Non-Display Period Bits [6:0] These bits specify the CRT/TV vertical non-display period height in 1 line resolution. Vertical non-display period height in number of lines = (ContentsOfThisRegister Note (REG[058h] bits 6 S1D13806 X28B-A-001-12 CRT/TV CRT/TV Vertical Vertical Display ...
Page 123
... CRT/TV CRT/TV CRT/TV VRTC Start VRTC Start VRTC Start Position Bit 2 Position Bit 1 Position Bit 0 CRT VRTC CRT VRTC CRT VRTC Pulse Width Pulse Width Pulse Width Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 123 RW RW ...
Page 124
... When this bit = 0, Composite TV signal output is selected. bit 0 TV PAL/NTSC Output Select When this bit = 1, PAL format TV signal output is selected. When this bit = 0, NTSC format TV signal output is selected. This bit must be set to 0 when CRT is enabled. S1D13806 X28B-A-001- DAC Output Luminance ...
Page 125
... Hardware Functional Specification Issue Date: 02/04/10 n/a n/a n/a . Table 8-22 : CRT/TV Bit-per-pixel Selection CRT/TV Bit- CRT/TV Bit- CRT/TV Bit- per-pixel per-pixel per-pixel Select Bit 2 Select Bit 1 Select Bit 0 Color Depth (bpp) Reserved Reserved 4 bpp 8 bpp Reserved 16 bpp Reserved X28B-A-001-12 Page 125 RW S1D13806 ...
Page 126
... These bits are the CRT/TV display’s 11-bit address offset from the starting word of line “n” to the starting word of line “n + 1”. A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. S1D13806 X28B-A-001-12 CRT/TV CRT/TV ...
Page 127
... High High Threshold Threshold Bit 5 Bit 4 Bit 3 CRT/TV Pixel CRT/TV Pixel n/a Panning Bit 1 Panning Bit 0 Bits [1:0] Bit 0 --- CRT/TV CRT/TV CRT/TV Display FIFO Display FIFO Display FIFO High High High Threshold Threshold Threshold Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 127 RW RW ...
Page 128
... REG[070h] n/a n/a bits 1-0 LCD Ink/Cursor Control Bits [1:0] These bits enable the LCD Ink/Cursor circuitry. LCD Ink/Cursor Bits [1:0] Note While in Ink mode, the Cursor X and Y Position registers must be set to 00h. S1D13806 X28B-A-001-12 CRT/TV CRT/TV Display FIFO Display FIFO Low Low Low Threshold ...
Page 129
... Start Address Bit 2 Bit 1 Start Address Memory Size - 1024 Memory Size - n 8192 invalid LCD Cursor X LCD Cursor X LCD Cursor X Position Position Bit 2 Bit 1 LCD Cursor X LCD Cursor X n/a Position Bit 9 X28B-A-001-12 Page 129 RW LCD Bit 0 RW Position Bit 0 RW Position Bit 8 S1D13806 ...
Page 130
... LCD vertical non-display period.The effect of REG[075h] takes place at the next LCD vertical non-display period. LCD Ink/Cursor Blue Color 0 Register REG[076h] n/a n/a bits 4-0 LCD Ink/Cursor Blue Color 0 Bits[4:0] These bits define the blue LCD Ink/Cursor color 0. S1D13806 X28B-A-001-12 LCD Cursor Y LCD Cursor Y Position Position Bit 5 Bit 4 Bit 3 ...
Page 131
... Blue Color 1 Bit 2 Bit 1 Bit 0 LCD LCD LCD Ink/Cursor Ink/Cursor Ink/Cursor Green Color 1 Green Color 1 Green Color 1 Bit 2 Bit 1 Bit 0 LCD LCD LCD Ink/Cursor Ink/Cursor Ink/Cursor Red Color 1 Red Color 1 Red Color 1 Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 131 ...
Page 132
... REG[080h] n/a n/a bits 1-0 CRT/TV Ink/Cursor Control Bits [1:0] These bits enable the CRT/TV Ink/Cursor circuitry. CRT/TV Ink/Cursor Bits [1:0] Note While in Ink mode, the Cursor X and Y Position registers must be set to 00h. S1D13806 X28B-A-001-12 LCD Ink/Cursor n/a n/a FIFO High Threshold Bit 3 FIFO High Threshold Bits [3:0] ...
Page 133
... Start Address Bit 2 Bit 1 Start Address Memory Size - 1024 Memory Size - n 8192 Invalid CRT/TV CRT/TV Cursor X Cursor X Position Bit 2 Position Bit 1 Position Bit 0 CRT/TV n/a Cursor X Position Bit 9 Position Bit 8 X28B-A-001-12 Page 133 RW CRT/TV Bit 0 RW CRT/TV Cursor X RW CRT/TV Cursor X S1D13806 ...
Page 134
... CRT/TV Ink/Cursor select registers. Note The effect of REG[082h] through REG[084h] takes place only after REG[085h]is writ- ten to and at the next CRT/TV vertical non-display period.The effect of REG[085h] takes place at the next CRT/TV vertical non-display period. S1D13806 X28B-A-001-12 CRT/TV CRT/TV Cursor Y Cursor Y ...
Page 135
... Red Color 0 Bit 2 Bit 1 Bit 0 CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Blue Color 1 Blue Color 1 Blue Color 1 Bit 2 Bit 1 Bit 0 CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Green Color 1 Green Color 1 Green Color 1 Bit 2 Bit 1 Bit 0 S1D13806 X28B-A-001-12 Page 135 ...
Page 136
... CRT/TV Ink/Cursor FIFO High Threshold Register REG[08Eh] n/a n/a bits 3-0 CRT/TV Ink/ These bits are used to optimize the display memory request arbitration for the Hardware Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in hardware. S1D13806 X28B-A-001-12 CRT/TV CRT/TV Ink/Cursor Ink/Cursor n/a Red Color 1 Red Color 1 ...
Page 137
... BitBLT FIFO Not Full Status Empty Status (REG[100h] Bit 5) (REG[100h] Bit BitBLT n/a Destination Source Linear Linear Select State Idle Reserved Initiating operation Number of Words available in BitBLT FIFO X28B-A-001-12 Page 137 RW BitBLT Select S1D13806 ...
Page 138
... BitBLT Color Format Select This bit selects the color format that the 2D operation is applied to. When this bit = 0, 8 bpp (256 color) format is selected. When this bit = 1, 16 bpp (64K color) format is selected. S1D13806 X28B-A-001-12 n/a Reserved n/a Epson Research and Development ...
Page 139
... (Whiteness) BitBLT ROP BitBLT ROP BitBLT ROP Code Code Code Bit 2 Bit 1 Bit 0 Start Bit Position for Color Expansion bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 S1D13806 X28B-A-001-12 Page 139 RW ...
Page 140
... Other combinations Note The BitBLT operations Pattern Fill with ROP and Pattern Fill with transparency require a BitBLT width depths. The BitBLT width is set in REG[110h], REG[111h]. S1D13806 X28B-A-001-12 BitBLT n/a n/a Operation Bit 3 Table 8-31 : BitBLT Operation Selection Write BitBLT with ROP. ...
Page 141
... Pattern Base Address[20:0] 8 bpp BitBLT Source Start Address[20:6] 16 bpp BitBLT Source Start Address[20:7] Note For further information on the BitBLT Source Start Address register, see the S1D13806 Programming Notes and Examples, document number X28B-G-003-xx. Hardware Functional Specification Issue Date: 02/04/10 BitBLT BitBLT ...
Page 142
... REG[10Dh] bits 2-0 These bits are the display’s 11-bit address offset from the starting word of line n to the starting word of line They are used only for address calculation when the BitBLT is configured as a rectangular region of memory. S1D13806 X28B-A-001-12 BitBLT BitBLT ...
Page 143
... BitBLT Height Bit 5 Bit 4 Bit 3 n/a n/a n/a BitBLT Width BitBLT Width BitBLT Width Bit 2 Bit 1 Bit 0 BitBLT Width BitBLT Width n/a Bit 9 Bit 8 BitBLT Height BitBLT Height BitBLT Height Bit 2 Bit 1 Bit 0 BitBLT Height BitBLT Height n/a Bit 9 Bit 8 S1D13806 X28B-A-001-12 Page 143 ...
Page 144
... REG[119h] bits 7-0 A 16-bit register that specifies the BitBLT foreground color for Color Expansion or Solid Fill. For 16 bpp color depths (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depths (REG[101h] bit 0 = 0), only bits 7-0 are used. S1D13806 X28B-A-001-12 BitBLT BitBLT ...
Page 145
... Bit 6 bits 7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13806 has three 256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 12, “Look-Up Table Architecture” on page 161 for details. This register selects which LUT entry is read/write accessible through the LUT Data Reg- ister (REG[1E4h]) ...
Page 146
... This bit must be set to 1. bit 0 Power Save Mode Enable When this bit = 1, power save mode is enabled. When this bit = 0, power save mode is disabled. Note For details on Power Save Mode, see Section 19, “Power Save Mode” on page 202. S1D13806 X28B-A-001-12 LUT Data n/a Bit 1 Bit 0 n/a ...
Page 147
... When this bit = 0, the memory controller is powered up and is in normal mode. Note When this bit reads a 1, the system may safely shut down the memory clock source. Hardware Functional Specification Issue Date: 02/04/10 n/a n/a n/a Page 147 RO Memory LCD Power Controller n/a Save Status Power Save Status S1D13806 X28B-A-001-12 ...
Page 148
... CPU-to-memory access cycle time in order gain higher CPU bandwidth. Doing so may significantly reduce the available display refresh bandwidth which may cause display corruption. This register does not affect CPU-to-register access or BitBLT access. S1D13806 X28B-A-001-12 Mem. Access Mem. Access ...
Page 149
... Display Mode Select Bit 2 Select Bit 1 Select Bit 0 ™ Modes SwivelView 180° SwivelView 270° Display Mode Enabled no display LCD only CRT only EISD (CRT and LCD) TV with flicker filter off TV with flicker filter on X28B-A-001-12 Page 149 RW S1D13806 ...
Page 150
... MediaPlug Registers Descriptions The S1D13806 has built-in support for Winnov’s MediaPlug connection designed for video cameras. The following registers are used to control the connection and accept data from the camera. The MediaPlug registers decode A11-A0 and require A20 = 0 and A12 = 1. The MediaPlug registers are 16-bit wide. Byte access to the MediaPlug registers is not allowed. For further information, see Section 17, “ ...
Page 151
... Hardware Functional Specification Issue Date: 02/04/10 Table 8-37: Timeout Option Delay Timeout (MediaPlug clock cycles) 00 1023 (default 128 11 64 Remote Powered Status [bit 5] 0 cable connected but remote not powered 1 cable connected and remote powered x cable not connected Status X28B-A-001-12 Page 151 S1D13806 ...
Page 152
... When this bit = 0, power to remote is off (default). When this bit =1, power to remote is on. bit 0 Watchdog Disable When this bit = 0, the MediaPlug watchdog is enabled (default). When this bit = 1, the MediaPlug watchdog is disabled. S1D13806 X28B-A-001-12 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/04/10 ...
Page 153
... CMD Bit 11 D14 D13 D12 D11 I[12:5] T I[10: I[4:0] I[4:0] LCMD Bit 18 LCMD Bit 17 LCMD Bit 16 LCMD Bit 26 LCMD Bit 25 LCMD Bit 24 CMD Bit 2 CMD Bit 1 CMD Bit 0 CMD Bit 10 CMD Bit 9 CMD Bit 8 D10 C[2:0] C[2:0] S1D13806 X28B-A-001-12 Page 153 RW RW ...
Page 154
... CMD Bit 29 REG[1006h] bits 15-0 MediaPlug Reserved CMD Bits [15:0] This register is not implemented and is reserved for future expansion of the CMD register. A write to this register has no hardware effect. A read from this register always return 0000h. S1D13806 X28B-A-001-12 Table 8-40: MediaPlug Commands Command CMD Bit 20 ...
Page 155
... Data Bit 2 Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 12 Data Bit 11 Data Bit 10 Page 155 RW Data Bit 1 Data Bit 0 Data Bit 9 Data Bit 8 RW Data Bit 1 Data Bit 0 Data Bit 9 Data Bit 8 S1D13806 X28B-A-001-12 ...
Page 156
... Page 156 9 2D BitBLT Engine 9.1 Overview The S1D13806 is designed with a built-in 2D BitBLT engine which increases the perfor- mance of Bit Block Transfers (BitBLT). It supports 8 and 16 bit-per-pixel color depths. The BitBLT engine supports rectangular and linear addressing modes for source and desti- nation in a positive direction for all BitBLT operations except the move BitBLT which also supports in a negative direction ...
Page 157
... Buffer Addressing”). The display buffer can contain an image buffer, one or more Ink Layer/Hardware Cursor buffers, and a dual panel buffer. Hardware Functional Specification Issue Date: 02/04/10 Table 10-1 : S1D13806 Addressing M/R# Register access - see Section 8.2, “Register Mapping” on page 97 . • REG[000h] is addressed when AB[12: • ...
Page 158
... Calculating the size of the dual panel buffer is required to avoid overwriting the Hardware Cursor/Ink Layer buffer. Example 1: For a 800x600 color panel the dual panel buffer size is 120,000 bytes. S1D13806 X28B-A-001- for monochrome panel With a 1280k byte display buffer, the dual panel buffer resides from 12 2b40h to 13 FFFFh ...
Page 159
... RGB value from LUT Index Panel Display 4-0 5 Panel Display , B represent the red, green, and blue color n n Page 159 , 4-0 ) S1D13806 X28B-A-001-12 ...
Page 160
... For CRT/TV: (REG[057h], REG[056h]) define the height of the CRT/TV display. Image Buffer Starting Word (REG[044h], REG[043h], REG[042h]) Starting Pixel of Word (REG[048h]) Screen Width of Virtual Image (REG[047h], REG[046h]) S1D13806 X28B-A-001-12 LCD Display Height of LCD Display ((REG[039h], REG[038h lines Line 0 Line 1 Screen Width of LCD Display ((REG[032h ...
Page 161
... Figure 12-1: 4 Bit-Per-Pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date: 02/04/10 Green Look-Up Table 256x4 4-bit Grey Data: 03 1010 (0Ah Page 161 FRM BLOCK Output to display = unused Look-Up Table entries S1D13806 X28B-A-001-12 ...
Page 162
... Figure 12-2: 8 Bit-Per-Pixel Monochrome Mode Data Output Path 16 Bit-Per-Pixel Monochrome Mode A color depth of 16 bpp is required to achieve 64 gray shades in monochrome mode. In this mode the LUT is bypassed and the green component of the pixel is mapped to the FRM. S1D13806 X28B-A-001-12 Green Look-Up Table 256x4 00 ...
Page 163
... Blue Look-Up Table 256x4 4-bit Blue Data: 03 1111 (0Fh Page 163 FRM BLOCK Output to display = unused Look-Up Table entries S1D13806 X28B-A-001-12 ...
Page 164
... Figure 12-4: 8 Bit-Per-Pixel Color Mode Data Output Path 16 Bit-Per-Pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode – Section 11, “Display Configuration” on page 159. S1D13806 X28B-A-001-12 Red Look-Up Table 256x4 00 01 ...
Page 165
... The required clock frequencies for NTSC/PAL are given in the following table. Table 13-1 : Required Clock Frequencies for NTSC/PAL TV Format Hardware Functional Specification Issue Date: 02/04/10 Required Clock Frequency NTSC 14.318180 MHz (3.579545 MHz subcarrier) PAL 17.734475 MHz (4.43361875 MHz subcarrier) Page 165 S1D13806 X28B-A-001-12 ...
Page 166
... TV display to reduce flickering. This filter is controlled using the Display Mode register (REG[1FCh] bits [2:1]). Note When TV with anti-flicker filter is enabled, the Flicker Filter Clock Enable bit (REG[18h] bit 7) must be set to 1. S1D13806 X28B-A-001-12 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
Page 167
... RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. Hardware Functional Specification Issue Date: 02/04/10 Parameter RGB N.A. N.A. Page 167 NTSC / PAL NTSC / PAL (mv) (IRE) 996 99.5 923 89 798 72 725 62 608 45 536 35 410 17 338 7.3 284 0 0 -40 S1D13806 X28B-A-001-12 ...
Page 168
... Cyan negative peak cyan V2 Green negative peak green V2 Magenta negative peak magenta V2 Red negative peak red V2 Blue negative peak blue Note RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. S1D13806 X28B-A-001-12 V1 cyan V1 V1 green magenta V1 yellow V2 yellow V2 V2 green magenta ...
Page 169
... NTSC / PAL (mv) NTSC / PAL (IRE) 1211 130 1202 128 1065 109 948 93 939 92 699 58 995 99 923 89 797 72 725 62 608 45 535 35 411 18 338 7.3 634 49 392 15 384 14 267 -2.6 130 -22 122 -23 284 0 426 / 415 142 / 153 -20 / -19 0 -40 X28B-A-001-12 Page 169 S1D13806 ...
Page 170
... The maximum and minimum register values for these registers are given in Table 13-5, “Minimum and Maximum Values for NTSC/PAL TV”. Increasing the HRTC Start Position moves the image left, while increasing the VRTC Start Position moves the image up. S1D13806 X28B-A-001-12 Epson Research and Development 8) + (((REG[052] bits[5:0]) ...
Page 171
... NTSC PAL max min max 510 215 511 752 624 920 t2 - 158 215 484 370 572 127 (128) 26 (27) 127 (128 X28B-A-001-12 Page 171 Units T 4SC T 4SC T 4SC T LINE T LINE T LINE S1D13806 ...
Page 172
... TV Horizontal Non-Display Period TV HRTC Start Position TV Vertical Display Height TV Vertical Non-Display Period TV Vertical Start Position 13.4.2 TV Cursor Operation See Section 14, “Ink Layer/Hardware Cursor Architecture” on page 173. S1D13806 X28B-A-001-12 752 x 484 696 x 436 NTSC NTSC Register 752x484 696x436 640x480 920x572 856x518 800x572 640x480 ...
Page 173
... Ink Layer buffer between the 1280K - image and dual panel buffers; (n 8192) • position a Hardware Cursor buffer between the image and dual panel buffers; • select from a multiple of Hardware Cursor buffers. Invalid Page 173 Comments S1D13806 X28B-A-001-12 ...
Page 174
... Ink/Cursor data format for a little endian system. 2-bpp: Byte 0 Byte 1 Host Address The image data for pixel Color Color 0 01 Color 1 10 Background 11 Inverted Background S1D13806 X28B-A-001-12 bit 7 bit ...
Page 175
... REG[072h]) and REG[073h] bit (REG[075h] bits [1:0], REG[074h]) and REG[075h] bit For CRT/TV (REG[083h] bits [1:0], REG[082h]) and REG[083h] bit (REG[085h] bits [1:0], REG[084h]) and REG[085h] bit Hardware Functional Specification Issue Date: 02/04/10 P(0;0) P(x;y) P(x+63;y) P(x;y+63) P(x+63;y+63) Figure 14-2: Unclipped Cursor Positioning Page 175 S1D13806 X28B-A-001-12 ...
Page 176
... REG[072h]) <= 63 and REG[073h] bit (REG[075h] bits [1:0], REG[074h]) <= 63 and REG[075h] bit For CRT/TV (REG[083h] bits [1:0], REG[082h]) <= 63 and REG[083h] bit (REG[085h] bits [1:0], REG[084h]) <= 63 and REG[085h] bit S1D13806 X28B-A-001-12 P(-x;-y) P(0;0) P(63-x;63-y) Figure 14-3: Clipped Cursor Positioning ...
Page 177
... SwivelView uses a 1024 1024 pixel virtual window. The following figures show how the display buffer memory map changes in 90° SwivelView. The display is refreshed in the following sense: C–A–D–B. The application image is written to the S1D13806 in the following sense: A–B–C–D. The S1D13806 rotates and stores the application image in the following sense: C– ...
Page 178
... Memory Address Offset The LCD/CRT Memory Address Offset register (REG[046h], REG[047h] for LCD, or REG[066h], REG[067h] for CRT) must be set for a 1024 pixel offset: LCD/CRT Memory Address Offset (words) S1D13806 X28B-A-001-12 display address 90° ...
Page 179
... Minimum Required Image Buffer (bytes) where H is the height of the panel in number of lines. Hardware Functional Specification Issue Date: 02/04/10 = (1024 - W) for 16 bpp color depth = (1024 - for 8 bpp color depth = (1024 H) 2 for 16 bpp color depth = (1024 H) for 8 bpp color depth Page 179 S1D13806 X28B-A-001-12 ...
Page 180
... The programmer also should not read/write to the memory beyond the maximum accessible horizontal virtual size because that memory is either reserved for the dual panel buffer or not associated with any real memory at all. S1D13806 X28B-A-001-12 =( ...
Page 181
... Vancouver Design Center The following table summarizes the SwivelView 90° and 270° memory requirements for different panel sizes and display modes. Note that the S1D13806 memory size is 1280K byte. The calculation of the minimum required image buffer size is based on the image buffer and the dual panel buffer only ...
Page 182
... Cursor or the Ink Layer buffer. • For 90° SwivelView modes, BitBLT (Bit Block Transfer) operations are still supported. However, the BitBLT data must first be rotated by software. For further information, refer to the S1D13806 Programmers Notes And Examples, document number X28B-G-003-xx. 15.3 180° SwivelView 180° ...
Page 183
... Hardware Cursor and Ink Layer images are not rotated – software rotation must be used. • CRT/TV mode is not supported. • For 180° SwivelView modes, BitBLT (Bit Block Transfer) operations are supported normally. For further information, refer to the S1D13806 Programmers Notes And Examples, document number X28B-G-003-xx. 15.4 270° SwivelView 270° ...
Page 184
... Increment/decrement LCD Display Start Address register in 16 bpp color depth scrolls the display window up/down by 1 line. • Increment/decrement LCD Pixel Panning register in 8 bpp color depth scrolls the display window down/ line. S1D13806 X28B-A-001-12 270° Rotation on CPU Read/Write to Display Buffer ...
Page 185
... CRT/TV display buffer. • For 270° SwivelView modes, BitBLT (Bit Block Transfer) operations are still supported. However, the BitBLT data must first be rotated by software. For further information, refer to the S1D13806 Programmers Notes And Examples, document number X28B-G-003-xx. Hardware Functional Specification ...
Page 186
... Page 186 16 EPSON Independent Simultaneous Display (EISD) EPSON Independent Simultaneous Display (EISD) allows the S1D13806 to display independent images on two different displays (LCD panel and CRT or TV). 16.1 Registers The LCD panel timings and mode setup are programmed through the Panel Configuration Registers (REG[03Xh]) and the LCD Display Mode Registers (REG[04Xh]). The CRT/TV timings and mode setup are programmed through the CRT/TV Configuration Registers (REG[05Xh]) and the CRT/TV Display Mode Registers (REG[06Xh]) ...
Page 187
... Bandwidth Limitation When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth available to the S1D13806. The result is that display modes with a high resolution or color depth may not be supported. In some cases, Ink Layers may not be possible on one or both of the displays. EISD increases the total demand for display refresh bandwidth and reduces CPU bandwidth, resulting in lower CPU performance ...
Page 188
... Table 4-9, “Summary of Power-On/Reset Options,” on page 33. 17.3 MediaPlug Interface Pin Mapping The S1D13806 provides 8 pins for use by the MediaPlug interface (VMP[7:0]). GPIO12 is also used as the MediaPlug power control output pin (VMPEPWR) when the MediaPlug interface is enabled. The following table lists the MediaPlug pin mapping when the interface is enabled ...
Page 189
... REG[039h] bits [1:0], REG[038h] bits [7: LCD Vertical Non-Display Period = REG[03Ah] bits [5: LCD Horizontal Display Width = ((REG[032h] bits [6:0 LCD Horizontal Non-Display Period = ((REG[034h] bits [4:0 minimum LCD pixel clock (LPCLK) period = 1 for single panel = 2 for dual panel max + LVNDP n 8Ts 8Ts S1D13806 X28B-A-001-12 Page 189 ...
Page 190
... CRT Frame Rate Calculation The maximum CRT frame rate is calculated using the following formula. max. CRT Frame Rate Where: CPCLKmax = maximum CRT pixel clock frequency CVDP CVNDP CHDP CHNDP Ts S1D13806 X28B-A-001-12 CPCLK = --------------------------------------------------------------------------------------------------------- - CHDP + CHNDP CVDP = CRT Vertical Display Height = REG[057h] bits [1:0], REG[056h] bits [7: ...
Page 191
... TV Vertical Non-Display Period = REG[058h] bits [6: Horizontal Display Width = ((REG[050h] bits [6:0 Horizontal Non-Display Period = for NTSC output use ((REG[052h] bits [5:0]) = for PAL output use ((REG[052h] bits [5:0]) = minimum TV pixel clock (TPCLK) period Page 191 + TVNDP + 0.5 8Ts 8Ts 8Ts S1D13806 X28B-A-001-12 ...
Page 192
... Example Frame Rates with Ink Layer Enabled S1D13806 X28B-A-001-12 max max min min CRT/ Frame PCLK HNDP VNDP Rate TV (MHz) (lines) (pixels) (Hz 119 118.1 ...
Page 193
... S1D13806 X28B-A-001-12 Frame Rate (Hz) 85.0 85.0 85 ...
Page 194
... Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[07Eh] = 0Ch. 2. REG[08Eh] = 0Ah. S1D13806 X28B-A-001-12 max max min min CRT/ Frame PCLK HNDP VNDP Rate TV (MHz) (lines) (pixels) ...
Page 195
... CRT Yes 1024 -- -- -- -- CRT Yes 1024 Page 195 Horiz Vert PCLK HNDP VNDP Res Res bpp (lines) (pixels) (MHz) (lines) (pixels) 1024 768 4 65 320 41 1024 768 8 65 320 41 768 4 65 320 41 768 8 65 320 41 S1D13806 X28B-A-001-12 Frame Rate (Hz) 59.8 59.8 59.8 59.8 ...
Page 196
... Passive Yes 640 480 Single Mono Passive Yes 640 480 2 Dual Color Passive Yes 640 480 Dual Example Frame Rates with Ink Layer Enabled S1D13806 X28B-A-001-12 max max min min CRT/ Frame PCLK HNDP VNDP Rate TV (MHz) (lines) (pixels) (Hz) ...
Page 197
... Ink PCLK HNDP VNDP Rate TV (MHz) (lines) (pixels) (Hz) 9. 58.4 CRT Yes 19 73.9 CRT Yes Page 197 Horiz Vert PCLK( HNDP VNDP Res Res bpp (lines) MHz) (pixels) (lines) (pixels) 640 480 16 25.18 160 44 640 480 8 25.18 160 44 S1D13806 X28B-A-001-12 Frame Rate (Hz) 60.1 60.1 ...
Page 198
... Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[04Ah] = 30h. REG[06Ah] = 30h. REG[04Bh] = 3Ch. REG[06Bh] = 3Ch. 2. REG[04Ah] = 1Ah. REG[06Bh] = 25h. 3. REG[06Ah] = 23h. REG[08Eh] = 0Ch. 4. REG[08Eh] = 0Ch. S1D13806 X28B-A-001-12 max max min min CRT/ Frame PCLK HNDP ...
Page 199
... Res bpp (lines) (pixels) (MHz) (lines) (pixels) 1024 768 8 65 320 41 1024 768 8 65 320 41 1024 768 8 65 320 41 1024 768 8 65 320 41 1024 768 8 65 320 41 1024 768 8 65 320 41 1024 768 8 65 320 41 S1D13806 X28B-A-001-12 Frame Rate (Hz) 59.8 59.8 59.8 59.8 59.8 59.8 59.8 ...
Page 200
... Yes 640 480 Color Passive Dual Yes 640 480 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[07Eh] = 0Ch. S1D13806 X28B-A-001-12 max max min min CRT/ Frame PCLK HNDP VNDP Rate ...