AD9877 Analog Devices, AD9877 Datasheet
AD9877
Available stocks
Related parts for AD9877
AD9877 Summary of contents
Page 1
... AD8321/AD8325 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers via the MxFE SPORT. The AD9877 is available in a 100-lead MQFP package. It offers enhanced receive path undersampling performance and lower cost compared to the pin-compatible AD9873. The AD9877 is specified over the extended industrial (−40°C to +85°C) temperature range ...
Page 2
... AD9877 TABLE OF CONTENTS Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 Transmit Section......................................................................... 13 Clock and Oscillator Circuitry ................................................. 14 Programmable Clock Output REFCLK................................... 15 Reset and Transmit Power-Down ............................................ 16 Σ-Δ Outputs ................................................................................ 17 Register Map and Bit Definitions ................................................. 18 Register 0x00— ...
Page 3
... Updated Format.................................................................. Universal Changed OSCOUT to REFCLK....................................... Universal Changed REF CLK to REFCLK........................................ Universal Changes to Specifications.................................................................4 Changes to Figure 24 ......................................................................23 Updated Outline Dimensions........................................................35 Changes to Ordering Guide...........................................................35 7/02—Rev Rev. A Edits to ORDERING GUIDE ..........................................................5 Edits to RESET AND TRANSMIT POWER-DOWN section..17 Revision 0: Initial Version Rev Page AD9877 ...
Page 4
... AD9877 SPECIFICATIONS V = 3.3 V ± 5 3.3 V ± 10 OSCIN derived from PLL ( 4.02 kΩ, maximum fine gain, 75 Ω DAC load. MCLK SET Table 1. Parameter SYSTEM CLOCK DAC SAMPLING, f SYSCLK Frequency Range ( Frequency Range ( OSCIN and XTAL CHARACTERISTICS Frequency Range ...
Page 5
... Full II 71.0 Full II 61.1 Full II 9.9 Full II 61.5 Full II Full II 69.9 25°C III 25°C III 25°C III 25°C III 25°C III 25°C III Rev Page AD9877 Typ Max Unit 47.3 dB 7.6 Bits −60.1 −50.0 dB 63.0 dB ±10 +100 mV 12 Bits 33 MHz 5.5 ADC cycles 2 Vppd 4||2 kΩ||pF 2.0 ns 1.2 ps rms ...
Page 6
... AD9877 Parameter TIMING CHARACTERISTICS (10 pF Load) Wake-Up Time Minimum RESET Pulse Width Low ( Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency (f ) MCLK TxSYNC/TxIQ Setup Time ( TxSYNC/TxIQ Hold Time ( MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (t REFCLK Rising or Falling Edge to RxSYNC/RxIQ/IF Valid ...
Page 7
... Rev Page Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial operating temperature range (−40°C to +85°C). Parameter is guaranteed by design and/or characterization testing. Parameter is a typical value only. Test level definition is not applicable. AD9877 ...
Page 8
... PIN 1 AD9877 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Mnemonic Description AVDD 12-Bit ADC Analog 3.3 V Supply. DRGND Pin Driver Digital Ground. DRVDD Pin Driver Digital 3.3 V Supply. DGND Digital Ground. ...
Page 9
... Differential Input to I ADC. Q IN−, Q IN+ Differential Input to Q ADC. REFB8 8-Bit ADC Decoupling Node. REFT8 8-Bit ADC Decoupling Node. REFB12 12-Bit ADC Decoupling Node. REFT12 12-Bit ADC Decoupling Node. IF12−, IF12+ Differential Input to IF ADC. Rev Page AD9877 ...
Page 10
... AD9877 TYPICAL PERFORMANCE CHARACTERISTICS MHz OSCIN 4.02 kΩ mA), and 75 Ω DAC load, unless otherwise noted. OSCIN SET OUT TYPICAL POWER CONSUMPTION CHARACTERISTICS Transmitted 20 MHz single tone, unless otherwise noted. 340 320 300 280 260 240 220 ...
Page 11
... Figure 12. 12-Bit ADC SFDR vs. Input Frequency f OSCIN PLL (MHz) IN Figure 13. 12-Bit ADC ENOBs vs. Input Frequency PLL f OSCIN (MHz) IN Figure 14. 12-Bit ADC THD vs. Input Frequency AD9877 9 5 105 9 5 105 9 5 105 ...
Page 12
... AD9877 TERMINOLOGY Aperture Delay The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance. It specifies the time delay between the rising edge of the sampling clock input and when the input signal is held for conversion. Aperture Uncertainty (Jitter) Aperture jitter is the variation in aperture delay for successive samples ...
Page 13
... THEORY OF OPERATION To gain a general understanding of the AD9877, refer to the block diagram of the device architecture in Figure 15. The following is a general description of the device functionality. Later sections will detail each of the data path building blocks. TRANSMIT SECTION Modulation Mode Operation The AD9877 accepts 6-bit words that are strobed synchronous to the master clock, MCLK, into the data assembler ...
Page 14
... The AD9877 provides for a 26-bit frequency tuning word, which results in a tuning resolution of 3 216 MHz. A good rule when using the AD9877 as a frequency synthesizer is to limit the fundamental output frequency to 30 ...
Page 15
... PROGRAMMABLE CLOCK OUTPUT REFCLK The AD9877 provides a frequency-programmable clock output REFCLK (Pin 71). OSCIN or MCLK (f MCLK clock divider ratio R stored in Register Address 0x01 determine its frequency. 1 AVDD PIN 1 DRGND 2 DRVDD 3 (MSB) IF(11) 4 IF(10) 5 IF(9) 6 IF(8) 7 IF(7) 8 IF(6) 9 IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 (MSB) RxIQ(3) 16 RxIQ(2) 17 RxIQ(1) 18 RxIQ(0) ...
Page 16
... Power-Up Sequence On initial power-up, the RESET pin should be held low until the power supply is stable. Once RESET is deasserted, the AD9877 can be programmed over the serial port recommended that the PWRDN pin be held low during the reset. Changes to ADC Clock Select (Register 0x08) or SYS Clock Divider N (Register 0x01) should be programmed before the rising edge of PWRDN ...
Page 17
... OUTPUTS The AD9877 contains two independent Σ-Δ outputs that provide a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the programmed code, as shown in Figure 19. These bit streams can be low-pass filtered to generate programmable dc voltages (Σ ...
Page 18
... AD9877 REGISTER MAP AND BIT DEFINITIONS 1 Table 4. Register Map Address (Hex) Bit 7 Bit 6 Bit 5 0x00 SDIO LSB First RESET Bidirectional 0x01 PLL Lock SYSCLK Detect Divider Default) 0x02 Power- Power- Power-Down Down PLL Down Digital Tx DAC Tx 0x03 Σ-Δ Output [0] Control Word [3:0] LSB ...
Page 19
... M, the clock multiplier value. After the recapture time of the PLL, the frequency of f For timing integrity, certain restrictions on the values of M and N apply when both AD9877 transmit and receive paths are used. The supported modes are shown in Table 5. Table 5. ADC Clock Select ...
Page 20
... FTW < 0 × 2000000. Changes to FTW bytes take effect immediately. Cable Driver Gain Control The AD9877 has a three-pin interface to the AD832x family of programmable gain cable driver amplifiers. This allows direct control of the cable driver’s gain through the AD9877. In its default mode, the complete 8-bit register value is transmitted over the 3-wire CA interface ...
Page 21
... Bits [3:0]. coarse is the decimal value of Bits [7:8 the level at AD9877 output in dBmV for fine = 0. 9877( the level at output of the AD8327 in dBmV. 8327 V is the level at output of the AD8322 in dBmV. 8322 Rev ...
Page 22
... AD9877. Single or multiple byte transfers are supported. Also, the interface can be programmed to read words either MSB first or LSB first. The serial interface port I/O of the AD9877 can be configured to have one bidirectional I/O (SDIO) pin or two unidirectional I/O (SDIO/SDO) pins. ...
Page 23
... When this bit is set default low, the AD9877 serial port is in MSB-first format. In MSB-first mode, the instruction byte and data bytes must be written from the MSB to the LSB. In MSB- first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. ...
Page 24
... The alternate form yields an indeterminate form (0/0) for but . NYQ is otherwise identical. The only variable parameter for the CIC filter of the AD9877 and n are fixed at 1 and 3, respectively. Thus, the CIC system function for the AD9877 simplifies ...
Page 25
... To keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of 2 prior to representing it to the AD9877. With- out oversampling, the Nyquist bandwidth of the baseband data corresponds to the f ...
Page 26
... AD9877 10 0 –10 –20 –30 –40 –50 –60 –70 –80 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (f S Figure 29. Response to Input Signal Spectrum ( –1 –2 –3 –4 –5 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY RELATIVE TO I/Q NYQUIST BW Figure 30. Cascaded Filter Pass-Band Detail ( –10 –20 –30 –40 –50 –60 – ...
Page 27
... AD9877. Data transmit latency through the AD9877 is easiest to describe in terms of f when an effect is first seen after an input value changes. Latency of I/Q data entering the data assembler (AD9877 input) to the DAC output is 119 values applied to the data assembler input take up to 176 ...
Page 28
... For example Ω terminated input/output low-pass filter will look like a 25 Ω load to the AD9877. The output compliance voltage of the AD9877 is −0 +1 avoid signal distortion, any signal developed at the DAC output should not exceed 1.5 V. Furthermore, the signal may extend below ground as much as 0 ...
Page 29
... Power-Up and Hardware Reset—Upon initial power-up and every hardware reset, the AD9877 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9877 writes all 0s out of the 3-wire cable amplifier control interface. 2. ...
Page 30
... OSCIN divider is programmed (M when the ADC sampling is selected to be derived from f DRIVING THE ANALOG INPUTS Figure 40 illustrates the equivalent analog inputs of the AD9877 (a switched capacitor input). Bringing CLK to a logic high opens Switch S3 and closes Switches S1 and S2. The input source is connected to AIN and must charge capacitor C during this time ...
Page 31
... Analog Devices amplifier product offerings. AINP ADC DIFFERENTIAL INPUTS AINN The AD9877 uses p-p input span for the 8-bit ADC inputs and p-p for the 12-bit ADC. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion ...
Page 32
... ADC VOLTAGE REFERENCES /n ) other than 2 1 The AD9877 has two independent internal references for its 8-bit and 12-bit ADCs. Both 8-bit ADCs have p-p input and share one internal reference source. The 12-bit ADC, however, is designed for 2 V p-p input voltages and provides its 2 ) effectively steps up own internal reference ...
Page 33
... The board has four layers: two signal layers, one ground plane, and one power plane. The power plane is split into a 3 VDD section used for the 3 V analog supply pins of the AD9877 and a VANLG section that supplies the higher voltage analog components on the board. ...
Page 34
... AD9877 SIGNAL ROUTING The digital Rx and Tx signal paths should be kept as short as possible. Also, these traces should have a controlled impedance of about 50 Ω. This prevents poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. If the signal traces cannot be kept shorter than approximately 1.5 inches, then series termination resistors (33 Ω ...
Page 35
... BSC 0° LEAD PITCH 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MS-022-GC-1 Figure 44. 100-Lead Metric Quad Flat Package [MQFP] (S-100-3) Dimensions shown in millimeters Package Description 100-Lead Metric Quad Flat Package [MQFP] Evaluation Board Rev Page AD9877 51 50 14.00 BSC 12.35 REF 17.20 BSC 31 30 0.40 0.22 LEAD WIDTH ...
Page 36
... AD9877 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02716-0-6/05(B) Rev Page ...