AT73C501 ATMEL Corporation, AT73C501 Datasheet
AT73C501
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AT73C501 Summary of contents
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... Single +5V Supply Description A two chip solution, consisting of AT73C500 and AT73C501 (or AT73C502), offers all main features required for the measurement and calculation of various power and energy quantities in static Watt-hour meters. The devices operate according to IEC1036, class 1, specification. IEC 687, class 0.5 and 0.2 requirements are fulfilled when used with external temperature compensated voltage reference ...
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Figure 1. Block diagram of the AT73C500 chipset in stand-alone configuration VDA VDDA VCC VREF BGD AT73501 VI1 VI2 SIX SINGLE-ENDED, VI3 INDEPENDENT SIGMA-DELTA CI1 CONVERTERS CI2 CI3 L1 RESET MODE VSA VSSA ...
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... Pin Description AT73C501 Single-ended ADC Figure 3. PLCC-28 package pin layout XO XI CLK CLKR ACK BGD VCC 7 8 PFAIL AGND 9 VCIN 10 11 VREF VSSA VDDA AIN2 AIN4 AIN6 AIN1 AIN3 Power Supply Pins Pin I/O Description VDDA 13 PWR ...
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AT73C502 Differential-Ended ADC Figure 4. QFP-44 package pin layout XI CLK CLKR XO N/C N/C N BGD VCC 3 VCC 4 PFAIL 5 AGND 6 VCIN 7 VREF 8 IADJUST ...
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... I/O P Bus, Bit0 Pin I/O Description Serial Output, used clock for EEPROM Serial Output, used as Chip Select (CS) for AT73C501 5 O and as Data Input (DI) for EEPROM Serial Data Input, data from SIN 33 I AT73C501 or from EEPROM Serial Clock Input, bit clock ...
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... If higher sampling rate is selected, the meter constant will also be increased by the same ratio. The three current inputs of AT73C501 are fed from second- ary outputs of current transformers, from Hall sensors or other similar sensors. In differential-ended applications, such as with current shunt resistors, the AT73C502 ADC can be used ...
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... PFAIL. To assure reliable power-down pro- cedure after voltage break, the V must be equipped with a 470 F or larger capacitor. AT73C500 AT73C500 performs power and energy calculations. It also controls the interfacing to the AT73C501 (or AT73C502) and to an external microprocessor. The block diagram of the DSP is presented below. GAIN CALIBRATION ...
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... AT73C500 reads through a bus during the initialization pro AT73C501/AT73C502 is independent of the mode selected. Mode Number Mode Bit 2 ...
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Measurements and Calculations The first operation performed by AT73C500 is digital high- pass filtering. The purpose of the filtering is to remove the DC offset of both current and voltage samples. From offset free samples, active power is calculated phase-by-phase ...
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... higher, erroneous frequency results may be obtained. The voltage registers (REG19-REG21) are scaled so that full scale sinusoidal input signal at AT73C501/AT73C502 voltage channels will produce 7A8BH value into voltage registers. This means that the resolution of the registers is about 8.6 mV. Accordingly, full scale current will produce 7DA4H to current registers (REG22-REG24) providing a resolution of about 2 ...
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It is recommended that 50 Hz meters are operated from 3.2768MHz crystal system, a 3.93216 MHz clock is normally used. Because the clock frequency generates a time reference for energy calculations, the content of energy registers and ...
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Output Operations The data output by AT73C500 can be divided into three categories: data to external processor, status information and impulse outputs. AT73C500 reads mode information, and in mode 3 and 4, also calibration data via external bus. For the ...
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PACKAGE 2 Byte Data Order Meaning 1 Sync LS Single byte Synchronization 2 Sync MS Single byte Synchronization 3 Mode Single byte Mode information 4 Status Single byte Status information 5 REG6 LS byte Apparent power, phase 1 6 REG6 ...
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PACKAGE 4 Byte Data Order Meaning 1 Sync LS Single byte Synchronization 2 Sync MS Single byte Synchronization 3 Mode Single byte Mode information 4 Status Single byte Status information Reactive energy, 5 REG15 LS byte capacitive load Reactive energy, ...
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The six data packages arrive as follows: Figure 9. Data transfer to processor in six packages 20 ms 200ms = 655360 clocks @ 3.2768 MHz Pack Pack Pack DATRDY LINE PERIOD normal mode, ...
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Figure 11. Contents of a data package 45 clock cycles LATCHED DATRDY CLK STROBE Sync LS Sync MS Synchronisation data AT73C500 offers some time for the processor to analyze the synchronization, status and mode information before starting to supply the ...
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... FAIL flag signifies that something abnormal has been detected. The following situations may cause a high level of FAIL: read operation of calibration coefficients is not suc- cessful, the serial bus of AT73C501 or AT73C502 is not working properly, the measurement results can't be trans- ferred to microprocessor, AT73C500 has detected an inter- nal failure ...
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... This mode can be used for initial calibration purposes special meter for additional processing of sample data. In 100imp/kVArh this mode, AT73C501/AT73C502 samples the six inputs 100imp/kVArh normally and transfers the samples to AT73C500, which performs DC suppression and further writes the samples to 8-bit processor bus together with header bytes in the fol- lowing sequence ...
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Calibration The calibration coefficients always have to be loaded into AT73C500 registers after reset state. The coefficients are either read from an external EEPROM or supplied by a microprocessor via the 8-bit bus. Loading of Calibration Coefficients In modes 3 ...
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The calibration data is transferred in the following sequence: Byte Calibration Coefficient 0 PC1 2 PC2 4 PC3 6 MCC 8 Not used 10 AGC1 12 AGC2 14 AGC3 16 RGC1 18 RGC2 20 RGC3 22 UGC1 24 UGC2 26 ...
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... AT73C501/AT73C502 sample output. During the initializa- tion phase, the ADC interface has to be disabled. This can be done by B8 bit of AT73C500 Status bus (ADDR0). The output has to be latched by an external flip-flop to keep the state over the whole initialization period ...
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The nominal full-scale values are 270V 80A FS Q 270V 80A = FS The valid range for the offset calibration factors is -128 to +127. The scale of offset calibration for active and ...
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... XI input from a separate clock source. The system clock ----------- - 77.143 A = kWh AT73C501/AT73C502 and is fed to the CLK input of the device from the CLK output of AT73C501/AT73C502. 140V E 0.4Wh 0.20741 = ...
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... Measurement Accuracy The accuracy measurements are based on the usage of Max Unit AT73C501. Using the differential-ended ADC, AT73C502, 5.25 V improves some of the results. Input Conditions V DD ...
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The measurements are done according to IEC1036 specifi- cation. The results are averaged over a period of 10s. Before measurements, AT73C500 devices have been operational for minimum 1h. Measurement Bandwidth Parameter Min General line frequency - high limit ...
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Frequency Current 0.95f ...1.05f 0. 0.95f ...1.05f 0. 0.8f ...5f 0. 0.8f ...5f 0. Current th 40 harmonic in current Current 0.1I B Current 0.1I B ...
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... Starting Current As default, the starting current is based on 5A basic current and 80A full scale current range. Starting Current Voltage Min U N Temperature Coefficient Measured with the internal reference voltage source of AT73C501/AT73C502. Mean Temperature Coefficient Power Current Voltage Factor Min 0.1I ...I U 1.000 ...
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... Addr Hold Time From Rising Edge of STROBE RWSU RD/WR Setup to Rising Edge of STROBE RWH RD/WR Hold from Rising Edge of STROBE BRS BRDY Set-Up Time to Rising Edge of Clock Power Supply Characteristics Parameter (AT73C501/AT73C502 + DD AT73C500) I (ADC GND V -A REF GND AT73C500 28 Min 4 ...