ATMEGA128L ATMEL Corporation, ATMEGA128L Datasheet

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ATMEGA128L

Manufacturer Part Number
ATMEGA128L
Description
Manufacturer
ATMEL Corporation
Datasheet
Features
High-performance, Low-power AVR
Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 128K Bytes of In-System Self-programmable Flash program memory
– 4K Bytes EEPROM
– 4K Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V for ATmega128L
– 4.5 - 5.5V for ATmega128
Speed Grades
– 0 - 8 MHz for ATmega128L
– 0 - 16 MHz for ATmega128
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Summary
Rev. 2467PS–AVR–08/07

Related parts for ATMEGA128L

ATMEGA128L Summary of contents

Page 1

... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega128L – 4.5 - 5.5V for ATmega128 • Speed Grades – MHz for ATmega128L – MHz for ATmega128 ® 8-bit Microcontroller (1) 8-bit Microcontroller with 128K Bytes In-System ...

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Pin Figure 1. Pinout ATmega128 Configurations (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 Note: Overview The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single ...

Page 3

Block Diagram Figure 2. Block Diagram PF0 - PF7 VCC GND PORTF DRIVERS DATA REGISTER PORTF REG. PORTF AVCC ADC AGND AREF PROGRAM JTAG TAP COUNTER PROGRAM ON-CHIP DEBUG FLASH BOUNDARY- INSTRUCTION SCAN REGISTER PROGRAMMING PEN INSTRUCTION LOGIC DECODER CONTROL ...

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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in ...

Page 5

ATmega103 By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103 Compatibility Mode regards to RAM, I/O pins and interrupt vectors as described above. However, some new fea- tures in ATmega128 are not available in this compatibility ...

Page 6

The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega128 as listed on ATmega103 compatibility mode, ...

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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 51. Shorter pulses are not guaranteed ...

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Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years ...

Page 9

Register Summary Address Name Bit 7 ($FF) Reserved – .. Reserved – ($9E) Reserved – ($9D) UCSR1C – ($9C) UDR1 ($9B) UCSR1A RXC1 ($9A) UCSR1B RXCIE1 ($99) UBRR1L ($98) UBRR1H – ($97) Reserved – ($96) Reserved – ($95) UCSR0C – ...

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Register Summary (Continued) Address Name Bit 7 ($61) DDRF DDF7 ($60) Reserved – $3F ($5F) SREG I $3E ($5E) SPH SP15 $3D ($5D) SPL SP7 $3C ($5C) XDIV XDIVEN $3B ($5B) RAMPZ – $3A ($5A) EICRB ISC71 $39 ($59) EIMSK ...

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Register Summary (Continued) Address Name Bit 7 $01 ($21) PINE PINE7 $00 ($20) PINF PINF7 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. ...

Page 12

Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 13

Instruction Set Summary (Continued) Mnemonics Operands Description BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD ...

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Instruction Set Summary (Continued) Mnemonics Operands Description SEV Set Twos Complement Overflow. CLV Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in ...

Page 15

... Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2467PS–AVR–08/07 Ordering Code Package ATmega128L-8AC 64A ATmega128L-8MC 64M1 ATmega128L-8AI 64A (2) ATmega128L-8AU 64A ATmega128L-8MI 64M1 (2) ATmega128L-8MU 64M1 ATmega128-16AC 64A ATmega128-16MC 64M1 ATmega128-16AI 64A (2) ATmega128-16AU 64A ATmega128-16MI ...

Page 16

Packaging Information 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...

Page 17

Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R 2467PS–AVR–08/07 ...

Page 18

Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev. M • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer ...

Page 19

Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior ...

Page 20

Stabilizing time needed when changing XDIV Register After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The NOP instruction ...

Page 21

Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg- ister triggers an unexpected EEPROM interrupt ...

Page 22

Assembly Code Example: CLI OUT NOP NOP NOP NOP NOP NOP NOP NOP SEI 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device ...

Page 23

First Analog Comparator conversion may be delayed If the device is powered by a slow rising V take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator ...

Page 24

IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround – – – 6. Reading EEPROM by using ST or STS ...

Page 25

I bit in the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute 8 NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly. Assembly Code Example: CLI ...

Page 26

ATmega128 Rev. F • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • Stabilizing time needed when changing OSCCAL ...

Page 27

Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior ...

Page 28

Datasheet Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Revision History Changes from Rev. 1. Updated 2467O-10/ Added Rev. ...

Page 29

Changes from Rev. 1. Removed “analog ground”, replaced by “ground”. 2467L-05/ Updated Rev. Table 132 on page 2467M-11/04 3. Added note to 4. Updated Changes from Rev. 1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ...

Page 30

Added a proposal for solving problems regarding the JTAG instruction IDCODE in “Errata” on page Changes from Rev. 1. Corrected the names of the two Prescaler bits in the SFIOR Register. 2467G-09/ Added Chip Erase as a ...

Page 31

Corrected typo (WGM-bit setting) for: “Fast PWM Mode” on page 99 “Phase Correct PWM Mode” on page 101 “Fast PWM Mode” on page 151 “Phase Correct PWM Mode” on page 153 8. Corrected 9. Corrected 10. Updated Vil parameter ...

Page 32

Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02 ATmega128(L) 32 10. Updated Programming Figures: Figure 135 on page 290 and Figure 144 on page 301 AVCC must be connected during Programming mode. added to illustrate how to program the fuses. 11. ...

Page 33

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...

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