CS5012A-KP7 Cirrus Logic, Inc., CS5012A-KP7 Datasheet

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CS5012A-KP7

Manufacturer Part Number
CS5012A-KP7
Description
Manufacturer
Cirrus Logic, Inc.
Datasheet

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Features
http://www.cirrus.com
Monolithic CMOS A/D Converters
True 12-bit, 14-bit, and 16-bit Precision
Conversion Times
Linearity Error:
Self-calibration Maintains Accuracy
Low Power Consumption
Low Distortion
– Microprocessor Compatible
– Parallel & Serial Output
– Inherent Track/Hold Input
– CS5016: 16.25 µs
– CS5014: 14.25 µs
– CS5012A: 7.20 µs
– Guaranteed No Missing Codes
– Accurate Over Time & Temperature
– 150 mW
I
16-, 14-, & 12-bit Self-calibrating A/D Converters
REFBUF
CLKIN
AGND
VREF
AIN
23
32
31
29
30
HOLD CS
±
1
0.001% FS
24
Generator
VA+
+
+
+
Clock
-
-
-
28
RD
25
A0 BP/UP RST BW INTRLV CAL
26
VA-
34
27
Copyright © Cirrus Logic, Inc. 2005
Calibration
Memory
36
Control
(All Rights Reserved)
VD+
Redistribution
37
12
Charge
DAC
38
CS5012A CS5014 CS5016
The CS5012A/14/16 are 12-, 14-, and 16-bit mono-
lithic analog to digital converters with conversion
times of 7.2 µs, 14.25 µs and 16.25 µs. Unique self-
calibration circuitry ensures excellent linearity and
differential nonlinearity, with no missing codes. Off-
set and full-scale errors are kept within 1/2 LSB
(CS5012A/14) and 1 LSB (CS5016), eliminating the
need for calibration. Unipolar and bipolar input
ranges are digitally selectable.
The pin compatible CS5012A/14/16 consist of a
DAC, conversion and calibration microcontroller,
oscillator, comparator, microprocessor-compatible
3-state I/O, and calibration circuitry. The input
track-and-hold, inherent to the devices’ sampling
architecture, acquires the input signal after each
conversion using a fast-slewing, on-chip buffer am-
plifier. This allows throughput rates up to
100 kSps(CS5012A),
50 kSps (CS5016).
ORDERING INFORMATION
See
VD-
Description
39
40
“Ordering Information” on page39.
EOT EOC SCLK SDATA
Microcontroller
41
Status Register
DGND
+
-
11
42
Comparator
43
TST
35
44
56 kSps
10
14
16
17
18
19
20
21
22
3
4
5
6
7
8
2
D0 (LSB) CS5016
D1
D2 (LSB) CS5014
D3
D4 (LSB) CS5012A
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)
(CS5014),
AUG ‘05
DS14F9
and

Related parts for CS5012A-KP7

CS5012A-KP7 Summary of contents

Page 1

... VA+ http://www.cirrus.com CS5012A CS5014 CS5016 Description The CS5012A/14/16 are 12-, 14-, and 16-bit mono- lithic analog to digital converters with conversion times of 7.2 µs, 14.25 µs and 16.25 µs. Unique self- calibration circuitry ensures excellent linearity and differential nonlinearity, with no missing codes. Off- set and full-scale errors are kept within 1/2 LSB (CS5012A/14) and 1 LSB (CS5016), eliminating the need for calibration ...

Page 2

... CS5012A ANALOG CHARACTERISTICS VA-, VD- = -5V; VREF = 2.5V to 4.5V; f Parameter* Specified Temperature Range Accuracy Linearity Error Drift Differential Linearity Drift Full Scale Error Drift Unipolar Offset Drift Bipolar Offset Drift Bipolar Negative Full-Scale Error(Note 1) Drift Total Unadjusted Error Drift Dynamic Performance (Bipolar Mode) Peak Harmonic or ...

Page 3

... Measured from falling transition on HOLD to falling transition on EOC. 6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions. The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock. ...

Page 4

... MIN Min (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 2) (Note 1) (Note 2) (Note (Note 3) CS5012A CS5014 CS5016 CS5014 VA+, VD+ = 5V; MAX CS5014-B Typ Max -40 to +85 ±1/4 ±1/2 ±1/8 ±1/4 ±1/2 ±1/32 ±1/2 ±1 ±1/4 ±1/4 ±3/4 ± ...

Page 5

... DC Power Supply Currents Power Dissipation Power Supply Rejection Positive Supplies Negative Supplies DS14F8 DS14F9 (continued) Min (Note 4) (Note 6) (Note 6) 55.6 (Note 7) (Note 7) (Note 8) CS5012A CS5014 CS5016 CS5014 CS5014 Typ Max -40 to +85 25 100 275 375 165 220 14.25 3.0 3. -19 3 ...

Page 6

... Typ Max Min 0 to +70 (Note 1) (Note (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 2) (Note 1) 100 85 90 (Note 3) CS5012A CS5014 CS5016 CS5016 VA+, VD+ = 5V; MAX CS5016 Typ Max Min Typ Max -40 to +85 -55 to +125 0.001 0.0015 ±1/4 16 ±2 ±3 ±1 ±1 ± ...

Page 7

... DS14F8 DS14F9 (continued) CS5016-J, K CS5016-A, B Min Typ Max Min 0 to +70 25 100 (Note 4) (Note 6) (Note 6) 50 (Note 7) (Note 7) 120 250 (Note 8) CS5012A CS5014 CS5016 CS5016 CS5016-S, T Typ Max Min Typ Max -40 to +85 -55 to +125 25 25 100 100 275 375 165 220 16.25 3.0 3.75 ...

Page 8

... Any Digital Output t 1/f hpw CLK CS5012A t 49/f c 57/f CS5014 CS5016 65 (Note 11) t 4/f epw CLK pwl t pwh t 2/f ss CLK t 2/f sh CLK CS5012A, CS5014, CS5016 Min Typ Max - - - +50 - 53/f +235 CLK CLK - 61/f +235 CLK ...

Page 9

... Rise and Fall Times t pwl t pwh Serial Output Timing Hi Read and Calibration Control Timing t hpw t c LAST CONVERSION DATA VALID Conversion Timing CS5012A, CS5014, CS5016 Hi epw t dd NEW DATA VALID 2-15 9 ...

Page 10

... Unipolar Bipolar Notes: 13. All voltages with respect to ground. 14. The CS5012A/14/16 can accept input voltages up to the analog supplies (VA+ and VA-). It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode and -VREF in bipolar mode. ...

Page 11

... CS5016: Bit 15 Bit 14 Bit 13 MSB THEORY OF OPERATION The CS5012A/14/16 family utilize a successive approximation conversion technique. The analog input is successively compared to the output of a D/A converter controlled by the conversion algo- rithm. Successive approximation begins by comparing the analog input to the DAC output which is set to half-scale (MSB on, all other bits off) ...

Page 12

... LSB resulting in nearly ideal differential and integral linearity. DIGITAL CIRCUIT CONNECTIONS The CS5012A/14/16 can be applied in a wide va- riety of master clock, sampling, and calibration conditions which directly affect the devices’ con- version time and throughput. The devices also ...

Page 13

... CLKIN cycles µ µ plus 2.25 s (1.32 s for the CS5012A -7 version only). This adds to the conversion time to define the converter’s maximum throughput. The con- version time of the CS5012A/14/16, in turn, depends on the sampling, calibration, and CLKIN conditions ADDR VALID AN Address ...

Page 14

... HOLD Input EOC Output Acquisition EOT Output * Dashed line: CS & CS5012A Solid line: See Figure 9 Figure 5b. Synchronous (Loopback Mode) Synchronous Sampling To achieve maximum throughput, sampling can be synchronized with the internal conversion clock by connecting the End-of-Track (EOT) out- put to HOLD (Figure 3b). The EOT output falls ...

Page 15

... However, the voltage reference input should have stabilized to within 5 0.25% of its final value, for the CS5012A/14/16 respectively, before RST falls to guarantee an ac- curate calibration. Later, the CS5012A/14/16 may be reset at any time to initiate a single full cali- bration ...

Page 16

... CS5012A and one calibration per 72,051 conversions in the CS5014 and CS5016). This is initiated by bringing both the INTRLV input and CS low (or hard-wiring INTRLV low), interleave extends the CS5012A/14/16’ ...

Page 17

... S7 CALIBRATING To interface with a 16-bit data bus, the BW input to the CS5012A/14/16 should be held high and all data bits (12, 14 and 16 for the CS5012A, CS5014 and CS5016 respectively) read in paral- lel on pins D4-D15 (CS5012A), D2-D15 (CS5014), or D0-D15 (CS5016). With an 8-bit bus, the converter’s result must be read in two portions. In this instance, BW should be held low and the 8 MSB’ ...

Page 18

... Microprocessor Independent Operation The CS5012A/14/16 can be operated in a stand- alone mode independent of intelligent control. In this mode, CS and RD are hard-wired low. This permanently enables the 3-state output buffers and allows transparent latch inputs (CAL and INTRLV active. A free-running condition is established when BW is tied high, CAL is tied low, and HOLD is continually strobed low or tied to EOT. The CS5012A/14/16’ ...

Page 19

... CLKIN fre- quency. At full speed, the reference must supply a maximum load current of 10 µ typical). For the CS5012A an output im- pedance of 15 Ω will therefore yield a maximum error of 150 mV. With a 2.5V reference and LSB size of 600 mV, this would insure better than 1/4 µ ...

Page 20

... The recommended refer- ence voltage is between 2.5 and 4.5 V for the CS5012A and 4.5 V for the CS5014/16. The CS5012A/14/16 can actually accept reference voltages up to the positive analog supply. How- ever, the buffer’s offset may increase as the reference voltage approaches VA+ thereby in- creasing external drive requirements at VREF ...

Page 21

... CS5012A is capable of slewing at 20V/ CS5014/16 can slew at 5V/µs. In bipolar mode, only half the capacitor array is connected to the analog input so the CS5012A can slew at 40V/ -16 and the CS5014/16 can slew at 10V/µs. After the first six CLKIN cycles, the CS5012A will slew at µ ...

Page 22

... Grounding and Power Supply Decoupling The CS5012A/14/16 use the analog ground con- nection, AGND, only as a reference voltage power currents flow through the AGND con- nection, and it is completely independent of DGND. However, any noise riding on the AGND input relative to the system’ ...

Page 23

... The CS5012A/14/16 calibrate all bits in the capacitor array to a small fraction of an LSB resulting in nearly ideal DNL. Histo- gram plots of typical DNL of the CS5012A/14/16 can be seen in Figures 14, 15, 16. A histogram test is a statistical method of deriv- ing an A/D converter’s differential nonlinearity. A ...

Page 24

... F igur e 14. C S5012A Differ ential Nonlinear ity Plot +1 +1 +1 2-30 2,048 Codes 8,192 Codes F igur e 15. C S5014 Differ ential Nonlinear ity Plot 32,768 Codes F igur e 16. C S5016 Differ ential Nonlinear ity Plot CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 4,095 16,383 65,535 DS14F9 DS14F8 ...

Page 25

... FFT Tests and Windowing In the factory, the CS5012A/14/16 are tested us- ing Fast Fourier Transform (FFT) techniques to analyze the converter’s dynamic performance. A pure sinewave is applied to the CS5012A/14/16, and a " ...

Page 26

... Figure 17. Plot of Ideal 12-bit ADC 0.0 -20.0 -40.0 Signal Amplitude Relative to -60.0 Full Scale (dB) -80.0 -100.0 -120.0 12.0 dc Input Frequency (kHz) Figure 19. FFT Plot of CS5012A with 12 kHz Full-Scale Input 0dB -20dB -40dB -60dB Signal Amplitude Relative to -80dB Full Scale -100dB -120dB dc Input Frequency Figure 20. Plot of Ideal 14-bit ADC ...

Page 27

... Input Frequency (kHz) CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 0dB Sampling Rate: 50 kHz Full Scale: 9V p-p S/(N+D): 92 kHz dc Input Frequency Full Scale Input CS5012A-KP7 tested un =100 kSps CS5012A VREF Signal 1. 4.5 FS-0.5dB 2. 2.5 FS-0.5dB 3. 4.5 FS-6.0dB 4. 2.5 FS-6.0dB 4 3 ...

Page 28

... In a sampled data system all information about the analog input applied to the sample/hold appears in the baseband from dc to one-half the sampling rate. This includes high-frequency components which alias into the baseband. Low-pass (anti-alias) filters CS5012A, CS5014, CS5016 Sampling Rate: 56 kHz Full Scale: 9V p-p S/(N+D): 24 kHz ...

Page 29

... HOLD input falls. It need only acquire the analog input by the time the entire conversion cycle finishes. CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 and the analog input voltage ...

Page 30

... External 4MHz Figure 35. Examples of Measured Clock Feedthrough If sampling is performed asynchronously with the master clock, clock feedthrough will appear error at the CS5014/16’s output. With a fixed CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 0dB Sampling Rate: 56 kHz Full Scale: 9V p-p S/(N+D): 64 kHz dc Input Frequency ...

Page 31

... LSB. This reduction in calibration resolution for the CS5012A reduces the time re- quired to calibrate the device (see Table 3) and reduces the size of the total array capacitance. The reduced array capacitance improves the high frequency performance by allowing higher slew rate in the input circuitry ...

Page 32

... CS and HOLD low software reset will result. +5V Analog Supply 0.1 µF Analog 200 Ω Signal Signal Conditioning Source 1000 pF 0 VREF ±VREF Voltage Reference 0.01 µF 10 µF 0.1 µ F -5V Analog Supply Figure 36. CS5012A/14/16 System Connection Diagram 32 DS14F8 INTRLV ...

Page 33

... HOLD DGND VD D10 D11 D12 D13 D14 D15 DS14F9 CS5012A CS5014 CS5016 CS5012A 10 CS5014 11 CS5016 Top View SDATA SCLK EOC EOT VD- ...

Page 34

... DGND. Digital Inputs HOLD – Hold, PIN 1. A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion. This input must remain low at least one CLKIN cycle plus 50 ns. CS – Chip Select, PIN 24. When high, the data bus outputs are held in a high impedance state and the input to CAL and INTRLV are ignored ...

Page 35

... CAL is latched low again. Calibration picks up where the previous calibration left off, and calibration cycles complete every 58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/ the device is converting when a calibration is signaled, it will wait until that conversion completes before beginning ...

Page 36

... Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid until the next bit appears. SCLK – Serial Clock Output, PIN 43. Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the rising edge of SCLK. Analog Outputs REFBUF – ...

Page 37

... The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction temperature of the device. 2-44 DS14F9 CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 DS14F8 37 ...

Page 38

... PACKAGE DIMENSIONS D2/E2 38 CS5012A CS5014 CS5016 44 pin PLCC E E1 DIM MIN A 4.20 A1 2.29 B 0.33 D/E 17.40 D1/E1 16.51 D2/E2 14. NO. OF TERMINALS MILLIMETERS INCHES NOM MAX MIN NOM MAX 4.45 4.57 0.165 0.175 0.180 2.79 3.04 0.090 0.110 0.120 0.41 0.53 0.013 0.016 0.021 17.53 17.65 0.685 0.690 0.695 16.59 16.66 0.650 0.653 0.656 15.50 16.00 0.590 0.610 ...

Page 39

... S/N Ratio Linearity 16.25 µ 0.0015% Peak Relfow Temp 225 °C 260 °C 225 °C 260 °C 225 °C 260 °C CS5012A CS5014 CS5016 Temperature Package -40 to +85 °C 44-pin PLCC Temperature Package -40 to +85 °C 44-pin PLCC MSL Rating* Maximum Floor Life 2 2 ...

Page 40

... AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks o service marks of their respective owners. 40 www.cirrus.com CS5012A CS5014 CS5016 DS14F9 ...

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